1 /* 2 * (C) Copyright 2014 3 * Dirk Eibach, Guntermann & Drunck GmbH, eibach@gdsys.de 4 * 5 * SPDX-License-Identifier: GPL-2.0+ 6 */ 7 8 #include <common.h> 9 #include <hwconfig.h> 10 #include <i2c.h> 11 #include <spi.h> 12 #include <libfdt.h> 13 #include <fdt_support.h> 14 #include <pci.h> 15 #include <mpc83xx.h> 16 #include <fsl_esdhc.h> 17 #include <asm/io.h> 18 #include <asm/fsl_serdes.h> 19 #include <asm/fsl_mpc83xx_serdes.h> 20 21 #include "mpc8308.h" 22 23 #include <gdsys_fpga.h> 24 25 #include "../common/adv7611.h" 26 #include "../common/ch7301.h" 27 #include "../common/dp501.h" 28 #include "../common/ioep-fpga.h" 29 #include "../common/mclink.h" 30 #include "../common/osd.h" 31 #include "../common/phy.h" 32 #include "../common/fanctrl.h" 33 34 #include <pca953x.h> 35 #include <pca9698.h> 36 37 #include <miiphy.h> 38 39 DECLARE_GLOBAL_DATA_PTR; 40 41 #define MAX_MUX_CHANNELS 2 42 43 enum { 44 MCFPGA_DONE = 1 << 0, 45 MCFPGA_INIT_N = 1 << 1, 46 MCFPGA_PROGRAM_N = 1 << 2, 47 MCFPGA_UPDATE_ENABLE_N = 1 << 3, 48 MCFPGA_RESET_N = 1 << 4, 49 }; 50 51 enum { 52 GPIO_MDC = 1 << 14, 53 GPIO_MDIO = 1 << 15, 54 }; 55 56 unsigned int mclink_fpgacount; 57 struct ihs_fpga *fpga_ptr[] = CONFIG_SYS_FPGA_PTR; 58 59 struct { 60 u8 bus; 61 u8 addr; 62 } strider_fans[] = CONFIG_STRIDER_FANS; 63 64 int fpga_set_reg(u32 fpga, u16 *reg, off_t regoff, u16 data) 65 { 66 int res; 67 68 switch (fpga) { 69 case 0: 70 out_le16(reg, data); 71 break; 72 default: 73 res = mclink_send(fpga - 1, regoff, data); 74 if (res < 0) { 75 printf("mclink_send reg %02lx data %04x returned %d\n", 76 regoff, data, res); 77 return res; 78 } 79 break; 80 } 81 82 return 0; 83 } 84 85 int fpga_get_reg(u32 fpga, u16 *reg, off_t regoff, u16 *data) 86 { 87 int res; 88 89 switch (fpga) { 90 case 0: 91 *data = in_le16(reg); 92 break; 93 default: 94 if (fpga > mclink_fpgacount) 95 return -EINVAL; 96 res = mclink_receive(fpga - 1, regoff, data); 97 if (res < 0) { 98 printf("mclink_receive reg %02lx returned %d\n", 99 regoff, res); 100 return res; 101 } 102 } 103 104 return 0; 105 } 106 107 int checkboard(void) 108 { 109 char *s = getenv("serial#"); 110 bool hw_type_cat = pca9698_get_value(0x20, 18); 111 112 puts("Board: "); 113 114 printf("Strider %s", hw_type_cat ? "CAT" : "Fiber"); 115 116 if (s != NULL) { 117 puts(", serial# "); 118 puts(s); 119 } 120 121 puts("\n"); 122 123 return 0; 124 } 125 126 int last_stage_init(void) 127 { 128 int slaves; 129 unsigned int k; 130 unsigned int mux_ch; 131 unsigned char mclink_controllers_dvi[] = { 0x3c, 0x3d, 0x3e }; 132 #ifdef CONFIG_STRIDER_CPU 133 unsigned char mclink_controllers_dp[] = { 0x24, 0x25, 0x26 }; 134 #endif 135 bool hw_type_cat = pca9698_get_value(0x20, 18); 136 #ifdef CONFIG_STRIDER_CON_DP 137 bool is_dh = pca9698_get_value(0x20, 25); 138 #endif 139 bool ch0_sgmii2_present = false; 140 141 /* Turn on Analog Devices ADV7611 */ 142 pca9698_direction_output(0x20, 8, 0); 143 144 /* Turn on Parade DP501 */ 145 pca9698_direction_output(0x20, 10, 1); 146 pca9698_direction_output(0x20, 11, 1); 147 148 ch0_sgmii2_present = !pca9698_get_value(0x20, 37); 149 150 /* wait for FPGA done, then reset FPGA */ 151 for (k = 0; k < ARRAY_SIZE(mclink_controllers_dvi); ++k) { 152 unsigned int ctr = 0; 153 unsigned char *mclink_controllers = mclink_controllers_dvi; 154 155 #ifdef CONFIG_STRIDER_CPU 156 if (i2c_probe(mclink_controllers[k])) { 157 mclink_controllers = mclink_controllers_dp; 158 if (i2c_probe(mclink_controllers[k])) 159 continue; 160 } 161 #else 162 if (i2c_probe(mclink_controllers[k])) 163 continue; 164 #endif 165 while (!(pca953x_get_val(mclink_controllers[k]) 166 & MCFPGA_DONE)) { 167 udelay(100000); 168 if (ctr++ > 5) { 169 printf("no done for mclink_controller %d\n", k); 170 break; 171 } 172 } 173 174 pca953x_set_dir(mclink_controllers[k], MCFPGA_RESET_N, 0); 175 pca953x_set_val(mclink_controllers[k], MCFPGA_RESET_N, 0); 176 udelay(10); 177 pca953x_set_val(mclink_controllers[k], MCFPGA_RESET_N, 178 MCFPGA_RESET_N); 179 } 180 181 if (hw_type_cat) { 182 miiphy_register(bb_miiphy_buses[0].name, bb_miiphy_read, 183 bb_miiphy_write); 184 for (mux_ch = 0; mux_ch < MAX_MUX_CHANNELS; ++mux_ch) { 185 if ((mux_ch == 1) && !ch0_sgmii2_present) 186 continue; 187 188 setup_88e1514(bb_miiphy_buses[0].name, mux_ch); 189 } 190 } 191 192 /* give slave-PLLs and Parade DP501 some time to be up and running */ 193 udelay(500000); 194 195 mclink_fpgacount = CONFIG_SYS_MCLINK_MAX; 196 slaves = mclink_probe(); 197 mclink_fpgacount = 0; 198 199 ioep_fpga_print_info(0); 200 201 if (!adv7611_probe(0)) 202 printf(" Advantiv ADV7611 HDMI Receiver\n"); 203 204 #ifdef CONFIG_STRIDER_CON 205 if (ioep_fpga_has_osd(0)) 206 osd_probe(0); 207 #endif 208 209 #ifdef CONFIG_STRIDER_CON_DP 210 if (ioep_fpga_has_osd(0)) { 211 osd_probe(0); 212 if (is_dh) 213 osd_probe(4); 214 } 215 #endif 216 217 #ifdef CONFIG_STRIDER_CPU 218 ch7301_probe(0, false); 219 dp501_probe(0, false); 220 #endif 221 222 if (slaves <= 0) 223 return 0; 224 225 mclink_fpgacount = slaves; 226 227 #ifdef CONFIG_STRIDER_CPU 228 /* get ADV7611 out of reset, power up DP501, give some time to wakeup */ 229 for (k = 1; k <= slaves; ++k) 230 FPGA_SET_REG(k, extended_control, 0x10); /* enable video */ 231 232 udelay(500000); 233 #endif 234 235 for (k = 1; k <= slaves; ++k) { 236 ioep_fpga_print_info(k); 237 #ifdef CONFIG_STRIDER_CON 238 if (ioep_fpga_has_osd(k)) 239 osd_probe(k); 240 #endif 241 #ifdef CONFIG_STRIDER_CON_DP 242 if (ioep_fpga_has_osd(k)) { 243 osd_probe(k); 244 if (is_dh) 245 osd_probe(k + 4); 246 } 247 #endif 248 #ifdef CONFIG_STRIDER_CPU 249 if (!adv7611_probe(k)) 250 printf(" Advantiv ADV7611 HDMI Receiver\n"); 251 ch7301_probe(k, false); 252 dp501_probe(k, false); 253 #endif 254 if (hw_type_cat) { 255 miiphy_register(bb_miiphy_buses[k].name, 256 bb_miiphy_read, bb_miiphy_write); 257 setup_88e1514(bb_miiphy_buses[k].name, 0); 258 } 259 } 260 261 for (k = 0; k < ARRAY_SIZE(strider_fans); ++k) { 262 i2c_set_bus_num(strider_fans[k].bus); 263 init_fan_controller(strider_fans[k].addr); 264 } 265 266 return 0; 267 } 268 269 /* 270 * provide access to fpga gpios (for I2C bitbang) 271 * (these may look all too simple but make iocon.h much more readable) 272 */ 273 void fpga_gpio_set(unsigned int bus, int pin) 274 { 275 FPGA_SET_REG(bus, gpio.set, pin); 276 } 277 278 void fpga_gpio_clear(unsigned int bus, int pin) 279 { 280 FPGA_SET_REG(bus, gpio.clear, pin); 281 } 282 283 int fpga_gpio_get(unsigned int bus, int pin) 284 { 285 u16 val; 286 287 FPGA_GET_REG(bus, gpio.read, &val); 288 289 return val & pin; 290 } 291 292 #ifdef CONFIG_STRIDER_CON_DP 293 void fpga_control_set(unsigned int bus, int pin) 294 { 295 u16 val; 296 297 FPGA_GET_REG(bus, control, &val); 298 FPGA_SET_REG(bus, control, val | pin); 299 } 300 301 void fpga_control_clear(unsigned int bus, int pin) 302 { 303 u16 val; 304 305 FPGA_GET_REG(bus, control, &val); 306 FPGA_SET_REG(bus, control, val & ~pin); 307 } 308 #endif 309 310 void mpc8308_init(void) 311 { 312 pca9698_direction_output(0x20, 26, 1); 313 } 314 315 void mpc8308_set_fpga_reset(unsigned state) 316 { 317 pca9698_set_value(0x20, 26, state ? 0 : 1); 318 } 319 320 void mpc8308_setup_hw(void) 321 { 322 immap_t *immr = (immap_t *)CONFIG_SYS_IMMR; 323 324 /* 325 * set "startup-finished"-gpios 326 */ 327 setbits_be32(&immr->gpio[0].dir, (1 << (31-11)) | (1 << (31-12))); 328 setbits_be32(&immr->gpio[0].dat, 1 << (31-12)); 329 } 330 331 int mpc8308_get_fpga_done(unsigned fpga) 332 { 333 return pca9698_get_value(0x20, 20); 334 } 335 336 #ifdef CONFIG_FSL_ESDHC 337 int board_mmc_init(bd_t *bd) 338 { 339 immap_t *immr = (immap_t *)CONFIG_SYS_IMMR; 340 sysconf83xx_t *sysconf = &immr->sysconf; 341 342 /* Enable cache snooping in eSDHC system configuration register */ 343 out_be32(&sysconf->sdhccr, 0x02000000); 344 345 return fsl_esdhc_mmc_init(bd); 346 } 347 #endif 348 349 static struct pci_region pcie_regions_0[] = { 350 { 351 .bus_start = CONFIG_SYS_PCIE1_MEM_BASE, 352 .phys_start = CONFIG_SYS_PCIE1_MEM_PHYS, 353 .size = CONFIG_SYS_PCIE1_MEM_SIZE, 354 .flags = PCI_REGION_MEM, 355 }, 356 { 357 .bus_start = CONFIG_SYS_PCIE1_IO_BASE, 358 .phys_start = CONFIG_SYS_PCIE1_IO_PHYS, 359 .size = CONFIG_SYS_PCIE1_IO_SIZE, 360 .flags = PCI_REGION_IO, 361 }, 362 }; 363 364 void pci_init_board(void) 365 { 366 immap_t *immr = (immap_t *)CONFIG_SYS_IMMR; 367 sysconf83xx_t *sysconf = &immr->sysconf; 368 law83xx_t *pcie_law = sysconf->pcielaw; 369 struct pci_region *pcie_reg[] = { pcie_regions_0 }; 370 371 fsl_setup_serdes(CONFIG_FSL_SERDES1, FSL_SERDES_PROTO_PEX, 372 FSL_SERDES_CLK_100, FSL_SERDES_VDD_1V); 373 374 /* Deassert the resets in the control register */ 375 out_be32(&sysconf->pecr1, 0xE0008000); 376 udelay(2000); 377 378 /* Configure PCI Express Local Access Windows */ 379 out_be32(&pcie_law[0].bar, CONFIG_SYS_PCIE1_BASE & LAWBAR_BAR); 380 out_be32(&pcie_law[0].ar, LBLAWAR_EN | LBLAWAR_512MB); 381 382 mpc83xx_pcie_init(1, pcie_reg); 383 } 384 385 ulong board_flash_get_legacy(ulong base, int banknum, flash_info_t *info) 386 { 387 info->portwidth = FLASH_CFI_16BIT; 388 info->chipwidth = FLASH_CFI_BY16; 389 info->interface = FLASH_CFI_X16; 390 return 1; 391 } 392 393 #if defined(CONFIG_OF_BOARD_SETUP) 394 int ft_board_setup(void *blob, bd_t *bd) 395 { 396 ft_cpu_setup(blob, bd); 397 fdt_fixup_dr_usb(blob, bd); 398 fdt_fixup_esdhc(blob, bd); 399 400 return 0; 401 } 402 #endif 403 404 /* 405 * FPGA MII bitbang implementation 406 */ 407 408 struct fpga_mii { 409 unsigned fpga; 410 int mdio; 411 } fpga_mii[] = { 412 { 0, 1}, 413 { 1, 1}, 414 { 2, 1}, 415 { 3, 1}, 416 }; 417 418 static int mii_dummy_init(struct bb_miiphy_bus *bus) 419 { 420 return 0; 421 } 422 423 static int mii_mdio_active(struct bb_miiphy_bus *bus) 424 { 425 struct fpga_mii *fpga_mii = bus->priv; 426 427 if (fpga_mii->mdio) 428 FPGA_SET_REG(fpga_mii->fpga, gpio.set, GPIO_MDIO); 429 else 430 FPGA_SET_REG(fpga_mii->fpga, gpio.clear, GPIO_MDIO); 431 432 return 0; 433 } 434 435 static int mii_mdio_tristate(struct bb_miiphy_bus *bus) 436 { 437 struct fpga_mii *fpga_mii = bus->priv; 438 439 FPGA_SET_REG(fpga_mii->fpga, gpio.set, GPIO_MDIO); 440 441 return 0; 442 } 443 444 static int mii_set_mdio(struct bb_miiphy_bus *bus, int v) 445 { 446 struct fpga_mii *fpga_mii = bus->priv; 447 448 if (v) 449 FPGA_SET_REG(fpga_mii->fpga, gpio.set, GPIO_MDIO); 450 else 451 FPGA_SET_REG(fpga_mii->fpga, gpio.clear, GPIO_MDIO); 452 453 fpga_mii->mdio = v; 454 455 return 0; 456 } 457 458 static int mii_get_mdio(struct bb_miiphy_bus *bus, int *v) 459 { 460 u16 gpio; 461 struct fpga_mii *fpga_mii = bus->priv; 462 463 FPGA_GET_REG(fpga_mii->fpga, gpio.read, &gpio); 464 465 *v = ((gpio & GPIO_MDIO) != 0); 466 467 return 0; 468 } 469 470 static int mii_set_mdc(struct bb_miiphy_bus *bus, int v) 471 { 472 struct fpga_mii *fpga_mii = bus->priv; 473 474 if (v) 475 FPGA_SET_REG(fpga_mii->fpga, gpio.set, GPIO_MDC); 476 else 477 FPGA_SET_REG(fpga_mii->fpga, gpio.clear, GPIO_MDC); 478 479 return 0; 480 } 481 482 static int mii_delay(struct bb_miiphy_bus *bus) 483 { 484 udelay(1); 485 486 return 0; 487 } 488 489 struct bb_miiphy_bus bb_miiphy_buses[] = { 490 { 491 .name = "board0", 492 .init = mii_dummy_init, 493 .mdio_active = mii_mdio_active, 494 .mdio_tristate = mii_mdio_tristate, 495 .set_mdio = mii_set_mdio, 496 .get_mdio = mii_get_mdio, 497 .set_mdc = mii_set_mdc, 498 .delay = mii_delay, 499 .priv = &fpga_mii[0], 500 }, 501 { 502 .name = "board1", 503 .init = mii_dummy_init, 504 .mdio_active = mii_mdio_active, 505 .mdio_tristate = mii_mdio_tristate, 506 .set_mdio = mii_set_mdio, 507 .get_mdio = mii_get_mdio, 508 .set_mdc = mii_set_mdc, 509 .delay = mii_delay, 510 .priv = &fpga_mii[1], 511 }, 512 { 513 .name = "board2", 514 .init = mii_dummy_init, 515 .mdio_active = mii_mdio_active, 516 .mdio_tristate = mii_mdio_tristate, 517 .set_mdio = mii_set_mdio, 518 .get_mdio = mii_get_mdio, 519 .set_mdc = mii_set_mdc, 520 .delay = mii_delay, 521 .priv = &fpga_mii[2], 522 }, 523 { 524 .name = "board3", 525 .init = mii_dummy_init, 526 .mdio_active = mii_mdio_active, 527 .mdio_tristate = mii_mdio_tristate, 528 .set_mdio = mii_set_mdio, 529 .get_mdio = mii_get_mdio, 530 .set_mdc = mii_set_mdc, 531 .delay = mii_delay, 532 .priv = &fpga_mii[3], 533 }, 534 }; 535 536 int bb_miiphy_buses_num = sizeof(bb_miiphy_buses) / 537 sizeof(bb_miiphy_buses[0]); 538