xref: /openbmc/u-boot/board/gdsys/mpc8308/strider.c (revision 0a61ee88) 
1 /*
2  * (C) Copyright 2014
3  * Dirk Eibach,  Guntermann & Drunck GmbH, eibach@gdsys.de
4  *
5  * SPDX-License-Identifier:	GPL-2.0+
6  */
7 
8 #include <common.h>
9 #include <hwconfig.h>
10 #include <i2c.h>
11 #include <spi.h>
12 #include <libfdt.h>
13 #include <fdt_support.h>
14 #include <pci.h>
15 #include <mpc83xx.h>
16 #include <fsl_esdhc.h>
17 #include <asm/io.h>
18 #include <asm/fsl_serdes.h>
19 #include <asm/fsl_mpc83xx_serdes.h>
20 
21 #include "mpc8308.h"
22 
23 #include <gdsys_fpga.h>
24 
25 #include "../common/adv7611.h"
26 #include "../common/ch7301.h"
27 #include "../common/ioep-fpga.h"
28 #include "../common/mclink.h"
29 #include "../common/osd.h"
30 #include "../common/phy.h"
31 #include "../common/fanctrl.h"
32 
33 #include <pca953x.h>
34 #include <pca9698.h>
35 
36 #include <miiphy.h>
37 
38 DECLARE_GLOBAL_DATA_PTR;
39 
40 #define MAX_MUX_CHANNELS 2
41 
42 enum {
43 	MCFPGA_DONE = 1 << 0,
44 	MCFPGA_INIT_N = 1 << 1,
45 	MCFPGA_PROGRAM_N = 1 << 2,
46 	MCFPGA_UPDATE_ENABLE_N = 1 << 3,
47 	MCFPGA_RESET_N = 1 << 4,
48 };
49 
50 enum {
51 	GPIO_MDC = 1 << 14,
52 	GPIO_MDIO = 1 << 15,
53 };
54 
55 unsigned int mclink_fpgacount;
56 struct ihs_fpga *fpga_ptr[] = CONFIG_SYS_FPGA_PTR;
57 
58 struct {
59 	u8 bus;
60 	u8 addr;
61 } strider_fans[] = CONFIG_STRIDER_FANS;
62 
63 int fpga_set_reg(u32 fpga, u16 *reg, off_t regoff, u16 data)
64 {
65 	int res;
66 
67 	switch (fpga) {
68 	case 0:
69 		out_le16(reg, data);
70 		break;
71 	default:
72 		res = mclink_send(fpga - 1, regoff, data);
73 		if (res < 0) {
74 			printf("mclink_send reg %02lx data %04x returned %d\n",
75 			       regoff, data, res);
76 			return res;
77 		}
78 		break;
79 	}
80 
81 	return 0;
82 }
83 
84 int fpga_get_reg(u32 fpga, u16 *reg, off_t regoff, u16 *data)
85 {
86 	int res;
87 
88 	switch (fpga) {
89 	case 0:
90 		*data = in_le16(reg);
91 		break;
92 	default:
93 		if (fpga > mclink_fpgacount)
94 			return -EINVAL;
95 		res = mclink_receive(fpga - 1, regoff, data);
96 		if (res < 0) {
97 			printf("mclink_receive reg %02lx returned %d\n",
98 			       regoff, res);
99 			return res;
100 		}
101 	}
102 
103 	return 0;
104 }
105 
106 int checkboard(void)
107 {
108 	char *s = getenv("serial#");
109 	bool hw_type_cat = pca9698_get_value(0x20, 18);
110 
111 	puts("Board: ");
112 
113 	printf("Strider %s", hw_type_cat ? "CAT" : "Fiber");
114 
115 	if (s != NULL) {
116 		puts(", serial# ");
117 		puts(s);
118 	}
119 
120 	puts("\n");
121 
122 	return 0;
123 }
124 
125 int last_stage_init(void)
126 {
127 	int slaves;
128 	unsigned int k;
129 	unsigned int mux_ch;
130 	unsigned char mclink_controllers[] = { 0x3c, 0x3d, 0x3e };
131 	bool hw_type_cat = pca9698_get_value(0x20, 18);
132 	bool ch0_sgmii2_present = false;
133 
134 	/* Turn on Analog Devices ADV7611 */
135 	pca9698_direction_output(0x20, 8, 0);
136 
137 	/* Turn on Parade DP501 */
138 	pca9698_direction_output(0x20, 9, 1);
139 
140 	ch0_sgmii2_present = !pca9698_get_value(0x20, 37);
141 
142 	/* wait for FPGA done, then reset FPGA */
143 	for (k = 0; k < ARRAY_SIZE(mclink_controllers); ++k) {
144 		unsigned int ctr = 0;
145 
146 		if (i2c_probe(mclink_controllers[k]))
147 			continue;
148 
149 		while (!(pca953x_get_val(mclink_controllers[k])
150 		       & MCFPGA_DONE)) {
151 			udelay(100000);
152 			if (ctr++ > 5) {
153 				printf("no done for mclink_controller %d\n", k);
154 				break;
155 			}
156 		}
157 
158 		pca953x_set_dir(mclink_controllers[k], MCFPGA_RESET_N, 0);
159 		pca953x_set_val(mclink_controllers[k], MCFPGA_RESET_N, 0);
160 		udelay(10);
161 		pca953x_set_val(mclink_controllers[k], MCFPGA_RESET_N,
162 				MCFPGA_RESET_N);
163 	}
164 
165 	if (hw_type_cat) {
166 		miiphy_register(bb_miiphy_buses[0].name, bb_miiphy_read,
167 				bb_miiphy_write);
168 		for (mux_ch = 0; mux_ch < MAX_MUX_CHANNELS; ++mux_ch) {
169 			if ((mux_ch == 1) && !ch0_sgmii2_present)
170 				continue;
171 
172 			setup_88e1514(bb_miiphy_buses[0].name, mux_ch);
173 		}
174 	}
175 
176 	/* give slave-PLLs and Parade DP501 some time to be up and running */
177 	udelay(500000);
178 
179 	mclink_fpgacount = CONFIG_SYS_MCLINK_MAX;
180 	slaves = mclink_probe();
181 	mclink_fpgacount = 0;
182 
183 	ioep_fpga_print_info(0);
184 
185 	if (!adv7611_probe(0))
186 		printf("       Advantiv ADV7611 HDMI Receiver\n");
187 
188 #ifdef CONFIG_STRIDER_CON
189 	if (ioep_fpga_has_osd(0))
190 		osd_probe(0);
191 #endif
192 
193 #ifdef CONFIG_STRIDER_CPU
194 	ch7301_probe(0, false);
195 #endif
196 
197 	if (slaves <= 0)
198 		return 0;
199 
200 	mclink_fpgacount = slaves;
201 
202 	for (k = 1; k <= slaves; ++k) {
203 		ioep_fpga_print_info(k);
204 #ifdef CONFIG_STRIDER_CON
205 		if (ioep_fpga_has_osd(k))
206 			osd_probe(k);
207 #endif
208 #ifdef CONFIG_STRIDER_CPU
209 		FPGA_SET_REG(k, extended_control, 0); /* enable video in*/
210 		if (!adv7611_probe(k))
211 			printf("       Advantiv ADV7611 HDMI Receiver\n");
212 		ch7301_probe(k, false);
213 #endif
214 		if (hw_type_cat) {
215 			miiphy_register(bb_miiphy_buses[k].name,
216 					bb_miiphy_read, bb_miiphy_write);
217 			setup_88e1514(bb_miiphy_buses[k].name, 0);
218 		}
219 	}
220 
221 	for (k = 0; k < ARRAY_SIZE(strider_fans); ++k) {
222 		i2c_set_bus_num(strider_fans[k].bus);
223 		init_fan_controller(strider_fans[k].addr);
224 	}
225 
226 	return 0;
227 }
228 
229 /*
230  * provide access to fpga gpios (for I2C bitbang)
231  * (these may look all too simple but make iocon.h much more readable)
232  */
233 void fpga_gpio_set(unsigned int bus, int pin)
234 {
235 	FPGA_SET_REG(bus, gpio.set, pin);
236 }
237 
238 void fpga_gpio_clear(unsigned int bus, int pin)
239 {
240 	FPGA_SET_REG(bus, gpio.clear, pin);
241 }
242 
243 int fpga_gpio_get(unsigned int bus, int pin)
244 {
245 	u16 val;
246 
247 	FPGA_GET_REG(bus, gpio.read, &val);
248 
249 	return val & pin;
250 }
251 
252 void mpc8308_init(void)
253 {
254 	pca9698_direction_output(0x20, 26, 1);
255 }
256 
257 void mpc8308_set_fpga_reset(unsigned state)
258 {
259 	pca9698_set_value(0x20, 26, state ? 0 : 1);
260 }
261 
262 void mpc8308_setup_hw(void)
263 {
264 	immap_t *immr = (immap_t *)CONFIG_SYS_IMMR;
265 
266 	/*
267 	 * set "startup-finished"-gpios
268 	 */
269 	setbits_be32(&immr->gpio[0].dir, (1 << (31-11)) | (1 << (31-12)));
270 	setbits_be32(&immr->gpio[0].dat, 1 << (31-12));
271 }
272 
273 int mpc8308_get_fpga_done(unsigned fpga)
274 {
275 	return pca9698_get_value(0x20, 20);
276 }
277 
278 #ifdef CONFIG_FSL_ESDHC
279 int board_mmc_init(bd_t *bd)
280 {
281 	immap_t *immr = (immap_t *)CONFIG_SYS_IMMR;
282 	sysconf83xx_t *sysconf = &immr->sysconf;
283 
284 	/* Enable cache snooping in eSDHC system configuration register */
285 	out_be32(&sysconf->sdhccr, 0x02000000);
286 
287 	return fsl_esdhc_mmc_init(bd);
288 }
289 #endif
290 
291 static struct pci_region pcie_regions_0[] = {
292 	{
293 		.bus_start = CONFIG_SYS_PCIE1_MEM_BASE,
294 		.phys_start = CONFIG_SYS_PCIE1_MEM_PHYS,
295 		.size = CONFIG_SYS_PCIE1_MEM_SIZE,
296 		.flags = PCI_REGION_MEM,
297 	},
298 	{
299 		.bus_start = CONFIG_SYS_PCIE1_IO_BASE,
300 		.phys_start = CONFIG_SYS_PCIE1_IO_PHYS,
301 		.size = CONFIG_SYS_PCIE1_IO_SIZE,
302 		.flags = PCI_REGION_IO,
303 	},
304 };
305 
306 void pci_init_board(void)
307 {
308 	immap_t *immr = (immap_t *)CONFIG_SYS_IMMR;
309 	sysconf83xx_t *sysconf = &immr->sysconf;
310 	law83xx_t *pcie_law = sysconf->pcielaw;
311 	struct pci_region *pcie_reg[] = { pcie_regions_0 };
312 
313 	fsl_setup_serdes(CONFIG_FSL_SERDES1, FSL_SERDES_PROTO_PEX,
314 			 FSL_SERDES_CLK_100, FSL_SERDES_VDD_1V);
315 
316 	/* Deassert the resets in the control register */
317 	out_be32(&sysconf->pecr1, 0xE0008000);
318 	udelay(2000);
319 
320 	/* Configure PCI Express Local Access Windows */
321 	out_be32(&pcie_law[0].bar, CONFIG_SYS_PCIE1_BASE & LAWBAR_BAR);
322 	out_be32(&pcie_law[0].ar, LBLAWAR_EN | LBLAWAR_512MB);
323 
324 	mpc83xx_pcie_init(1, pcie_reg);
325 }
326 
327 ulong board_flash_get_legacy(ulong base, int banknum, flash_info_t *info)
328 {
329 	info->portwidth = FLASH_CFI_16BIT;
330 	info->chipwidth = FLASH_CFI_BY16;
331 	info->interface = FLASH_CFI_X16;
332 	return 1;
333 }
334 
335 #if defined(CONFIG_OF_BOARD_SETUP)
336 int ft_board_setup(void *blob, bd_t *bd)
337 {
338 	ft_cpu_setup(blob, bd);
339 	fdt_fixup_dr_usb(blob, bd);
340 	fdt_fixup_esdhc(blob, bd);
341 
342 	return 0;
343 }
344 #endif
345 
346 /*
347  * FPGA MII bitbang implementation
348  */
349 
350 struct fpga_mii {
351 	unsigned fpga;
352 	int mdio;
353 } fpga_mii[] = {
354 	{ 0, 1},
355 	{ 1, 1},
356 	{ 2, 1},
357 	{ 3, 1},
358 };
359 
360 static int mii_dummy_init(struct bb_miiphy_bus *bus)
361 {
362 	return 0;
363 }
364 
365 static int mii_mdio_active(struct bb_miiphy_bus *bus)
366 {
367 	struct fpga_mii *fpga_mii = bus->priv;
368 
369 	if (fpga_mii->mdio)
370 		FPGA_SET_REG(fpga_mii->fpga, gpio.set, GPIO_MDIO);
371 	else
372 		FPGA_SET_REG(fpga_mii->fpga, gpio.clear, GPIO_MDIO);
373 
374 	return 0;
375 }
376 
377 static int mii_mdio_tristate(struct bb_miiphy_bus *bus)
378 {
379 	struct fpga_mii *fpga_mii = bus->priv;
380 
381 	FPGA_SET_REG(fpga_mii->fpga, gpio.set, GPIO_MDIO);
382 
383 	return 0;
384 }
385 
386 static int mii_set_mdio(struct bb_miiphy_bus *bus, int v)
387 {
388 	struct fpga_mii *fpga_mii = bus->priv;
389 
390 	if (v)
391 		FPGA_SET_REG(fpga_mii->fpga, gpio.set, GPIO_MDIO);
392 	else
393 		FPGA_SET_REG(fpga_mii->fpga, gpio.clear, GPIO_MDIO);
394 
395 	fpga_mii->mdio = v;
396 
397 	return 0;
398 }
399 
400 static int mii_get_mdio(struct bb_miiphy_bus *bus, int *v)
401 {
402 	u16 gpio;
403 	struct fpga_mii *fpga_mii = bus->priv;
404 
405 	FPGA_GET_REG(fpga_mii->fpga, gpio.read, &gpio);
406 
407 	*v = ((gpio & GPIO_MDIO) != 0);
408 
409 	return 0;
410 }
411 
412 static int mii_set_mdc(struct bb_miiphy_bus *bus, int v)
413 {
414 	struct fpga_mii *fpga_mii = bus->priv;
415 
416 	if (v)
417 		FPGA_SET_REG(fpga_mii->fpga, gpio.set, GPIO_MDC);
418 	else
419 		FPGA_SET_REG(fpga_mii->fpga, gpio.clear, GPIO_MDC);
420 
421 	return 0;
422 }
423 
424 static int mii_delay(struct bb_miiphy_bus *bus)
425 {
426 	udelay(1);
427 
428 	return 0;
429 }
430 
431 struct bb_miiphy_bus bb_miiphy_buses[] = {
432 	{
433 		.name = "board0",
434 		.init = mii_dummy_init,
435 		.mdio_active = mii_mdio_active,
436 		.mdio_tristate = mii_mdio_tristate,
437 		.set_mdio = mii_set_mdio,
438 		.get_mdio = mii_get_mdio,
439 		.set_mdc = mii_set_mdc,
440 		.delay = mii_delay,
441 		.priv = &fpga_mii[0],
442 	},
443 	{
444 		.name = "board1",
445 		.init = mii_dummy_init,
446 		.mdio_active = mii_mdio_active,
447 		.mdio_tristate = mii_mdio_tristate,
448 		.set_mdio = mii_set_mdio,
449 		.get_mdio = mii_get_mdio,
450 		.set_mdc = mii_set_mdc,
451 		.delay = mii_delay,
452 		.priv = &fpga_mii[1],
453 	},
454 	{
455 		.name = "board2",
456 		.init = mii_dummy_init,
457 		.mdio_active = mii_mdio_active,
458 		.mdio_tristate = mii_mdio_tristate,
459 		.set_mdio = mii_set_mdio,
460 		.get_mdio = mii_get_mdio,
461 		.set_mdc = mii_set_mdc,
462 		.delay = mii_delay,
463 		.priv = &fpga_mii[2],
464 	},
465 	{
466 		.name = "board3",
467 		.init = mii_dummy_init,
468 		.mdio_active = mii_mdio_active,
469 		.mdio_tristate = mii_mdio_tristate,
470 		.set_mdio = mii_set_mdio,
471 		.get_mdio = mii_get_mdio,
472 		.set_mdc = mii_set_mdc,
473 		.delay = mii_delay,
474 		.priv = &fpga_mii[3],
475 	},
476 };
477 
478 int bb_miiphy_buses_num = sizeof(bb_miiphy_buses) /
479 			  sizeof(bb_miiphy_buses[0]);
480