1 /* 2 * Copyright (C) 2007 Freescale Semiconductor, Inc. 3 * Copyright (C) 2010 Ilya Yanok, Emcraft Systems, yanok@emcraft.com 4 * 5 * Authors: Nick.Spence@freescale.com 6 * Wilson.Lo@freescale.com 7 * scottwood@freescale.com 8 * 9 * This files is mostly identical to the original from 10 * board\freescale\mpc8315erdb\sdram.c 11 * 12 * SPDX-License-Identifier: GPL-2.0+ 13 */ 14 15 #include <common.h> 16 #include <mpc83xx.h> 17 #include <spd_sdram.h> 18 19 #include <asm/bitops.h> 20 #include <asm/io.h> 21 22 #include <asm/processor.h> 23 24 DECLARE_GLOBAL_DATA_PTR; 25 26 /* Fixed sdram init -- doesn't use serial presence detect. 27 * 28 * This is useful for faster booting in configs where the RAM is unlikely 29 * to be changed, or for things like NAND booting where space is tight. 30 */ 31 static long fixed_sdram(void) 32 { 33 immap_t *im = (immap_t *)CONFIG_SYS_IMMR; 34 u32 msize = CONFIG_SYS_DDR_SIZE * 1024 * 1024; 35 u32 msize_log2 = __ilog2(msize); 36 37 out_be32(&im->sysconf.ddrlaw[0].bar, 38 CONFIG_SYS_DDR_SDRAM_BASE & 0xfffff000); 39 out_be32(&im->sysconf.ddrlaw[0].ar, LBLAWAR_EN | (msize_log2 - 1)); 40 out_be32(&im->sysconf.ddrcdr, CONFIG_SYS_DDRCDR_VALUE); 41 42 out_be32(&im->ddr.csbnds[0].csbnds, (msize - 1) >> 24); 43 out_be32(&im->ddr.cs_config[0], CONFIG_SYS_DDR_CS0_CONFIG); 44 45 /* Currently we use only one CS, so disable the other bank. */ 46 out_be32(&im->ddr.cs_config[1], 0); 47 48 out_be32(&im->ddr.sdram_clk_cntl, CONFIG_SYS_DDR_SDRAM_CLK_CNTL); 49 out_be32(&im->ddr.timing_cfg_3, CONFIG_SYS_DDR_TIMING_3); 50 out_be32(&im->ddr.timing_cfg_1, CONFIG_SYS_DDR_TIMING_1); 51 out_be32(&im->ddr.timing_cfg_2, CONFIG_SYS_DDR_TIMING_2); 52 out_be32(&im->ddr.timing_cfg_0, CONFIG_SYS_DDR_TIMING_0); 53 54 out_be32(&im->ddr.sdram_cfg, CONFIG_SYS_DDR_SDRAM_CFG); 55 out_be32(&im->ddr.sdram_cfg2, CONFIG_SYS_DDR_SDRAM_CFG2); 56 out_be32(&im->ddr.sdram_mode, CONFIG_SYS_DDR_MODE); 57 out_be32(&im->ddr.sdram_mode2, CONFIG_SYS_DDR_MODE2); 58 59 out_be32(&im->ddr.sdram_interval, CONFIG_SYS_DDR_INTERVAL); 60 sync(); 61 62 /* enable DDR controller */ 63 setbits_be32(&im->ddr.sdram_cfg, SDRAM_CFG_MEM_EN); 64 sync(); 65 66 return get_ram_size(CONFIG_SYS_DDR_SDRAM_BASE, msize); 67 } 68 69 phys_size_t initdram(int board_type) 70 { 71 immap_t *im = (immap_t *)CONFIG_SYS_IMMR; 72 u32 msize; 73 74 if ((in_be32(&im->sysconf.immrbar) & IMMRBAR_BASE_ADDR) != (u32)im) 75 return -1; 76 77 /* DDR SDRAM */ 78 msize = fixed_sdram(); 79 80 /* return total bus SDRAM size(bytes) -- DDR */ 81 return msize; 82 } 83