1 /* 2 * (C) Copyright 2014 3 * Dirk Eibach, Guntermann & Drunck GmbH, eibach@gdsys.de 4 * 5 * SPDX-License-Identifier: GPL-2.0+ 6 */ 7 8 #include <common.h> 9 #include <command.h> 10 #include <asm/processor.h> 11 #include <asm/io.h> 12 #include <asm/ppc4xx-gpio.h> 13 #include <asm/global_data.h> 14 15 #include "mpc8308.h" 16 #include <gdsys_fpga.h> 17 18 #define REFLECTION_TESTPATTERN 0xdede 19 #define REFLECTION_TESTPATTERN_INV (~REFLECTION_TESTPATTERN & 0xffff) 20 21 #ifdef CONFIG_SYS_FPGA_NO_RFL_HI 22 #define REFLECTION_TESTREG reflection_low 23 #else 24 #define REFLECTION_TESTREG reflection_high 25 #endif 26 27 DECLARE_GLOBAL_DATA_PTR; 28 29 int get_fpga_state(unsigned dev) 30 { 31 return gd->arch.fpga_state[dev]; 32 } 33 34 void print_fpga_state(unsigned dev) 35 { 36 if (gd->arch.fpga_state[dev] & FPGA_STATE_DONE_FAILED) 37 puts(" Waiting for FPGA-DONE timed out.\n"); 38 if (gd->arch.fpga_state[dev] & FPGA_STATE_REFLECTION_FAILED) 39 puts(" FPGA reflection test failed.\n"); 40 } 41 42 int board_early_init_f(void) 43 { 44 unsigned k; 45 46 for (k = 0; k < CONFIG_SYS_FPGA_COUNT; ++k) 47 gd->arch.fpga_state[k] = 0; 48 49 return 0; 50 } 51 52 int board_early_init_r(void) 53 { 54 unsigned k; 55 unsigned ctr; 56 57 for (k = 0; k < CONFIG_SYS_FPGA_COUNT; ++k) 58 gd->arch.fpga_state[k] = 0; 59 60 /* 61 * reset FPGA 62 */ 63 mpc8308_init(); 64 65 mpc8308_set_fpga_reset(1); 66 67 mpc8308_setup_hw(); 68 69 for (k = 0; k < CONFIG_SYS_FPGA_COUNT; ++k) { 70 ctr = 0; 71 while (!mpc8308_get_fpga_done(k)) { 72 udelay(100000); 73 if (ctr++ > 5) { 74 gd->arch.fpga_state[k] |= 75 FPGA_STATE_DONE_FAILED; 76 break; 77 } 78 } 79 } 80 81 udelay(10); 82 83 mpc8308_set_fpga_reset(0); 84 85 for (k = 0; k < CONFIG_SYS_FPGA_COUNT; ++k) { 86 /* 87 * wait for fpga out of reset 88 */ 89 ctr = 0; 90 while (1) { 91 u16 val; 92 93 FPGA_SET_REG(k, reflection_low, REFLECTION_TESTPATTERN); 94 95 FPGA_GET_REG(k, REFLECTION_TESTREG, &val); 96 if (val == REFLECTION_TESTPATTERN_INV) 97 break; 98 99 udelay(100000); 100 if (ctr++ > 5) { 101 gd->arch.fpga_state[k] |= 102 FPGA_STATE_REFLECTION_FAILED; 103 break; 104 } 105 } 106 } 107 108 return 0; 109 } 110