1 /* 2 * (C) Copyright 2014 3 * Dirk Eibach, Guntermann & Drunck GmbH, eibach@gdsys.de 4 * 5 * SPDX-License-Identifier: GPL-2.0+ 6 */ 7 8 #include <common.h> 9 #include <command.h> 10 #include <asm/processor.h> 11 #include <asm/io.h> 12 #include <asm/ppc4xx-gpio.h> 13 #include <asm/global_data.h> 14 15 #include "mpc8308.h" 16 #include <gdsys_fpga.h> 17 18 #define REFLECTION_TESTPATTERN 0xdede 19 #define REFLECTION_TESTPATTERN_INV (~REFLECTION_TESTPATTERN & 0xffff) 20 21 #ifdef CONFIG_SYS_FPGA_NO_RFL_HI 22 #define REFLECTION_TESTREG reflection_low 23 #else 24 #define REFLECTION_TESTREG reflection_high 25 #endif 26 27 DECLARE_GLOBAL_DATA_PTR; 28 29 int get_fpga_state(unsigned dev) 30 { 31 return gd->arch.fpga_state[dev]; 32 } 33 34 int board_early_init_f(void) 35 { 36 unsigned k; 37 38 for (k = 0; k < CONFIG_SYS_FPGA_COUNT; ++k) 39 gd->arch.fpga_state[k] = 0; 40 41 return 0; 42 } 43 44 int board_early_init_r(void) 45 { 46 unsigned k; 47 unsigned ctr; 48 49 for (k = 0; k < CONFIG_SYS_FPGA_COUNT; ++k) 50 gd->arch.fpga_state[k] = 0; 51 52 /* 53 * reset FPGA 54 */ 55 mpc8308_init(); 56 57 mpc8308_set_fpga_reset(1); 58 59 mpc8308_setup_hw(); 60 61 for (k = 0; k < CONFIG_SYS_FPGA_COUNT; ++k) { 62 ctr = 0; 63 while (!mpc8308_get_fpga_done(k)) { 64 udelay(100000); 65 if (ctr++ > 5) { 66 gd->arch.fpga_state[k] |= 67 FPGA_STATE_DONE_FAILED; 68 break; 69 } 70 } 71 } 72 73 udelay(10); 74 75 mpc8308_set_fpga_reset(0); 76 77 for (k = 0; k < CONFIG_SYS_FPGA_COUNT; ++k) { 78 /* 79 * wait for fpga out of reset 80 */ 81 ctr = 0; 82 while (1) { 83 u16 val; 84 85 FPGA_SET_REG(k, reflection_low, REFLECTION_TESTPATTERN); 86 87 FPGA_GET_REG(k, REFLECTION_TESTREG, &val); 88 if (val == REFLECTION_TESTPATTERN_INV) 89 break; 90 91 udelay(100000); 92 if (ctr++ > 5) { 93 gd->arch.fpga_state[k] |= 94 FPGA_STATE_REFLECTION_FAILED; 95 break; 96 } 97 } 98 } 99 100 return 0; 101 } 102