1 /* 2 * (C) Copyright 2014 3 * Dirk Eibach, Guntermann & Drunck GmbH, eibach@gdsys.de 4 * 5 * SPDX-License-Identifier: GPL-2.0+ 6 */ 7 8 #include <common.h> 9 #include <hwconfig.h> 10 #include <i2c.h> 11 #include <spi.h> 12 #include <libfdt.h> 13 #include <fdt_support.h> 14 #include <pci.h> 15 #include <mpc83xx.h> 16 #include <fsl_esdhc.h> 17 #include <asm/io.h> 18 #include <asm/fsl_serdes.h> 19 #include <asm/fsl_mpc83xx_serdes.h> 20 21 #include "mpc8308.h" 22 23 #include <gdsys_fpga.h> 24 25 #include "../common/osd.h" 26 #include "../common/mclink.h" 27 #include "../common/phy.h" 28 29 #include <pca953x.h> 30 #include <pca9698.h> 31 32 #include <miiphy.h> 33 34 DECLARE_GLOBAL_DATA_PTR; 35 36 #define MAX_MUX_CHANNELS 2 37 38 enum { 39 UNITTYPE_MAIN_SERVER = 0, 40 UNITTYPE_MAIN_USER = 1, 41 UNITTYPE_VIDEO_SERVER = 2, 42 UNITTYPE_VIDEO_USER = 3, 43 }; 44 45 enum { 46 UNITTYPEPCB_DVI = 0, 47 UNITTYPEPCB_DP_165 = 1, 48 UNITTYPEPCB_DP_300 = 2, 49 UNITTYPEPCB_HDMI = 3, 50 }; 51 52 enum { 53 HWVER_100 = 0, 54 HWVER_110 = 1, 55 }; 56 57 enum { 58 FPGA_HWVER_200 = 0, 59 FPGA_HWVER_210 = 1, 60 }; 61 62 enum { 63 COMPRESSION_NONE = 0, 64 COMPRESSION_TYPE1_DELTA = 1, 65 COMPRESSION_TYPE1_TYPE2_DELTA = 3, 66 }; 67 68 enum { 69 AUDIO_NONE = 0, 70 AUDIO_TX = 1, 71 AUDIO_RX = 2, 72 AUDIO_RXTX = 3, 73 }; 74 75 enum { 76 SYSCLK_147456 = 0, 77 }; 78 79 enum { 80 RAM_DDR2_32 = 0, 81 RAM_DDR3_32 = 1, 82 }; 83 84 enum { 85 CARRIER_SPEED_1G = 0, 86 CARRIER_SPEED_2_5G = 1, 87 }; 88 89 enum { 90 MCFPGA_DONE = 1 << 0, 91 MCFPGA_INIT_N = 1 << 1, 92 MCFPGA_PROGRAM_N = 1 << 2, 93 MCFPGA_UPDATE_ENABLE_N = 1 << 3, 94 MCFPGA_RESET_N = 1 << 4, 95 }; 96 97 enum { 98 GPIO_MDC = 1 << 14, 99 GPIO_MDIO = 1 << 15, 100 }; 101 102 unsigned int mclink_fpgacount; 103 struct ihs_fpga *fpga_ptr[] = CONFIG_SYS_FPGA_PTR; 104 105 int fpga_set_reg(u32 fpga, u16 *reg, off_t regoff, u16 data) 106 { 107 int res; 108 109 switch (fpga) { 110 case 0: 111 out_le16(reg, data); 112 break; 113 default: 114 res = mclink_send(fpga - 1, regoff, data); 115 if (res < 0) { 116 printf("mclink_send reg %02lx data %04x returned %d\n", 117 regoff, data, res); 118 return res; 119 } 120 break; 121 } 122 123 return 0; 124 } 125 126 int fpga_get_reg(u32 fpga, u16 *reg, off_t regoff, u16 *data) 127 { 128 int res; 129 130 switch (fpga) { 131 case 0: 132 *data = in_le16(reg); 133 break; 134 default: 135 if (fpga > mclink_fpgacount) 136 return -EINVAL; 137 res = mclink_receive(fpga - 1, regoff, data); 138 if (res < 0) { 139 printf("mclink_receive reg %02lx returned %d\n", 140 regoff, res); 141 return res; 142 } 143 } 144 145 return 0; 146 } 147 148 int checkboard(void) 149 { 150 char *s = getenv("serial#"); 151 bool hw_type_cat = pca9698_get_value(0x20, 20); 152 153 puts("Board: "); 154 155 printf("HRCon %s", hw_type_cat ? "CAT" : "Fiber"); 156 157 if (s != NULL) { 158 puts(", serial# "); 159 puts(s); 160 } 161 162 puts("\n"); 163 164 return 0; 165 } 166 167 static void print_fpga_info(unsigned int fpga, bool rgmii2_present) 168 { 169 u16 versions; 170 u16 fpga_version; 171 u16 fpga_features; 172 unsigned unit_type; 173 unsigned unit_type_pcb_video; 174 unsigned hardware_version; 175 unsigned feature_compression; 176 unsigned feature_osd; 177 unsigned feature_audio; 178 unsigned feature_sysclock; 179 unsigned feature_ramconfig; 180 unsigned feature_carrier_speed; 181 unsigned feature_carriers; 182 unsigned feature_video_channels; 183 184 FPGA_GET_REG(fpga, versions, &versions); 185 FPGA_GET_REG(fpga, fpga_version, &fpga_version); 186 FPGA_GET_REG(fpga, fpga_features, &fpga_features); 187 188 unit_type = (versions & 0xf000) >> 12; 189 unit_type_pcb_video = (versions & 0x01c0) >> 6; 190 feature_compression = (fpga_features & 0xe000) >> 13; 191 feature_osd = fpga_features & (1<<11); 192 feature_audio = (fpga_features & 0x0600) >> 9; 193 feature_sysclock = (fpga_features & 0x0180) >> 7; 194 feature_ramconfig = (fpga_features & 0x0060) >> 5; 195 feature_carrier_speed = fpga_features & (1<<4); 196 feature_carriers = (fpga_features & 0x000c) >> 2; 197 feature_video_channels = fpga_features & 0x0003; 198 199 switch (unit_type) { 200 case UNITTYPE_MAIN_USER: 201 printf("Mainchannel"); 202 break; 203 204 case UNITTYPE_VIDEO_USER: 205 printf("Videochannel"); 206 break; 207 208 default: 209 printf("UnitType %d(not supported)", unit_type); 210 break; 211 } 212 213 if (unit_type == UNITTYPE_MAIN_USER) { 214 hardware_version = 215 (!!pca9698_get_value(0x20, 24) << 0) 216 | (!!pca9698_get_value(0x20, 25) << 1) 217 | (!!pca9698_get_value(0x20, 26) << 2) 218 | (!!pca9698_get_value(0x20, 27) << 3) 219 | (!!pca9698_get_value(0x20, 28) << 4); 220 switch (hardware_version) { 221 case HWVER_100: 222 printf(" HW-Ver 1.00,"); 223 break; 224 225 case HWVER_110: 226 printf(" HW-Ver 1.10,"); 227 break; 228 229 default: 230 printf(" HW-Ver %d(not supported),", 231 hardware_version); 232 break; 233 } 234 if (rgmii2_present) 235 printf(" RGMII2,"); 236 } 237 238 if (unit_type == UNITTYPE_VIDEO_USER) { 239 hardware_version = versions & 0x000f; 240 switch (hardware_version) { 241 case FPGA_HWVER_200: 242 printf(" HW-Ver 2.00,"); 243 break; 244 245 case FPGA_HWVER_210: 246 printf(" HW-Ver 2.10,"); 247 break; 248 249 default: 250 printf(" HW-Ver %d(not supported),", 251 hardware_version); 252 break; 253 } 254 } 255 256 switch (unit_type_pcb_video) { 257 case UNITTYPEPCB_DVI: 258 printf(" DVI,"); 259 break; 260 261 case UNITTYPEPCB_DP_165: 262 printf(" DP 165MPix/s,"); 263 break; 264 265 case UNITTYPEPCB_DP_300: 266 printf(" DP 300MPix/s,"); 267 break; 268 269 case UNITTYPEPCB_HDMI: 270 printf(" HDMI,"); 271 break; 272 } 273 274 printf(" FPGA V %d.%02d\n features:", 275 fpga_version / 100, fpga_version % 100); 276 277 278 switch (feature_compression) { 279 case COMPRESSION_NONE: 280 printf(" no compression"); 281 break; 282 283 case COMPRESSION_TYPE1_DELTA: 284 printf(" type1-deltacompression"); 285 break; 286 287 case COMPRESSION_TYPE1_TYPE2_DELTA: 288 printf(" type1-deltacompression, type2-inlinecompression"); 289 break; 290 291 default: 292 printf(" compression %d(not supported)", feature_compression); 293 break; 294 } 295 296 printf(", %sosd", feature_osd ? "" : "no "); 297 298 switch (feature_audio) { 299 case AUDIO_NONE: 300 printf(", no audio"); 301 break; 302 303 case AUDIO_TX: 304 printf(", audio tx"); 305 break; 306 307 case AUDIO_RX: 308 printf(", audio rx"); 309 break; 310 311 case AUDIO_RXTX: 312 printf(", audio rx+tx"); 313 break; 314 315 default: 316 printf(", audio %d(not supported)", feature_audio); 317 break; 318 } 319 320 puts(",\n "); 321 322 switch (feature_sysclock) { 323 case SYSCLK_147456: 324 printf("clock 147.456 MHz"); 325 break; 326 327 default: 328 printf("clock %d(not supported)", feature_sysclock); 329 break; 330 } 331 332 switch (feature_ramconfig) { 333 case RAM_DDR2_32: 334 printf(", RAM 32 bit DDR2"); 335 break; 336 337 case RAM_DDR3_32: 338 printf(", RAM 32 bit DDR3"); 339 break; 340 341 default: 342 printf(", RAM %d(not supported)", feature_ramconfig); 343 break; 344 } 345 346 printf(", %d carrier(s) %s", feature_carriers, 347 feature_carrier_speed ? "2.5Gbit/s" : "1Gbit/s"); 348 349 printf(", %d video channel(s)\n", feature_video_channels); 350 } 351 352 int last_stage_init(void) 353 { 354 int slaves; 355 unsigned int k; 356 unsigned int mux_ch; 357 unsigned char mclink_controllers[] = { 0x24, 0x25, 0x26 }; 358 u16 fpga_features; 359 bool hw_type_cat = pca9698_get_value(0x20, 20); 360 bool ch0_rgmii2_present = false; 361 362 FPGA_GET_REG(0, fpga_features, &fpga_features); 363 364 /* Turn on Parade DP501 */ 365 pca9698_direction_output(0x20, 10, 1); 366 367 ch0_rgmii2_present = !pca9698_get_value(0x20, 30); 368 369 /* wait for FPGA done */ 370 for (k = 0; k < ARRAY_SIZE(mclink_controllers); ++k) { 371 unsigned int ctr = 0; 372 373 if (i2c_probe(mclink_controllers[k])) 374 continue; 375 376 while (!(pca953x_get_val(mclink_controllers[k]) 377 & MCFPGA_DONE)) { 378 udelay(100000); 379 if (ctr++ > 5) { 380 printf("no done for mclink_controller %d\n", k); 381 break; 382 } 383 } 384 } 385 386 if (hw_type_cat) { 387 miiphy_register(bb_miiphy_buses[0].name, bb_miiphy_read, 388 bb_miiphy_write); 389 for (mux_ch = 0; mux_ch < MAX_MUX_CHANNELS; ++mux_ch) { 390 if ((mux_ch == 1) && !ch0_rgmii2_present) 391 continue; 392 393 setup_88e1514(bb_miiphy_buses[0].name, mux_ch); 394 } 395 } 396 397 /* give slave-PLLs and Parade DP501 some time to be up and running */ 398 udelay(500000); 399 400 mclink_fpgacount = CONFIG_SYS_MCLINK_MAX; 401 slaves = mclink_probe(); 402 mclink_fpgacount = 0; 403 404 print_fpga_info(0, ch0_rgmii2_present); 405 osd_probe(0); 406 407 if (slaves <= 0) 408 return 0; 409 410 mclink_fpgacount = slaves; 411 412 for (k = 1; k <= slaves; ++k) { 413 FPGA_GET_REG(k, fpga_features, &fpga_features); 414 415 print_fpga_info(k, false); 416 osd_probe(k); 417 if (hw_type_cat) { 418 miiphy_register(bb_miiphy_buses[k].name, 419 bb_miiphy_read, bb_miiphy_write); 420 setup_88e1514(bb_miiphy_buses[k].name, 0); 421 } 422 } 423 424 return 0; 425 } 426 427 /* 428 * provide access to fpga gpios (for I2C bitbang) 429 * (these may look all too simple but make iocon.h much more readable) 430 */ 431 void fpga_gpio_set(unsigned int bus, int pin) 432 { 433 FPGA_SET_REG(bus, gpio.set, pin); 434 } 435 436 void fpga_gpio_clear(unsigned int bus, int pin) 437 { 438 FPGA_SET_REG(bus, gpio.clear, pin); 439 } 440 441 int fpga_gpio_get(unsigned int bus, int pin) 442 { 443 u16 val; 444 445 FPGA_GET_REG(bus, gpio.read, &val); 446 447 return val & pin; 448 } 449 450 void mpc8308_init(void) 451 { 452 pca9698_direction_output(0x20, 4, 1); 453 } 454 455 void mpc8308_set_fpga_reset(unsigned state) 456 { 457 pca9698_set_value(0x20, 4, state ? 0 : 1); 458 } 459 460 void mpc8308_setup_hw(void) 461 { 462 immap_t *immr = (immap_t *)CONFIG_SYS_IMMR; 463 464 /* 465 * set "startup-finished"-gpios 466 */ 467 setbits_be32(&immr->gpio[0].dir, (1 << (31-11)) | (1 << (31-12))); 468 setbits_be32(&immr->gpio[0].dat, 1 << (31-12)); 469 } 470 471 int mpc8308_get_fpga_done(unsigned fpga) 472 { 473 return pca9698_get_value(0x20, 19); 474 } 475 476 #ifdef CONFIG_FSL_ESDHC 477 int board_mmc_init(bd_t *bd) 478 { 479 immap_t *immr = (immap_t *)CONFIG_SYS_IMMR; 480 sysconf83xx_t *sysconf = &immr->sysconf; 481 482 /* Enable cache snooping in eSDHC system configuration register */ 483 out_be32(&sysconf->sdhccr, 0x02000000); 484 485 return fsl_esdhc_mmc_init(bd); 486 } 487 #endif 488 489 static struct pci_region pcie_regions_0[] = { 490 { 491 .bus_start = CONFIG_SYS_PCIE1_MEM_BASE, 492 .phys_start = CONFIG_SYS_PCIE1_MEM_PHYS, 493 .size = CONFIG_SYS_PCIE1_MEM_SIZE, 494 .flags = PCI_REGION_MEM, 495 }, 496 { 497 .bus_start = CONFIG_SYS_PCIE1_IO_BASE, 498 .phys_start = CONFIG_SYS_PCIE1_IO_PHYS, 499 .size = CONFIG_SYS_PCIE1_IO_SIZE, 500 .flags = PCI_REGION_IO, 501 }, 502 }; 503 504 void pci_init_board(void) 505 { 506 immap_t *immr = (immap_t *)CONFIG_SYS_IMMR; 507 sysconf83xx_t *sysconf = &immr->sysconf; 508 law83xx_t *pcie_law = sysconf->pcielaw; 509 struct pci_region *pcie_reg[] = { pcie_regions_0 }; 510 511 fsl_setup_serdes(CONFIG_FSL_SERDES1, FSL_SERDES_PROTO_PEX, 512 FSL_SERDES_CLK_100, FSL_SERDES_VDD_1V); 513 514 /* Deassert the resets in the control register */ 515 out_be32(&sysconf->pecr1, 0xE0008000); 516 udelay(2000); 517 518 /* Configure PCI Express Local Access Windows */ 519 out_be32(&pcie_law[0].bar, CONFIG_SYS_PCIE1_BASE & LAWBAR_BAR); 520 out_be32(&pcie_law[0].ar, LBLAWAR_EN | LBLAWAR_512MB); 521 522 mpc83xx_pcie_init(1, pcie_reg); 523 } 524 525 ulong board_flash_get_legacy(ulong base, int banknum, flash_info_t *info) 526 { 527 info->portwidth = FLASH_CFI_16BIT; 528 info->chipwidth = FLASH_CFI_BY16; 529 info->interface = FLASH_CFI_X16; 530 return 1; 531 } 532 533 #if defined(CONFIG_OF_BOARD_SETUP) 534 void ft_board_setup(void *blob, bd_t *bd) 535 { 536 ft_cpu_setup(blob, bd); 537 fdt_fixup_dr_usb(blob, bd); 538 fdt_fixup_esdhc(blob, bd); 539 } 540 #endif 541 542 /* 543 * FPGA MII bitbang implementation 544 */ 545 546 struct fpga_mii { 547 unsigned fpga; 548 int mdio; 549 } fpga_mii[] = { 550 { 0, 1}, 551 { 1, 1}, 552 { 2, 1}, 553 { 3, 1}, 554 }; 555 556 static int mii_dummy_init(struct bb_miiphy_bus *bus) 557 { 558 return 0; 559 } 560 561 static int mii_mdio_active(struct bb_miiphy_bus *bus) 562 { 563 struct fpga_mii *fpga_mii = bus->priv; 564 565 if (fpga_mii->mdio) 566 FPGA_SET_REG(fpga_mii->fpga, gpio.set, GPIO_MDIO); 567 else 568 FPGA_SET_REG(fpga_mii->fpga, gpio.clear, GPIO_MDIO); 569 570 return 0; 571 } 572 573 static int mii_mdio_tristate(struct bb_miiphy_bus *bus) 574 { 575 struct fpga_mii *fpga_mii = bus->priv; 576 577 FPGA_SET_REG(fpga_mii->fpga, gpio.set, GPIO_MDIO); 578 579 return 0; 580 } 581 582 static int mii_set_mdio(struct bb_miiphy_bus *bus, int v) 583 { 584 struct fpga_mii *fpga_mii = bus->priv; 585 586 if (v) 587 FPGA_SET_REG(fpga_mii->fpga, gpio.set, GPIO_MDIO); 588 else 589 FPGA_SET_REG(fpga_mii->fpga, gpio.clear, GPIO_MDIO); 590 591 fpga_mii->mdio = v; 592 593 return 0; 594 } 595 596 static int mii_get_mdio(struct bb_miiphy_bus *bus, int *v) 597 { 598 u16 gpio; 599 struct fpga_mii *fpga_mii = bus->priv; 600 601 FPGA_GET_REG(fpga_mii->fpga, gpio.read, &gpio); 602 603 *v = ((gpio & GPIO_MDIO) != 0); 604 605 return 0; 606 } 607 608 static int mii_set_mdc(struct bb_miiphy_bus *bus, int v) 609 { 610 struct fpga_mii *fpga_mii = bus->priv; 611 612 if (v) 613 FPGA_SET_REG(fpga_mii->fpga, gpio.set, GPIO_MDC); 614 else 615 FPGA_SET_REG(fpga_mii->fpga, gpio.clear, GPIO_MDC); 616 617 return 0; 618 } 619 620 static int mii_delay(struct bb_miiphy_bus *bus) 621 { 622 udelay(1); 623 624 return 0; 625 } 626 627 struct bb_miiphy_bus bb_miiphy_buses[] = { 628 { 629 .name = "board0", 630 .init = mii_dummy_init, 631 .mdio_active = mii_mdio_active, 632 .mdio_tristate = mii_mdio_tristate, 633 .set_mdio = mii_set_mdio, 634 .get_mdio = mii_get_mdio, 635 .set_mdc = mii_set_mdc, 636 .delay = mii_delay, 637 .priv = &fpga_mii[0], 638 }, 639 { 640 .name = "board1", 641 .init = mii_dummy_init, 642 .mdio_active = mii_mdio_active, 643 .mdio_tristate = mii_mdio_tristate, 644 .set_mdio = mii_set_mdio, 645 .get_mdio = mii_get_mdio, 646 .set_mdc = mii_set_mdc, 647 .delay = mii_delay, 648 .priv = &fpga_mii[1], 649 }, 650 { 651 .name = "board2", 652 .init = mii_dummy_init, 653 .mdio_active = mii_mdio_active, 654 .mdio_tristate = mii_mdio_tristate, 655 .set_mdio = mii_set_mdio, 656 .get_mdio = mii_get_mdio, 657 .set_mdc = mii_set_mdc, 658 .delay = mii_delay, 659 .priv = &fpga_mii[2], 660 }, 661 { 662 .name = "board3", 663 .init = mii_dummy_init, 664 .mdio_active = mii_mdio_active, 665 .mdio_tristate = mii_mdio_tristate, 666 .set_mdio = mii_set_mdio, 667 .get_mdio = mii_get_mdio, 668 .set_mdc = mii_set_mdc, 669 .delay = mii_delay, 670 .priv = &fpga_mii[3], 671 }, 672 }; 673 674 int bb_miiphy_buses_num = sizeof(bb_miiphy_buses) / 675 sizeof(bb_miiphy_buses[0]); 676