1 /* 2 * (C) Copyright 2010 3 * Dirk Eibach, Guntermann & Drunck GmbH, eibach@gdsys.de 4 * 5 * See file CREDITS for list of people who contributed to this 6 * project. 7 * 8 * This program is free software; you can redistribute it and/or 9 * modify it under the terms of the GNU General Public License as 10 * published by the Free Software Foundation; either version 2 of 11 * the License, or (at your option) any later version. 12 * 13 * This program is distributed in the hope that it will be useful, 14 * but WITHOUT ANY WARRANTY; without even the implied warranty of 15 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the 16 * GNU General Public License for more details. 17 * 18 * You should have received a copy of the GNU General Public License 19 * along with this program; if not, write to the Free Software 20 * Foundation, Inc., 59 Temple Place, Suite 330, Boston, 21 * MA 02111-1307 USA 22 */ 23 24 #include <common.h> 25 #include <i2c.h> 26 #include <asm/io.h> 27 28 #include <gdsys_fpga.h> 29 30 #define CH7301_I2C_ADDR 0x75 31 32 #define ICS8N3QV01_I2C_ADDR 0x6E 33 #define ICS8N3QV01_FREF 114285 34 35 #define SIL1178_MASTER_I2C_ADDRESS 0x38 36 #define SIL1178_SLAVE_I2C_ADDRESS 0x39 37 38 #define PIXCLK_640_480_60 25180000 39 40 #define BASE_WIDTH 32 41 #define BASE_HEIGHT 16 42 #define BUFSIZE (BASE_WIDTH * BASE_HEIGHT) 43 44 enum { 45 CH7301_CM = 0x1c, /* Clock Mode Register */ 46 CH7301_IC = 0x1d, /* Input Clock Register */ 47 CH7301_GPIO = 0x1e, /* GPIO Control Register */ 48 CH7301_IDF = 0x1f, /* Input Data Format Register */ 49 CH7301_CD = 0x20, /* Connection Detect Register */ 50 CH7301_DC = 0x21, /* DAC Control Register */ 51 CH7301_HPD = 0x23, /* Hot Plug Detection Register */ 52 CH7301_TCTL = 0x31, /* DVI Control Input Register */ 53 CH7301_TPCP = 0x33, /* DVI PLL Charge Pump Ctrl Register */ 54 CH7301_TPD = 0x34, /* DVI PLL Divide Register */ 55 CH7301_TPVT = 0x35, /* DVI PLL Supply Control Register */ 56 CH7301_TPF = 0x36, /* DVI PLL Filter Register */ 57 CH7301_TCT = 0x37, /* DVI Clock Test Register */ 58 CH7301_TSTP = 0x48, /* Test Pattern Register */ 59 CH7301_PM = 0x49, /* Power Management register */ 60 CH7301_VID = 0x4a, /* Version ID Register */ 61 CH7301_DID = 0x4b, /* Device ID Register */ 62 CH7301_DSP = 0x56, /* DVI Sync polarity Register */ 63 }; 64 65 #if defined(CONFIG_SYS_ICS8N3QV01) || defined(CONFIG_SYS_SIL1178) 66 static void fpga_iic_write(unsigned screen, u8 slave, u8 reg, u8 data) 67 { 68 ihs_fpga_t *fpga = (ihs_fpga_t *) CONFIG_SYS_FPGA_BASE(screen); 69 ihs_i2c_t *i2c = &fpga->i2c; 70 71 while (in_le16(&fpga->extended_interrupt) & (1 << 12)) 72 ; 73 out_le16(&i2c->write_mailbox_ext, reg | (data << 8)); 74 out_le16(&i2c->write_mailbox, 0xc400 | (slave << 1)); 75 } 76 77 static u8 fpga_iic_read(unsigned screen, u8 slave, u8 reg) 78 { 79 ihs_fpga_t *fpga = (ihs_fpga_t *) CONFIG_SYS_FPGA_BASE(screen); 80 ihs_i2c_t *i2c = &fpga->i2c; 81 unsigned int ctr = 0; 82 83 while (in_le16(&fpga->extended_interrupt) & (1 << 12)) 84 ; 85 out_le16(&fpga->extended_interrupt, 1 << 14); 86 out_le16(&i2c->write_mailbox_ext, reg); 87 out_le16(&i2c->write_mailbox, 0xc000 | (slave << 1)); 88 while (!(in_le16(&fpga->extended_interrupt) & (1 << 14))) { 89 udelay(100000); 90 if (ctr++ > 5) { 91 printf("iic receive timeout\n"); 92 break; 93 } 94 } 95 return in_le16(&i2c->read_mailbox_ext) >> 8; 96 } 97 #endif 98 99 #ifdef CONFIG_SYS_MPC92469AC 100 static void mpc92469ac_calc_parameters(unsigned int fout, 101 unsigned int *post_div, unsigned int *feedback_div) 102 { 103 unsigned int n = *post_div; 104 unsigned int m = *feedback_div; 105 unsigned int a; 106 unsigned int b = 14745600 / 16; 107 108 if (fout < 50169600) 109 n = 8; 110 else if (fout < 100339199) 111 n = 4; 112 else if (fout < 200678399) 113 n = 2; 114 else 115 n = 1; 116 117 a = fout * n + (b / 2); /* add b/2 for proper rounding */ 118 119 m = a / b; 120 121 *post_div = n; 122 *feedback_div = m; 123 } 124 125 static void mpc92469ac_set(unsigned screen, unsigned int fout) 126 { 127 ihs_fpga_t *fpga = (ihs_fpga_t *) CONFIG_SYS_FPGA_BASE(screen); 128 unsigned int n; 129 unsigned int m; 130 unsigned int bitval = 0; 131 mpc92469ac_calc_parameters(fout, &n, &m); 132 133 switch (n) { 134 case 1: 135 bitval = 0x00; 136 break; 137 case 2: 138 bitval = 0x01; 139 break; 140 case 4: 141 bitval = 0x02; 142 break; 143 case 8: 144 bitval = 0x03; 145 break; 146 } 147 148 out_le16(&fpga->mpc3w_control, (bitval << 9) | m); 149 } 150 #endif 151 152 #ifdef CONFIG_SYS_ICS8N3QV01 153 static void ics8n3qv01_calc_parameters(unsigned int fout, 154 unsigned int *_mint, unsigned int *_mfrac, 155 unsigned int *_n) 156 { 157 unsigned int n; 158 unsigned int foutiic; 159 unsigned int fvcoiic; 160 unsigned int mint; 161 unsigned long long mfrac; 162 163 n = 2550000000U / fout; 164 if ((n & 1) && (n > 5)) 165 n -= 1; 166 167 foutiic = fout - (fout / 10000); 168 fvcoiic = foutiic * n; 169 170 mint = fvcoiic / 114285000; 171 if ((mint < 17) || (mint > 63)) 172 printf("ics8n3qv01_calc_parameters: cannot determine mint\n"); 173 174 mfrac = ((unsigned long long)fvcoiic % 114285000LL) * 262144LL 175 / 114285000LL; 176 177 *_mint = mint; 178 *_mfrac = mfrac; 179 *_n = n; 180 } 181 182 static void ics8n3qv01_set(unsigned screen, unsigned int fout) 183 { 184 unsigned int n; 185 unsigned int mint; 186 unsigned int mfrac; 187 u8 reg0, reg4, reg8, reg12, reg18, reg20; 188 189 ics8n3qv01_calc_parameters(fout, &mint, &mfrac, &n); 190 191 reg0 = fpga_iic_read(screen, ICS8N3QV01_I2C_ADDR, 0) & 0xc0; 192 reg0 |= (mint & 0x1f) << 1; 193 reg0 |= (mfrac >> 17) & 0x01; 194 fpga_iic_write(screen, ICS8N3QV01_I2C_ADDR, 0, reg0); 195 196 reg4 = mfrac >> 9; 197 fpga_iic_write(screen, ICS8N3QV01_I2C_ADDR, 4, reg4); 198 199 reg8 = mfrac >> 1; 200 fpga_iic_write(screen, ICS8N3QV01_I2C_ADDR, 8, reg8); 201 202 reg12 = mfrac << 7; 203 reg12 |= n & 0x7f; 204 fpga_iic_write(screen, ICS8N3QV01_I2C_ADDR, 12, reg12); 205 206 reg18 = fpga_iic_read(screen, ICS8N3QV01_I2C_ADDR, 18) & 0x03; 207 reg18 |= 0x20; 208 fpga_iic_write(screen, ICS8N3QV01_I2C_ADDR, 18, reg18); 209 210 reg20 = fpga_iic_read(screen, ICS8N3QV01_I2C_ADDR, 20) & 0x1f; 211 reg20 |= mint & (1 << 5); 212 fpga_iic_write(screen, ICS8N3QV01_I2C_ADDR, 20, reg20); 213 } 214 #endif 215 216 static int osd_write_videomem(unsigned screen, unsigned offset, 217 u16 *data, size_t charcount) 218 { 219 ihs_fpga_t *fpga = 220 (ihs_fpga_t *) CONFIG_SYS_FPGA_BASE(screen); 221 unsigned int k; 222 223 for (k = 0; k < charcount; ++k) { 224 if (offset + k >= BUFSIZE) 225 return -1; 226 out_le16(&fpga->videomem + offset + k, data[k]); 227 } 228 229 return charcount; 230 } 231 232 static int osd_print(cmd_tbl_t *cmdtp, int flag, int argc, char * const argv[]) 233 { 234 unsigned screen; 235 236 for (screen = 0; screen < CONFIG_SYS_OSD_SCREENS; ++screen) { 237 unsigned x; 238 unsigned y; 239 unsigned charcount; 240 unsigned len; 241 u8 color; 242 unsigned int k; 243 u16 buf[BUFSIZE]; 244 char *text; 245 int res; 246 247 if (argc < 5) { 248 cmd_usage(cmdtp); 249 return 1; 250 } 251 252 x = simple_strtoul(argv[1], NULL, 16); 253 y = simple_strtoul(argv[2], NULL, 16); 254 color = simple_strtoul(argv[3], NULL, 16); 255 text = argv[4]; 256 charcount = strlen(text); 257 len = (charcount > BUFSIZE) ? BUFSIZE : charcount; 258 259 for (k = 0; k < len; ++k) 260 buf[k] = (text[k] << 8) | color; 261 262 res = osd_write_videomem(screen, y * BASE_WIDTH + x, buf, len); 263 if (res < 0) 264 return res; 265 } 266 267 return 0; 268 } 269 270 int osd_probe(unsigned screen) 271 { 272 ihs_fpga_t *fpga = (ihs_fpga_t *) CONFIG_SYS_FPGA_BASE(screen); 273 ihs_osd_t *osd = &fpga->osd; 274 u16 version = in_le16(&osd->version); 275 u16 features = in_le16(&osd->features); 276 unsigned width; 277 unsigned height; 278 u8 value; 279 280 width = ((features & 0x3f00) >> 8) + 1; 281 height = (features & 0x001f) + 1; 282 283 printf("OSD%d: Digital-OSD version %01d.%02d, %d" "x%d characters\n", 284 screen, version/100, version%100, width, height); 285 286 #ifdef CONFIG_SYS_CH7301 287 value = i2c_reg_read(CH7301_I2C_ADDR, CH7301_DID); 288 if (value != 0x17) { 289 printf(" Probing CH7301 failed, DID %02x\n", value); 290 return -1; 291 } 292 i2c_reg_write(CH7301_I2C_ADDR, CH7301_TPCP, 0x08); 293 i2c_reg_write(CH7301_I2C_ADDR, CH7301_TPD, 0x16); 294 i2c_reg_write(CH7301_I2C_ADDR, CH7301_TPF, 0x60); 295 i2c_reg_write(CH7301_I2C_ADDR, CH7301_DC, 0x09); 296 i2c_reg_write(CH7301_I2C_ADDR, CH7301_PM, 0xc0); 297 #endif 298 299 #ifdef CONFIG_SYS_MPC92469AC 300 mpc92469ac_set(screen, PIXCLK_640_480_60); 301 #endif 302 303 #ifdef CONFIG_SYS_ICS8N3QV01 304 ics8n3qv01_set(screen, PIXCLK_640_480_60); 305 #endif 306 307 #ifdef CONFIG_SYS_SIL1178 308 value = fpga_iic_read(screen, SIL1178_SLAVE_I2C_ADDRESS, 0x02); 309 if (value != 0x06) { 310 printf(" Probing CH7301 SIL1178, DEV_IDL %02x\n", value); 311 return -1; 312 } 313 /* magic initialization sequence adapted from datasheet */ 314 fpga_iic_write(screen, SIL1178_SLAVE_I2C_ADDRESS, 0x08, 0x36); 315 fpga_iic_write(screen, SIL1178_MASTER_I2C_ADDRESS, 0x0f, 0x44); 316 fpga_iic_write(screen, SIL1178_MASTER_I2C_ADDRESS, 0x0f, 0x4c); 317 fpga_iic_write(screen, SIL1178_MASTER_I2C_ADDRESS, 0x0e, 0x10); 318 fpga_iic_write(screen, SIL1178_MASTER_I2C_ADDRESS, 0x0a, 0x80); 319 fpga_iic_write(screen, SIL1178_MASTER_I2C_ADDRESS, 0x09, 0x30); 320 fpga_iic_write(screen, SIL1178_MASTER_I2C_ADDRESS, 0x0c, 0x89); 321 fpga_iic_write(screen, SIL1178_MASTER_I2C_ADDRESS, 0x0d, 0x60); 322 fpga_iic_write(screen, SIL1178_MASTER_I2C_ADDRESS, 0x08, 0x36); 323 fpga_iic_write(screen, SIL1178_MASTER_I2C_ADDRESS, 0x08, 0x37); 324 #endif 325 326 out_le16(&fpga->videocontrol, 0x0002); 327 out_le16(&osd->control, 0x0049); 328 329 out_le16(&osd->xy_size, ((32 - 1) << 8) | (16 - 1)); 330 331 return 0; 332 } 333 334 int osd_write(cmd_tbl_t *cmdtp, int flag, int argc, char * const argv[]) 335 { 336 unsigned screen; 337 338 for (screen = 0; screen < CONFIG_SYS_OSD_SCREENS; ++screen) { 339 unsigned x; 340 unsigned y; 341 unsigned k; 342 u16 buffer[BASE_WIDTH]; 343 char *rp; 344 u16 *wp = buffer; 345 unsigned count = (argc > 4) ? 346 simple_strtoul(argv[4], NULL, 16) : 1; 347 348 if ((argc < 4) || (strlen(argv[3]) % 4)) { 349 cmd_usage(cmdtp); 350 return 1; 351 } 352 353 x = simple_strtoul(argv[1], NULL, 16); 354 y = simple_strtoul(argv[2], NULL, 16); 355 rp = argv[3]; 356 357 358 while (*rp) { 359 char substr[5]; 360 361 memcpy(substr, rp, 4); 362 substr[4] = 0; 363 *wp = simple_strtoul(substr, NULL, 16); 364 365 rp += 4; 366 wp++; 367 if (wp - buffer > BASE_WIDTH) 368 break; 369 } 370 371 for (k = 0; k < count; ++k) { 372 unsigned offset = 373 y * BASE_WIDTH + x + k * (wp - buffer); 374 osd_write_videomem(screen, offset, buffer, 375 wp - buffer); 376 } 377 } 378 379 return 0; 380 } 381 382 U_BOOT_CMD( 383 osdw, 5, 0, osd_write, 384 "write 16-bit hex encoded buffer to osd memory", 385 "pos_x pos_y buffer count\n" 386 ); 387 388 U_BOOT_CMD( 389 osdp, 5, 0, osd_print, 390 "write ASCII buffer to osd memory", 391 "pos_x pos_y color text\n" 392 ); 393