1 /* 2 * (C) Copyright 2010 3 * Dirk Eibach, Guntermann & Drunck GmbH, eibach@gdsys.de 4 * 5 * SPDX-License-Identifier: GPL-2.0+ 6 */ 7 8 #include <common.h> 9 #include <i2c.h> 10 #include <malloc.h> 11 12 #include <gdsys_fpga.h> 13 14 #define CH7301_I2C_ADDR 0x75 15 16 #define ICS8N3QV01_I2C_ADDR 0x6E 17 #define ICS8N3QV01_FREF 114285000 18 #define ICS8N3QV01_FREF_LL 114285000LL 19 #define ICS8N3QV01_F_DEFAULT_0 156250000LL 20 #define ICS8N3QV01_F_DEFAULT_1 125000000LL 21 #define ICS8N3QV01_F_DEFAULT_2 100000000LL 22 #define ICS8N3QV01_F_DEFAULT_3 25175000LL 23 24 #define SIL1178_MASTER_I2C_ADDRESS 0x38 25 #define SIL1178_SLAVE_I2C_ADDRESS 0x39 26 27 #define PIXCLK_640_480_60 25180000 28 29 enum { 30 CH7301_CM = 0x1c, /* Clock Mode Register */ 31 CH7301_IC = 0x1d, /* Input Clock Register */ 32 CH7301_GPIO = 0x1e, /* GPIO Control Register */ 33 CH7301_IDF = 0x1f, /* Input Data Format Register */ 34 CH7301_CD = 0x20, /* Connection Detect Register */ 35 CH7301_DC = 0x21, /* DAC Control Register */ 36 CH7301_HPD = 0x23, /* Hot Plug Detection Register */ 37 CH7301_TCTL = 0x31, /* DVI Control Input Register */ 38 CH7301_TPCP = 0x33, /* DVI PLL Charge Pump Ctrl Register */ 39 CH7301_TPD = 0x34, /* DVI PLL Divide Register */ 40 CH7301_TPVT = 0x35, /* DVI PLL Supply Control Register */ 41 CH7301_TPF = 0x36, /* DVI PLL Filter Register */ 42 CH7301_TCT = 0x37, /* DVI Clock Test Register */ 43 CH7301_TSTP = 0x48, /* Test Pattern Register */ 44 CH7301_PM = 0x49, /* Power Management register */ 45 CH7301_VID = 0x4a, /* Version ID Register */ 46 CH7301_DID = 0x4b, /* Device ID Register */ 47 CH7301_DSP = 0x56, /* DVI Sync polarity Register */ 48 }; 49 50 unsigned int base_width; 51 unsigned int base_height; 52 size_t bufsize; 53 u16 *buf; 54 55 unsigned int max_osd_screen = CONFIG_SYS_OSD_SCREENS - 1; 56 57 #ifdef CONFIG_SYS_CH7301 58 int ch7301_i2c[] = CONFIG_SYS_CH7301_I2C; 59 #endif 60 61 #if defined(CONFIG_SYS_ICS8N3QV01) || defined(CONFIG_SYS_SIL1178) 62 static void fpga_iic_write(unsigned screen, u8 slave, u8 reg, u8 data) 63 { 64 u16 val; 65 66 do { 67 FPGA_GET_REG(screen, extended_interrupt, &val); 68 } while (val & (1 << 12)); 69 70 FPGA_SET_REG(screen, i2c.write_mailbox_ext, reg | (data << 8)); 71 FPGA_SET_REG(screen, i2c.write_mailbox, 0xc400 | (slave << 1)); 72 } 73 74 static u8 fpga_iic_read(unsigned screen, u8 slave, u8 reg) 75 { 76 unsigned int ctr = 0; 77 u16 val; 78 79 do { 80 FPGA_GET_REG(screen, extended_interrupt, &val); 81 } while (val & (1 << 12)); 82 83 FPGA_SET_REG(screen, extended_interrupt, 1 << 14); 84 FPGA_SET_REG(screen, i2c.write_mailbox_ext, reg); 85 FPGA_SET_REG(screen, i2c.write_mailbox, 0xc000 | (slave << 1)); 86 87 FPGA_GET_REG(screen, extended_interrupt, &val); 88 while (!(val & (1 << 14))) { 89 udelay(100000); 90 if (ctr++ > 5) { 91 printf("iic receive timeout\n"); 92 break; 93 } 94 FPGA_GET_REG(screen, extended_interrupt, &val); 95 } 96 97 FPGA_GET_REG(screen, i2c.read_mailbox_ext, &val); 98 return val >> 8; 99 } 100 #endif 101 102 #ifdef CONFIG_SYS_MPC92469AC 103 static void mpc92469ac_calc_parameters(unsigned int fout, 104 unsigned int *post_div, unsigned int *feedback_div) 105 { 106 unsigned int n = *post_div; 107 unsigned int m = *feedback_div; 108 unsigned int a; 109 unsigned int b = 14745600 / 16; 110 111 if (fout < 50169600) 112 n = 8; 113 else if (fout < 100339199) 114 n = 4; 115 else if (fout < 200678399) 116 n = 2; 117 else 118 n = 1; 119 120 a = fout * n + (b / 2); /* add b/2 for proper rounding */ 121 122 m = a / b; 123 124 *post_div = n; 125 *feedback_div = m; 126 } 127 128 static void mpc92469ac_set(unsigned screen, unsigned int fout) 129 { 130 unsigned int n; 131 unsigned int m; 132 unsigned int bitval = 0; 133 mpc92469ac_calc_parameters(fout, &n, &m); 134 135 switch (n) { 136 case 1: 137 bitval = 0x00; 138 break; 139 case 2: 140 bitval = 0x01; 141 break; 142 case 4: 143 bitval = 0x02; 144 break; 145 case 8: 146 bitval = 0x03; 147 break; 148 } 149 150 FPGA_SET_REG(screen, mpc3w_control, (bitval << 9) | m); 151 } 152 #endif 153 154 #ifdef CONFIG_SYS_ICS8N3QV01 155 156 static unsigned int ics8n3qv01_get_fout_calc(unsigned screen, unsigned index) 157 { 158 unsigned long long n; 159 unsigned long long mint; 160 unsigned long long mfrac; 161 u8 reg_a, reg_b, reg_c, reg_d, reg_f; 162 unsigned long long fout_calc; 163 164 if (index > 3) 165 return 0; 166 167 reg_a = fpga_iic_read(screen, ICS8N3QV01_I2C_ADDR, 0 + index); 168 reg_b = fpga_iic_read(screen, ICS8N3QV01_I2C_ADDR, 4 + index); 169 reg_c = fpga_iic_read(screen, ICS8N3QV01_I2C_ADDR, 8 + index); 170 reg_d = fpga_iic_read(screen, ICS8N3QV01_I2C_ADDR, 12 + index); 171 reg_f = fpga_iic_read(screen, ICS8N3QV01_I2C_ADDR, 20 + index); 172 173 mint = ((reg_a >> 1) & 0x1f) | (reg_f & 0x20); 174 mfrac = ((reg_a & 0x01) << 17) | (reg_b << 9) | (reg_c << 1) 175 | (reg_d >> 7); 176 n = reg_d & 0x7f; 177 178 fout_calc = (mint * ICS8N3QV01_FREF_LL 179 + mfrac * ICS8N3QV01_FREF_LL / 262144LL 180 + ICS8N3QV01_FREF_LL / 524288LL 181 + n / 2) 182 / n 183 * 1000000 184 / (1000000 - 100); 185 186 return fout_calc; 187 } 188 189 190 static void ics8n3qv01_calc_parameters(unsigned int fout, 191 unsigned int *_mint, unsigned int *_mfrac, 192 unsigned int *_n) 193 { 194 unsigned int n; 195 unsigned int foutiic; 196 unsigned int fvcoiic; 197 unsigned int mint; 198 unsigned long long mfrac; 199 200 n = (2215000000U + fout / 2) / fout; 201 if ((n & 1) && (n > 5)) 202 n -= 1; 203 204 foutiic = fout - (fout / 10000); 205 fvcoiic = foutiic * n; 206 207 mint = fvcoiic / 114285000; 208 if ((mint < 17) || (mint > 63)) 209 printf("ics8n3qv01_calc_parameters: cannot determine mint\n"); 210 211 mfrac = ((unsigned long long)fvcoiic % 114285000LL) * 262144LL 212 / 114285000LL; 213 214 *_mint = mint; 215 *_mfrac = mfrac; 216 *_n = n; 217 } 218 219 static void ics8n3qv01_set(unsigned screen, unsigned int fout) 220 { 221 unsigned int n; 222 unsigned int mint; 223 unsigned int mfrac; 224 unsigned int fout_calc; 225 unsigned long long fout_prog; 226 long long off_ppm; 227 u8 reg0, reg4, reg8, reg12, reg18, reg20; 228 229 fout_calc = ics8n3qv01_get_fout_calc(screen, 1); 230 off_ppm = (fout_calc - ICS8N3QV01_F_DEFAULT_1) * 1000000 231 / ICS8N3QV01_F_DEFAULT_1; 232 printf(" PLL is off by %lld ppm\n", off_ppm); 233 fout_prog = (unsigned long long)fout * (unsigned long long)fout_calc 234 / ICS8N3QV01_F_DEFAULT_1; 235 ics8n3qv01_calc_parameters(fout_prog, &mint, &mfrac, &n); 236 237 reg0 = fpga_iic_read(screen, ICS8N3QV01_I2C_ADDR, 0) & 0xc0; 238 reg0 |= (mint & 0x1f) << 1; 239 reg0 |= (mfrac >> 17) & 0x01; 240 fpga_iic_write(screen, ICS8N3QV01_I2C_ADDR, 0, reg0); 241 242 reg4 = mfrac >> 9; 243 fpga_iic_write(screen, ICS8N3QV01_I2C_ADDR, 4, reg4); 244 245 reg8 = mfrac >> 1; 246 fpga_iic_write(screen, ICS8N3QV01_I2C_ADDR, 8, reg8); 247 248 reg12 = mfrac << 7; 249 reg12 |= n & 0x7f; 250 fpga_iic_write(screen, ICS8N3QV01_I2C_ADDR, 12, reg12); 251 252 reg18 = fpga_iic_read(screen, ICS8N3QV01_I2C_ADDR, 18) & 0x03; 253 reg18 |= 0x20; 254 fpga_iic_write(screen, ICS8N3QV01_I2C_ADDR, 18, reg18); 255 256 reg20 = fpga_iic_read(screen, ICS8N3QV01_I2C_ADDR, 20) & 0x1f; 257 reg20 |= mint & (1 << 5); 258 fpga_iic_write(screen, ICS8N3QV01_I2C_ADDR, 20, reg20); 259 } 260 #endif 261 262 static int osd_write_videomem(unsigned screen, unsigned offset, 263 u16 *data, size_t charcount) 264 { 265 unsigned int k; 266 267 for (k = 0; k < charcount; ++k) { 268 if (offset + k >= bufsize) 269 return -1; 270 FPGA_SET_REG(screen, videomem[offset + k], data[k]); 271 } 272 273 return charcount; 274 } 275 276 static int osd_print(cmd_tbl_t *cmdtp, int flag, int argc, char * const argv[]) 277 { 278 unsigned screen; 279 280 for (screen = 0; screen <= max_osd_screen; ++screen) { 281 unsigned x; 282 unsigned y; 283 unsigned charcount; 284 unsigned len; 285 u8 color; 286 unsigned int k; 287 char *text; 288 int res; 289 290 if (argc < 5) { 291 cmd_usage(cmdtp); 292 return 1; 293 } 294 295 x = simple_strtoul(argv[1], NULL, 16); 296 y = simple_strtoul(argv[2], NULL, 16); 297 color = simple_strtoul(argv[3], NULL, 16); 298 text = argv[4]; 299 charcount = strlen(text); 300 len = (charcount > bufsize) ? bufsize : charcount; 301 302 for (k = 0; k < len; ++k) 303 buf[k] = (text[k] << 8) | color; 304 305 res = osd_write_videomem(screen, y * base_width + x, buf, len); 306 if (res < 0) 307 return res; 308 } 309 310 return 0; 311 } 312 313 int osd_probe(unsigned screen) 314 { 315 u16 version; 316 u16 features; 317 u8 value; 318 #ifdef CONFIG_SYS_CH7301 319 int old_bus = i2c_get_bus_num(); 320 #endif 321 322 FPGA_GET_REG(0, osd.version, &version); 323 FPGA_GET_REG(0, osd.features, &features); 324 325 base_width = ((features & 0x3f00) >> 8) + 1; 326 base_height = (features & 0x001f) + 1; 327 bufsize = base_width * base_height; 328 buf = malloc(sizeof(u16) * bufsize); 329 if (!buf) 330 return -1; 331 332 printf("OSD%d: Digital-OSD version %01d.%02d, %d" "x%d characters\n", 333 screen, version/100, version%100, base_width, base_height); 334 335 #ifdef CONFIG_SYS_CH7301 336 i2c_set_bus_num(ch7301_i2c[screen]); 337 value = i2c_reg_read(CH7301_I2C_ADDR, CH7301_DID); 338 if (value != 0x17) { 339 printf(" Probing CH7301 failed, DID %02x\n", value); 340 i2c_set_bus_num(old_bus); 341 return -1; 342 } 343 i2c_reg_write(CH7301_I2C_ADDR, CH7301_TPCP, 0x08); 344 i2c_reg_write(CH7301_I2C_ADDR, CH7301_TPD, 0x16); 345 i2c_reg_write(CH7301_I2C_ADDR, CH7301_TPF, 0x60); 346 i2c_reg_write(CH7301_I2C_ADDR, CH7301_DC, 0x09); 347 i2c_reg_write(CH7301_I2C_ADDR, CH7301_PM, 0xc0); 348 i2c_set_bus_num(old_bus); 349 #endif 350 351 #ifdef CONFIG_SYS_MPC92469AC 352 mpc92469ac_set(screen, PIXCLK_640_480_60); 353 #endif 354 355 #ifdef CONFIG_SYS_ICS8N3QV01 356 ics8n3qv01_set(screen, PIXCLK_640_480_60); 357 #endif 358 359 #ifdef CONFIG_SYS_SIL1178 360 value = fpga_iic_read(screen, SIL1178_SLAVE_I2C_ADDRESS, 0x02); 361 if (value != 0x06) { 362 printf(" Probing CH7301 SIL1178, DEV_IDL %02x\n", value); 363 return -1; 364 } 365 /* magic initialization sequence adapted from datasheet */ 366 fpga_iic_write(screen, SIL1178_SLAVE_I2C_ADDRESS, 0x08, 0x36); 367 fpga_iic_write(screen, SIL1178_MASTER_I2C_ADDRESS, 0x0f, 0x44); 368 fpga_iic_write(screen, SIL1178_MASTER_I2C_ADDRESS, 0x0f, 0x4c); 369 fpga_iic_write(screen, SIL1178_MASTER_I2C_ADDRESS, 0x0e, 0x10); 370 fpga_iic_write(screen, SIL1178_MASTER_I2C_ADDRESS, 0x0a, 0x80); 371 fpga_iic_write(screen, SIL1178_MASTER_I2C_ADDRESS, 0x09, 0x30); 372 fpga_iic_write(screen, SIL1178_MASTER_I2C_ADDRESS, 0x0c, 0x89); 373 fpga_iic_write(screen, SIL1178_MASTER_I2C_ADDRESS, 0x0d, 0x60); 374 fpga_iic_write(screen, SIL1178_MASTER_I2C_ADDRESS, 0x08, 0x36); 375 fpga_iic_write(screen, SIL1178_MASTER_I2C_ADDRESS, 0x08, 0x37); 376 #endif 377 378 FPGA_SET_REG(screen, videocontrol, 0x0002); 379 FPGA_SET_REG(screen, osd.control, 0x0049); 380 381 FPGA_SET_REG(screen, osd.xy_size, ((32 - 1) << 8) | (16 - 1)); 382 FPGA_SET_REG(screen, osd.x_pos, 0x007f); 383 FPGA_SET_REG(screen, osd.y_pos, 0x005f); 384 385 if (screen > max_osd_screen) 386 max_osd_screen = screen; 387 388 return 0; 389 } 390 391 int osd_write(cmd_tbl_t *cmdtp, int flag, int argc, char * const argv[]) 392 { 393 unsigned screen; 394 395 for (screen = 0; screen <= max_osd_screen; ++screen) { 396 unsigned x; 397 unsigned y; 398 unsigned k; 399 u16 buffer[base_width]; 400 char *rp; 401 u16 *wp = buffer; 402 unsigned count = (argc > 4) ? 403 simple_strtoul(argv[4], NULL, 16) : 1; 404 405 if ((argc < 4) || (strlen(argv[3]) % 4)) { 406 cmd_usage(cmdtp); 407 return 1; 408 } 409 410 x = simple_strtoul(argv[1], NULL, 16); 411 y = simple_strtoul(argv[2], NULL, 16); 412 rp = argv[3]; 413 414 415 while (*rp) { 416 char substr[5]; 417 418 memcpy(substr, rp, 4); 419 substr[4] = 0; 420 *wp = simple_strtoul(substr, NULL, 16); 421 422 rp += 4; 423 wp++; 424 if (wp - buffer > base_width) 425 break; 426 } 427 428 for (k = 0; k < count; ++k) { 429 unsigned offset = 430 y * base_width + x + k * (wp - buffer); 431 osd_write_videomem(screen, offset, buffer, 432 wp - buffer); 433 } 434 } 435 436 return 0; 437 } 438 439 U_BOOT_CMD( 440 osdw, 5, 0, osd_write, 441 "write 16-bit hex encoded buffer to osd memory", 442 "pos_x pos_y buffer count\n" 443 ); 444 445 U_BOOT_CMD( 446 osdp, 5, 0, osd_print, 447 "write ASCII buffer to osd memory", 448 "pos_x pos_y color text\n" 449 ); 450