xref: /openbmc/u-boot/board/gdsys/common/dp501.c (revision 03efcb05)
1 /*
2  * (C) Copyright 2012
3  * Dirk Eibach,  Guntermann & Drunck GmbH, dirk.eibach@gdsys.cc
4  *
5  * See file CREDITS for list of people who contributed to this
6  * project.
7  *
8  * This program is free software; you can redistribute it and/or
9  * modify it under the terms of the GNU General Public License as
10  * published by the Free Software Foundation; either version 2 of
11  * the License, or (at your option) any later version.
12  *
13  * This program is distributed in the hope that it will be useful,
14  * but WITHOUT ANY WARRANTY; without even the implied warranty of
15  * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
16  * GNU General Public License for more details.
17  *
18  * You should have received a copy of the GNU General Public License
19  * along with this program; if not, write to the Free Software
20  * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
21  * MA 02111-1307 USA
22  */
23 
24 /* Parade Technologies Inc. DP501 DisplayPort DVI/HDMI Transmitter */
25 
26 #include <common.h>
27 #include <asm/io.h>
28 #include <errno.h>
29 #include <i2c.h>
30 
31 static void dp501_setbits(u8 addr, u8 reg, u8 mask)
32 {
33 	u8 val;
34 
35 	val = i2c_reg_read(addr, reg);
36 	setbits_8(&val, mask);
37 	i2c_reg_write(addr, reg, val);
38 }
39 
40 static void dp501_clrbits(u8 addr, u8 reg, u8 mask)
41 {
42 	u8 val;
43 
44 	val = i2c_reg_read(addr, reg);
45 	clrbits_8(&val, mask);
46 	i2c_reg_write(addr, reg, val);
47 }
48 
49 static int dp501_detect_cable_adapter(u8 addr)
50 {
51 	u8 val = i2c_reg_read(addr, 0x00);
52 
53 	return !(val & 0x04);
54 }
55 
56 static void dp501_link_training(u8 addr)
57 {
58 	u8 val;
59 
60 	val = i2c_reg_read(addr, 0x51);
61 	i2c_reg_write(addr, 0x5d, val); /* set link_bw */
62 	val = i2c_reg_read(addr, 0x52);
63 	i2c_reg_write(addr, 0x5e, val); /* set lane_cnt */
64 	val = i2c_reg_read(addr, 0x53);
65 	i2c_reg_write(addr, 0x5c, val); /* set downspread_ctl */
66 
67 	i2c_reg_write(addr, 0x5f, 0x0d); /* start training */
68 }
69 
70 void dp501_powerup(u8 addr)
71 {
72 	dp501_clrbits(addr, 0x0a, 0x30); /* power on encoder */
73 	i2c_reg_write(addr, 0x27, 0x30); /* Hardware auto detect DVO timing */
74 	dp501_setbits(addr, 0x72, 0x80); /* DPCD read enable */
75 	dp501_setbits(addr, 0x30, 0x20); /* RS polynomial select */
76 	i2c_reg_write(addr, 0x71, 0x20); /* Enable Aux burst write */
77 	dp501_setbits(addr, 0x78, 0x30); /* Disable HPD2 IRQ */
78 	dp501_clrbits(addr, 0x2f, 0x40); /* Link FIFO reset selection */
79 	i2c_reg_write(addr, 0x24, 0xc0); /* SDR mode 0, ext. H/VSYNC */
80 	i2c_reg_write(addr + 2, 0x24, 0x02); /* clock input single ended */
81 
82 	if (dp501_detect_cable_adapter(addr)) {
83 		printf("DVI/HDMI cable adapter detected\n");
84 		i2c_reg_write(addr, 0x5e, 0x04); /* enable 4 channel */
85 		dp501_clrbits(addr, 0x00, 0x08); /* DVI/HDMI HDCP operation */
86 	} else {
87 		printf("no DVI/HDMI cable adapter detected\n");
88 		i2c_reg_write(addr + 2, 0x00, 0x18); /* driving strength */
89 		i2c_reg_write(addr + 2, 0x03, 0x06); /* driving strength */
90 		i2c_reg_write(addr, 0x2c, 0x00); /* configure N value */
91 		i2c_reg_write(addr, 0x2d, 0x00); /* configure N value */
92 		i2c_reg_write(addr, 0x2e, 0x0c); /* configure N value */
93 		i2c_reg_write(addr, 0x76, 0xff); /* clear all interrupt */
94 		dp501_setbits(addr, 0x78, 0x03); /* clear all interrupt */
95 		i2c_reg_write(addr, 0x75, 0xf8); /* aux channel reset */
96 		i2c_reg_write(addr, 0x75, 0x00); /* clear aux channel reset */
97 		i2c_reg_write(addr, 0x87, 0x70); /* set retry counter as 7 */
98 		dp501_setbits(addr, 0x00, 0x08); /* for DP HDCP operation */
99 
100 		dp501_link_training(addr);
101 	}
102 }
103 
104 void dp501_powerdown(u8 addr)
105 {
106 	dp501_setbits(addr, 0x0a, 0x30); /* power down encoder, standby mode */
107 }
108