1 /* 2 * (C) Copyright 2012 3 * Dirk Eibach, Guntermann & Drunck GmbH, dirk.eibach@gdsys.cc 4 * 5 * SPDX-License-Identifier: GPL-2.0+ 6 */ 7 8 /* Parade Technologies Inc. DP501 DisplayPort DVI/HDMI Transmitter */ 9 10 #include <common.h> 11 #include <asm/io.h> 12 #include <errno.h> 13 #include <i2c.h> 14 15 static void dp501_setbits(u8 addr, u8 reg, u8 mask) 16 { 17 u8 val; 18 19 val = i2c_reg_read(addr, reg); 20 setbits_8(&val, mask); 21 i2c_reg_write(addr, reg, val); 22 } 23 24 static void dp501_clrbits(u8 addr, u8 reg, u8 mask) 25 { 26 u8 val; 27 28 val = i2c_reg_read(addr, reg); 29 clrbits_8(&val, mask); 30 i2c_reg_write(addr, reg, val); 31 } 32 33 static int dp501_detect_cable_adapter(u8 addr) 34 { 35 u8 val = i2c_reg_read(addr, 0x00); 36 37 return !(val & 0x04); 38 } 39 40 static void dp501_link_training(u8 addr) 41 { 42 u8 val; 43 u8 link_bw; 44 u8 max_lane_cnt; 45 u8 lane_cnt; 46 47 val = i2c_reg_read(addr, 0x51); 48 if (val >= 0x0a) 49 link_bw = 0x0a; 50 else 51 link_bw = 0x06; 52 if (link_bw != val) 53 printf("DP sink supports %d Mbps link rate, set to %d Mbps\n", 54 val * 270, link_bw * 270); 55 i2c_reg_write(addr, 0x5d, link_bw); /* set link_bw */ 56 val = i2c_reg_read(addr, 0x52); 57 max_lane_cnt = val & 0x1f; 58 if (max_lane_cnt >= 4) 59 lane_cnt = 4; 60 else 61 lane_cnt = max_lane_cnt; 62 if (lane_cnt != max_lane_cnt) 63 printf("DP sink supports %d lanes, set to %d lanes\n", 64 max_lane_cnt, lane_cnt); 65 i2c_reg_write(addr, 0x5e, lane_cnt | (val & 0x80)); /* set lane_cnt */ 66 val = i2c_reg_read(addr, 0x53); 67 i2c_reg_write(addr, 0x5c, val); /* set downspread_ctl */ 68 69 i2c_reg_write(addr, 0x5f, 0x0d); /* start training */ 70 } 71 72 void dp501_powerup(u8 addr) 73 { 74 dp501_clrbits(addr, 0x0a, 0x30); /* power on encoder */ 75 dp501_setbits(addr, 0x0a, 0x0e); /* block HDCP and MCCS on I2C bride*/ 76 i2c_reg_write(addr, 0x27, 0x30); /* Hardware auto detect DVO timing */ 77 dp501_setbits(addr, 0x72, 0x80); /* DPCD read enable */ 78 dp501_setbits(addr, 0x30, 0x20); /* RS polynomial select */ 79 i2c_reg_write(addr, 0x71, 0x20); /* Enable Aux burst write */ 80 dp501_setbits(addr, 0x78, 0x30); /* Disable HPD2 IRQ */ 81 dp501_clrbits(addr, 0x2f, 0x40); /* Link FIFO reset selection */ 82 dp501_clrbits(addr, 0x60, 0x20); /* Enable scrambling */ 83 84 #ifdef CONFIG_SYS_DP501_VCAPCTRL0 85 i2c_reg_write(addr, 0x24, CONFIG_SYS_DP501_VCAPCTRL0); 86 #else 87 i2c_reg_write(addr, 0x24, 0xc0); /* SDR mode 0, ext. H/VSYNC */ 88 #endif 89 90 #ifdef CONFIG_SYS_DP501_DIFFERENTIAL 91 i2c_reg_write(addr + 2, 0x24, 0x10); /* clock input differential */ 92 i2c_reg_write(addr + 2, 0x25, 0x04); 93 i2c_reg_write(addr + 2, 0x26, 0x10); 94 #else 95 i2c_reg_write(addr + 2, 0x24, 0x02); /* clock input single ended */ 96 #endif 97 98 i2c_reg_write(addr + 2, 0x1a, 0x04); /* SPDIF input method TTL */ 99 100 i2c_reg_write(addr + 2, 0x00, 0x18); /* driving strength */ 101 i2c_reg_write(addr + 2, 0x03, 0x06); /* driving strength */ 102 i2c_reg_write(addr, 0x2c, 0x00); /* configure N value */ 103 i2c_reg_write(addr, 0x2d, 0x00); /* configure N value */ 104 i2c_reg_write(addr, 0x2e, 0x0c); /* configure N value */ 105 i2c_reg_write(addr, 0x76, 0xff); /* clear all interrupt */ 106 dp501_setbits(addr, 0x78, 0x03); /* clear all interrupt */ 107 i2c_reg_write(addr, 0x75, 0xf8); /* aux channel reset */ 108 i2c_reg_write(addr, 0x75, 0x00); /* clear aux channel reset */ 109 i2c_reg_write(addr, 0x87, 0x7f); /* set retry counter as 7 110 retry interval 400us */ 111 112 if (dp501_detect_cable_adapter(addr)) { 113 printf("DVI/HDMI cable adapter detected\n"); 114 i2c_reg_write(addr, 0x5e, 0x04); /* enable 4 channel */ 115 dp501_clrbits(addr, 0x00, 0x08); /* DVI/HDMI HDCP operation */ 116 } else { 117 printf("no DVI/HDMI cable adapter detected\n"); 118 dp501_setbits(addr, 0x00, 0x08); /* for DP HDCP operation */ 119 120 dp501_link_training(addr); 121 } 122 } 123 124 void dp501_powerdown(u8 addr) 125 { 126 dp501_setbits(addr, 0x0a, 0x30); /* power down encoder, standby mode */ 127 } 128