1 /*
2  * Copyright (C) 2015 Stefan Roese <sr@denx.de>
3  * Copyright (C) 2016 Mario Six <mario.six@gdsys.cc>
4  *
5  * SPDX-License-Identifier:	GPL-2.0+
6  */
7 
8 #include <common.h>
9 #include <dm.h>
10 #include <miiphy.h>
11 #include <tpm.h>
12 #include <asm/io.h>
13 #include <asm/arch/cpu.h>
14 #include <asm-generic/gpio.h>
15 
16 #include "../drivers/ddr/marvell/a38x/ddr3_a38x_topology.h"
17 #include "../arch/arm/mach-mvebu/serdes/a38x/high_speed_env_spec.h"
18 
19 #include "keyprogram.h"
20 #include "dt_helpers.h"
21 #include "hydra.h"
22 #include "ihs_phys.h"
23 
24 DECLARE_GLOBAL_DATA_PTR;
25 
26 #define ETH_PHY_CTRL_REG		0
27 #define ETH_PHY_CTRL_POWER_DOWN_BIT	11
28 #define ETH_PHY_CTRL_POWER_DOWN_MASK	(1 << ETH_PHY_CTRL_POWER_DOWN_BIT)
29 
30 #define DB_GP_88F68XX_GPP_OUT_ENA_LOW	0x7fffffff
31 #define DB_GP_88F68XX_GPP_OUT_ENA_MID	0xffffefff
32 
33 #define DB_GP_88F68XX_GPP_OUT_VAL_LOW	0x0
34 #define DB_GP_88F68XX_GPP_OUT_VAL_MID	0x00001000
35 #define DB_GP_88F68XX_GPP_POL_LOW	0x0
36 #define DB_GP_88F68XX_GPP_POL_MID	0x0
37 
38 /*
39  * Define the DDR layout / topology here in the board file. This will
40  * be used by the DDR3 init code in the SPL U-Boot version to configure
41  * the DDR3 controller.
42  */
43 static struct hws_topology_map ddr_topology_map = {
44 	0x1, /* active interfaces */
45 	/* cs_mask, mirror, dqs_swap, ck_swap X PUPs */
46 	{ { { {0x1, 0, 0, 0},
47 	      {0x1, 0, 0, 0},
48 	      {0x1, 0, 0, 0},
49 	      {0x1, 0, 0, 0},
50 	      {0x1, 0, 0, 0} },
51 	    SPEED_BIN_DDR_1600K,	/* speed_bin */
52 	    BUS_WIDTH_16,		/* memory_width */
53 	    MEM_4G,			/* mem_size */
54 	    DDR_FREQ_533,		/* frequency */
55 	    0, 0,			/* cas_l cas_wl */
56 	    HWS_TEMP_LOW} },		/* temperature */
57 	5,				/* Num Of Bus Per Interface*/
58 	BUS_MASK_32BIT			/* Busses mask */
59 };
60 
61 static struct serdes_map serdes_topology_map[] = {
62 	{SGMII0, SERDES_SPEED_1_25_GBPS, SERDES_DEFAULT_MODE, 0, 0},
63 	{USB3_HOST0, SERDES_SPEED_5_GBPS, SERDES_DEFAULT_MODE, 0, 0},
64 	/* SATA tx polarity is inverted */
65 	{SATA1, SERDES_SPEED_3_GBPS, SERDES_DEFAULT_MODE, 0, 1},
66 	{SGMII2, SERDES_SPEED_1_25_GBPS, SERDES_DEFAULT_MODE, 0, 0},
67 	{DEFAULT_SERDES, SERDES_SPEED_3_GBPS, SERDES_DEFAULT_MODE, 0, 0},
68 	{PEX2, SERDES_SPEED_5_GBPS, PEX_ROOT_COMPLEX_X1, 0, 0}
69 };
70 
71 int hws_board_topology_load(struct serdes_map **serdes_map_array, u8 *count)
72 {
73 	*serdes_map_array = serdes_topology_map;
74 	*count = ARRAY_SIZE(serdes_topology_map);
75 	return 0;
76 }
77 
78 void board_pex_config(void)
79 {
80 #ifdef CONFIG_SPL_BUILD
81 	uint k;
82 	struct gpio_desc gpio = {};
83 
84 	if (!request_gpio_by_name(&gpio, "pca9698@22", 31, "fpga-program-gpio")) {
85 		/* prepare FPGA reconfiguration */
86 		dm_gpio_set_dir_flags(&gpio, GPIOD_IS_OUT);
87 		dm_gpio_set_value(&gpio, 0);
88 
89 		/* give lunatic PCIe clock some time to stabilize */
90 		mdelay(500);
91 
92 		/* start FPGA reconfiguration */
93 		dm_gpio_set_dir_flags(&gpio, GPIOD_IS_IN);
94 	}
95 
96 	/* wait for FPGA done */
97 	if (!request_gpio_by_name(&gpio, "pca9698@22", 19, "fpga-done-gpio")) {
98 		for (k = 0; k < 20; ++k) {
99 			if (dm_gpio_get_value(&gpio)) {
100 				printf("FPGA done after %u rounds\n", k);
101 				break;
102 			}
103 			mdelay(100);
104 		}
105 	}
106 
107 	/* disable FPGA reset */
108 	if (!request_gpio_by_name(&gpio, "gpio@18100", 6, "cpu-to-fpga-reset")) {
109 		dm_gpio_set_dir_flags(&gpio, GPIOD_IS_OUT);
110 		dm_gpio_set_value(&gpio, 1);
111 	}
112 
113 	/* wait for FPGA ready */
114 	if (!request_gpio_by_name(&gpio, "pca9698@22", 27, "fpga-ready-gpio")) {
115 		for (k = 0; k < 2; ++k) {
116 			if (!dm_gpio_get_value(&gpio))
117 				break;
118 			mdelay(100);
119 		}
120 	}
121 #endif
122 }
123 
124 struct hws_topology_map *ddr3_get_topology_map(void)
125 {
126 	return &ddr_topology_map;
127 }
128 
129 int board_early_init_f(void)
130 {
131 #ifdef CONFIG_SPL_BUILD
132 	/* Configure MPP */
133 	writel(0x00111111, MVEBU_MPP_BASE + 0x00);
134 	writel(0x40040000, MVEBU_MPP_BASE + 0x04);
135 	writel(0x00466444, MVEBU_MPP_BASE + 0x08);
136 	writel(0x00043300, MVEBU_MPP_BASE + 0x0c);
137 	writel(0x44400000, MVEBU_MPP_BASE + 0x10);
138 	writel(0x20000334, MVEBU_MPP_BASE + 0x14);
139 	writel(0x40000000, MVEBU_MPP_BASE + 0x18);
140 	writel(0x00004444, MVEBU_MPP_BASE + 0x1c);
141 
142 	/* Set GPP Out value */
143 	writel(DB_GP_88F68XX_GPP_OUT_VAL_LOW, MVEBU_GPIO0_BASE + 0x00);
144 	writel(DB_GP_88F68XX_GPP_OUT_VAL_MID, MVEBU_GPIO1_BASE + 0x00);
145 
146 	/* Set GPP Polarity */
147 	writel(DB_GP_88F68XX_GPP_POL_LOW, MVEBU_GPIO0_BASE + 0x0c);
148 	writel(DB_GP_88F68XX_GPP_POL_MID, MVEBU_GPIO1_BASE + 0x0c);
149 
150 	/* Set GPP Out Enable */
151 	writel(DB_GP_88F68XX_GPP_OUT_ENA_LOW, MVEBU_GPIO0_BASE + 0x04);
152 	writel(DB_GP_88F68XX_GPP_OUT_ENA_MID, MVEBU_GPIO1_BASE + 0x04);
153 #endif
154 
155 	return 0;
156 }
157 
158 int board_init(void)
159 {
160 	/* Address of boot parameters */
161 	gd->bd->bi_boot_params = mvebu_sdram_bar(0) + 0x100;
162 
163 	return 0;
164 }
165 
166 #ifndef CONFIG_SPL_BUILD
167 void init_host_phys(struct mii_dev *bus)
168 {
169 	uint k;
170 
171 	for (k = 0; k < 2; ++k) {
172 		struct phy_device *phydev;
173 
174 		phydev = phy_find_by_mask(bus, 1 << k,
175 					  PHY_INTERFACE_MODE_SGMII);
176 
177 		if (phydev)
178 			phy_config(phydev);
179 	}
180 }
181 
182 int ccdc_eth_init(void)
183 {
184 	uint k;
185 	uint octo_phy_mask = 0;
186 	int ret;
187 	struct mii_dev *bus;
188 
189 	/* Init SoC's phys */
190 	bus = miiphy_get_dev_by_name("ethernet@34000");
191 
192 	if (bus)
193 		init_host_phys(bus);
194 
195 	bus = miiphy_get_dev_by_name("ethernet@70000");
196 
197 	if (bus)
198 		init_host_phys(bus);
199 
200 	/* Init octo phys */
201 	octo_phy_mask = calculate_octo_phy_mask();
202 
203 	printf("IHS PHYS: %08x", octo_phy_mask);
204 
205 	ret = init_octo_phys(octo_phy_mask);
206 
207 	if (ret)
208 		return ret;
209 
210 	printf("\n");
211 
212 	if (!get_fpga()) {
213 		puts("fpga was NULL\n");
214 		return 1;
215 	}
216 
217 	/* reset all FPGA-QSGMII instances */
218 	for (k = 0; k < 80; ++k)
219 		writel(1 << 31, get_fpga()->qsgmii_port_state[k]);
220 
221 	udelay(100);
222 
223 	for (k = 0; k < 80; ++k)
224 		writel(0, get_fpga()->qsgmii_port_state[k]);
225 	return 0;
226 }
227 
228 #endif
229 
230 int board_late_init(void)
231 {
232 #ifndef CONFIG_SPL_BUILD
233 	hydra_initialize();
234 #endif
235 	return 0;
236 }
237 
238 int board_fix_fdt(void *rw_fdt_blob)
239 {
240 	struct udevice *bus = NULL;
241 	uint k;
242 	char name[64];
243 	int err;
244 
245 	err = uclass_get_device_by_name(UCLASS_I2C, "i2c@11000", &bus);
246 
247 	if (err) {
248 		printf("Could not get I2C bus.\n");
249 		return err;
250 	}
251 
252 	for (k = 0x21; k <= 0x26; k++) {
253 		snprintf(name, 64,
254 			 "/soc/internal-regs/i2c@11000/pca9698@%02x", k);
255 
256 		if (!dm_i2c_simple_probe(bus, k))
257 			fdt_disable_by_ofname(rw_fdt_blob, name);
258 	}
259 
260 	return 0;
261 }
262 
263 int last_stage_init(void)
264 {
265 #ifndef CONFIG_SPL_BUILD
266 	ccdc_eth_init();
267 #endif
268 	if (tpm_init() || tpm_startup(TPM_ST_CLEAR) ||
269 	    tpm_continue_self_test()) {
270 		return 1;
271 	}
272 
273 	mdelay(37);
274 
275 	flush_keys();
276 	load_and_run_keyprog();
277 
278 	return 0;
279 }
280