1 // SPDX-License-Identifier: GPL-2.0+ 2 /* 3 * Copyright (C) 2014 Gateworks Corporation 4 * Author: Tim Harvey <tharvey@gateworks.com> 5 */ 6 7 #include <common.h> 8 #include <asm/io.h> 9 #include <asm/arch/crm_regs.h> 10 #include <asm/arch/mx6-ddr.h> 11 #include <asm/arch/mx6-pins.h> 12 #include <asm/arch/sys_proto.h> 13 #include <asm/mach-imx/boot_mode.h> 14 #include <asm/mach-imx/iomux-v3.h> 15 #include <asm/mach-imx/mxc_i2c.h> 16 #include <environment.h> 17 #include <i2c.h> 18 #include <spl.h> 19 20 #include "gsc.h" 21 #include "common.h" 22 23 #define RTT_NOM_120OHM /* use 120ohm Rtt_nom vs 60ohm (lower power) */ 24 #define GSC_EEPROM_DDR_SIZE 0x2B /* enum (512,1024,2048) MB */ 25 #define GSC_EEPROM_DDR_WIDTH 0x2D /* enum (32,64) bit */ 26 27 /* configure MX6Q/DUAL mmdc DDR io registers */ 28 struct mx6dq_iomux_ddr_regs mx6dq_ddr_ioregs = { 29 /* SDCLK[0:1], CAS, RAS, Reset: Differential input, 40ohm */ 30 .dram_sdclk_0 = 0x00020030, 31 .dram_sdclk_1 = 0x00020030, 32 .dram_cas = 0x00020030, 33 .dram_ras = 0x00020030, 34 .dram_reset = 0x00020030, 35 /* SDCKE[0:1]: 100k pull-up */ 36 .dram_sdcke0 = 0x00003000, 37 .dram_sdcke1 = 0x00003000, 38 /* SDBA2: pull-up disabled */ 39 .dram_sdba2 = 0x00000000, 40 /* SDODT[0:1]: 100k pull-up, 40 ohm */ 41 .dram_sdodt0 = 0x00003030, 42 .dram_sdodt1 = 0x00003030, 43 /* SDQS[0:7]: Differential input, 40 ohm */ 44 .dram_sdqs0 = 0x00000030, 45 .dram_sdqs1 = 0x00000030, 46 .dram_sdqs2 = 0x00000030, 47 .dram_sdqs3 = 0x00000030, 48 .dram_sdqs4 = 0x00000030, 49 .dram_sdqs5 = 0x00000030, 50 .dram_sdqs6 = 0x00000030, 51 .dram_sdqs7 = 0x00000030, 52 53 /* DQM[0:7]: Differential input, 40 ohm */ 54 .dram_dqm0 = 0x00020030, 55 .dram_dqm1 = 0x00020030, 56 .dram_dqm2 = 0x00020030, 57 .dram_dqm3 = 0x00020030, 58 .dram_dqm4 = 0x00020030, 59 .dram_dqm5 = 0x00020030, 60 .dram_dqm6 = 0x00020030, 61 .dram_dqm7 = 0x00020030, 62 }; 63 64 /* configure MX6Q/DUAL mmdc GRP io registers */ 65 struct mx6dq_iomux_grp_regs mx6dq_grp_ioregs = { 66 /* DDR3 */ 67 .grp_ddr_type = 0x000c0000, 68 .grp_ddrmode_ctl = 0x00020000, 69 /* disable DDR pullups */ 70 .grp_ddrpke = 0x00000000, 71 /* ADDR[00:16], SDBA[0:1]: 40 ohm */ 72 .grp_addds = 0x00000030, 73 /* CS0/CS1/SDBA2/CKE0/CKE1/SDWE: 40 ohm */ 74 .grp_ctlds = 0x00000030, 75 /* DATA[00:63]: Differential input, 40 ohm */ 76 .grp_ddrmode = 0x00020000, 77 .grp_b0ds = 0x00000030, 78 .grp_b1ds = 0x00000030, 79 .grp_b2ds = 0x00000030, 80 .grp_b3ds = 0x00000030, 81 .grp_b4ds = 0x00000030, 82 .grp_b5ds = 0x00000030, 83 .grp_b6ds = 0x00000030, 84 .grp_b7ds = 0x00000030, 85 }; 86 87 /* configure MX6SOLO/DUALLITE mmdc DDR io registers */ 88 struct mx6sdl_iomux_ddr_regs mx6sdl_ddr_ioregs = { 89 /* SDCLK[0:1], CAS, RAS, Reset: Differential input, 40ohm */ 90 .dram_sdclk_0 = 0x00020030, 91 .dram_sdclk_1 = 0x00020030, 92 .dram_cas = 0x00020030, 93 .dram_ras = 0x00020030, 94 .dram_reset = 0x00020030, 95 /* SDCKE[0:1]: 100k pull-up */ 96 .dram_sdcke0 = 0x00003000, 97 .dram_sdcke1 = 0x00003000, 98 /* SDBA2: pull-up disabled */ 99 .dram_sdba2 = 0x00000000, 100 /* SDODT[0:1]: 100k pull-up, 40 ohm */ 101 .dram_sdodt0 = 0x00003030, 102 .dram_sdodt1 = 0x00003030, 103 /* SDQS[0:7]: Differential input, 40 ohm */ 104 .dram_sdqs0 = 0x00000030, 105 .dram_sdqs1 = 0x00000030, 106 .dram_sdqs2 = 0x00000030, 107 .dram_sdqs3 = 0x00000030, 108 .dram_sdqs4 = 0x00000030, 109 .dram_sdqs5 = 0x00000030, 110 .dram_sdqs6 = 0x00000030, 111 .dram_sdqs7 = 0x00000030, 112 113 /* DQM[0:7]: Differential input, 40 ohm */ 114 .dram_dqm0 = 0x00020030, 115 .dram_dqm1 = 0x00020030, 116 .dram_dqm2 = 0x00020030, 117 .dram_dqm3 = 0x00020030, 118 .dram_dqm4 = 0x00020030, 119 .dram_dqm5 = 0x00020030, 120 .dram_dqm6 = 0x00020030, 121 .dram_dqm7 = 0x00020030, 122 }; 123 124 /* configure MX6SOLO/DUALLITE mmdc GRP io registers */ 125 struct mx6sdl_iomux_grp_regs mx6sdl_grp_ioregs = { 126 /* DDR3 */ 127 .grp_ddr_type = 0x000c0000, 128 /* SDQS[0:7]: Differential input, 40 ohm */ 129 .grp_ddrmode_ctl = 0x00020000, 130 /* disable DDR pullups */ 131 .grp_ddrpke = 0x00000000, 132 /* ADDR[00:16], SDBA[0:1]: 40 ohm */ 133 .grp_addds = 0x00000030, 134 /* CS0/CS1/SDBA2/CKE0/CKE1/SDWE: 40 ohm */ 135 .grp_ctlds = 0x00000030, 136 /* DATA[00:63]: Differential input, 40 ohm */ 137 .grp_ddrmode = 0x00020000, 138 .grp_b0ds = 0x00000030, 139 .grp_b1ds = 0x00000030, 140 .grp_b2ds = 0x00000030, 141 .grp_b3ds = 0x00000030, 142 .grp_b4ds = 0x00000030, 143 .grp_b5ds = 0x00000030, 144 .grp_b6ds = 0x00000030, 145 .grp_b7ds = 0x00000030, 146 }; 147 148 /* MT41K64M16JT-125 (1Gb density) */ 149 static struct mx6_ddr3_cfg mt41k64m16jt_125 = { 150 .mem_speed = 1600, 151 .density = 1, 152 .width = 16, 153 .banks = 8, 154 .rowaddr = 13, 155 .coladdr = 10, 156 .pagesz = 2, 157 .trcd = 1375, 158 .trcmin = 4875, 159 .trasmin = 3500, 160 }; 161 162 /* MT41K128M16JT-125 (2Gb density) */ 163 static struct mx6_ddr3_cfg mt41k128m16jt_125 = { 164 .mem_speed = 1600, 165 .density = 2, 166 .width = 16, 167 .banks = 8, 168 .rowaddr = 14, 169 .coladdr = 10, 170 .pagesz = 2, 171 .trcd = 1375, 172 .trcmin = 4875, 173 .trasmin = 3500, 174 }; 175 176 /* MT41K256M16HA-125 (4Gb density) */ 177 static struct mx6_ddr3_cfg mt41k256m16ha_125 = { 178 .mem_speed = 1600, 179 .density = 4, 180 .width = 16, 181 .banks = 8, 182 .rowaddr = 15, 183 .coladdr = 10, 184 .pagesz = 2, 185 .trcd = 1375, 186 .trcmin = 4875, 187 .trasmin = 3500, 188 }; 189 190 /* MT41K512M16HA-125 (8Gb density) */ 191 static struct mx6_ddr3_cfg mt41k512m16ha_125 = { 192 .mem_speed = 1600, 193 .density = 8, 194 .width = 16, 195 .banks = 8, 196 .rowaddr = 16, 197 .coladdr = 10, 198 .pagesz = 2, 199 .trcd = 1375, 200 .trcmin = 4875, 201 .trasmin = 3500, 202 }; 203 204 /* 205 * calibration - these are the various CPU/DDR3 combinations we support 206 */ 207 static struct mx6_mmdc_calibration mx6sdl_64x16_mmdc_calib = { 208 /* write leveling calibration determine */ 209 .p0_mpwldectrl0 = 0x004C004E, 210 .p0_mpwldectrl1 = 0x00440044, 211 /* Read DQS Gating calibration */ 212 .p0_mpdgctrl0 = 0x42440247, 213 .p0_mpdgctrl1 = 0x02310232, 214 /* Read Calibration: DQS delay relative to DQ read access */ 215 .p0_mprddlctl = 0x45424746, 216 /* Write Calibration: DQ/DM delay relative to DQS write access */ 217 .p0_mpwrdlctl = 0x33382C31, 218 }; 219 220 /* TODO: update with calibrated values */ 221 static struct mx6_mmdc_calibration mx6dq_64x64_mmdc_calib = { 222 /* write leveling calibration determine */ 223 .p0_mpwldectrl0 = 0x00190017, 224 .p0_mpwldectrl1 = 0x00140026, 225 .p1_mpwldectrl0 = 0x0021001C, 226 .p1_mpwldectrl1 = 0x0011001D, 227 /* Read DQS Gating calibration */ 228 .p0_mpdgctrl0 = 0x43380347, 229 .p0_mpdgctrl1 = 0x433C034D, 230 .p1_mpdgctrl0 = 0x032C0324, 231 .p1_mpdgctrl1 = 0x03310232, 232 /* Read Calibration: DQS delay relative to DQ read access */ 233 .p0_mprddlctl = 0x3C313539, 234 .p1_mprddlctl = 0x37343141, 235 /* Write Calibration: DQ/DM delay relative to DQS write access */ 236 .p0_mpwrdlctl = 0x36393C39, 237 .p1_mpwrdlctl = 0x42344438, 238 }; 239 240 /* TODO: update with calibrated values */ 241 static struct mx6_mmdc_calibration mx6sdl_64x64_mmdc_calib = { 242 /* write leveling calibration determine */ 243 .p0_mpwldectrl0 = 0x003C003C, 244 .p0_mpwldectrl1 = 0x001F002A, 245 .p1_mpwldectrl0 = 0x00330038, 246 .p1_mpwldectrl1 = 0x0022003F, 247 /* Read DQS Gating calibration */ 248 .p0_mpdgctrl0 = 0x42410244, 249 .p0_mpdgctrl1 = 0x4234023A, 250 .p1_mpdgctrl0 = 0x022D022D, 251 .p1_mpdgctrl1 = 0x021C0228, 252 /* Read Calibration: DQS delay relative to DQ read access */ 253 .p0_mprddlctl = 0x484A4C4B, 254 .p1_mprddlctl = 0x4B4D4E4B, 255 /* Write Calibration: DQ/DM delay relative to DQS write access */ 256 .p0_mpwrdlctl = 0x33342B32, 257 .p1_mpwrdlctl = 0x3933332B, 258 }; 259 260 static struct mx6_mmdc_calibration mx6dq_256x16_mmdc_calib = { 261 /* write leveling calibration determine */ 262 .p0_mpwldectrl0 = 0x001B0016, 263 .p0_mpwldectrl1 = 0x000C000E, 264 /* Read DQS Gating calibration */ 265 .p0_mpdgctrl0 = 0x4324033A, 266 .p0_mpdgctrl1 = 0x00000000, 267 /* Read Calibration: DQS delay relative to DQ read access */ 268 .p0_mprddlctl = 0x40403438, 269 /* Write Calibration: DQ/DM delay relative to DQS write access */ 270 .p0_mpwrdlctl = 0x40403D36, 271 }; 272 273 static struct mx6_mmdc_calibration mx6sdl_256x16_mmdc_calib = { 274 /* write leveling calibration determine */ 275 .p0_mpwldectrl0 = 0x00420043, 276 .p0_mpwldectrl1 = 0x0016001A, 277 /* Read DQS Gating calibration */ 278 .p0_mpdgctrl0 = 0x4238023B, 279 .p0_mpdgctrl1 = 0x00000000, 280 /* Read Calibration: DQS delay relative to DQ read access */ 281 .p0_mprddlctl = 0x40404849, 282 /* Write Calibration: DQ/DM delay relative to DQS write access */ 283 .p0_mpwrdlctl = 0x40402E2F, 284 }; 285 286 static struct mx6_mmdc_calibration mx6dq_128x32_mmdc_calib = { 287 /* write leveling calibration determine */ 288 .p0_mpwldectrl0 = 0x00190017, 289 .p0_mpwldectrl1 = 0x00140026, 290 /* Read DQS Gating calibration */ 291 .p0_mpdgctrl0 = 0x43380347, 292 .p0_mpdgctrl1 = 0x433C034D, 293 /* Read Calibration: DQS delay relative to DQ read access */ 294 .p0_mprddlctl = 0x3C313539, 295 /* Write Calibration: DQ/DM delay relative to DQS write access */ 296 .p0_mpwrdlctl = 0x36393C39, 297 }; 298 299 static struct mx6_mmdc_calibration mx6sdl_128x32_mmdc_calib = { 300 /* write leveling calibration determine */ 301 .p0_mpwldectrl0 = 0x003C003C, 302 .p0_mpwldectrl1 = 0x001F002A, 303 /* Read DQS Gating calibration */ 304 .p0_mpdgctrl0 = 0x42410244, 305 .p0_mpdgctrl1 = 0x4234023A, 306 /* Read Calibration: DQS delay relative to DQ read access */ 307 .p0_mprddlctl = 0x484A4C4B, 308 /* Write Calibration: DQ/DM delay relative to DQS write access */ 309 .p0_mpwrdlctl = 0x33342B32, 310 }; 311 312 static struct mx6_mmdc_calibration mx6dq_128x64_mmdc_calib = { 313 /* write leveling calibration determine */ 314 .p0_mpwldectrl0 = 0x00190017, 315 .p0_mpwldectrl1 = 0x00140026, 316 .p1_mpwldectrl0 = 0x0021001C, 317 .p1_mpwldectrl1 = 0x0011001D, 318 /* Read DQS Gating calibration */ 319 .p0_mpdgctrl0 = 0x43380347, 320 .p0_mpdgctrl1 = 0x433C034D, 321 .p1_mpdgctrl0 = 0x032C0324, 322 .p1_mpdgctrl1 = 0x03310232, 323 /* Read Calibration: DQS delay relative to DQ read access */ 324 .p0_mprddlctl = 0x3C313539, 325 .p1_mprddlctl = 0x37343141, 326 /* Write Calibration: DQ/DM delay relative to DQS write access */ 327 .p0_mpwrdlctl = 0x36393C39, 328 .p1_mpwrdlctl = 0x42344438, 329 }; 330 331 static struct mx6_mmdc_calibration mx6sdl_128x64_mmdc_calib = { 332 /* write leveling calibration determine */ 333 .p0_mpwldectrl0 = 0x003C003C, 334 .p0_mpwldectrl1 = 0x001F002A, 335 .p1_mpwldectrl0 = 0x00330038, 336 .p1_mpwldectrl1 = 0x0022003F, 337 /* Read DQS Gating calibration */ 338 .p0_mpdgctrl0 = 0x42410244, 339 .p0_mpdgctrl1 = 0x4234023A, 340 .p1_mpdgctrl0 = 0x022D022D, 341 .p1_mpdgctrl1 = 0x021C0228, 342 /* Read Calibration: DQS delay relative to DQ read access */ 343 .p0_mprddlctl = 0x484A4C4B, 344 .p1_mprddlctl = 0x4B4D4E4B, 345 /* Write Calibration: DQ/DM delay relative to DQS write access */ 346 .p0_mpwrdlctl = 0x33342B32, 347 .p1_mpwrdlctl = 0x3933332B, 348 }; 349 350 static struct mx6_mmdc_calibration mx6dq_256x32_mmdc_calib = { 351 /* write leveling calibration determine */ 352 .p0_mpwldectrl0 = 0x001E001A, 353 .p0_mpwldectrl1 = 0x0026001F, 354 /* Read DQS Gating calibration */ 355 .p0_mpdgctrl0 = 0x43370349, 356 .p0_mpdgctrl1 = 0x032D0327, 357 /* Read Calibration: DQS delay relative to DQ read access */ 358 .p0_mprddlctl = 0x3D303639, 359 /* Write Calibration: DQ/DM delay relative to DQS write access */ 360 .p0_mpwrdlctl = 0x32363934, 361 }; 362 363 static struct mx6_mmdc_calibration mx6sdl_256x32_mmdc_calib = { 364 /* write leveling calibration determine */ 365 .p0_mpwldectrl0 = 0X00480047, 366 .p0_mpwldectrl1 = 0X003D003F, 367 /* Read DQS Gating calibration */ 368 .p0_mpdgctrl0 = 0X423E0241, 369 .p0_mpdgctrl1 = 0X022B022C, 370 /* Read Calibration: DQS delay relative to DQ read access */ 371 .p0_mprddlctl = 0X49454A4A, 372 /* Write Calibration: DQ/DM delay relative to DQS write access */ 373 .p0_mpwrdlctl = 0X2E372C32, 374 }; 375 376 static struct mx6_mmdc_calibration mx6dq_256x64_mmdc_calib = { 377 /* write leveling calibration determine */ 378 .p0_mpwldectrl0 = 0X00220021, 379 .p0_mpwldectrl1 = 0X00200030, 380 .p1_mpwldectrl0 = 0X002D0027, 381 .p1_mpwldectrl1 = 0X00150026, 382 /* Read DQS Gating calibration */ 383 .p0_mpdgctrl0 = 0x43330342, 384 .p0_mpdgctrl1 = 0x0339034A, 385 .p1_mpdgctrl0 = 0x032F0325, 386 .p1_mpdgctrl1 = 0x032F022E, 387 /* Read Calibration: DQS delay relative to DQ read access */ 388 .p0_mprddlctl = 0X3A2E3437, 389 .p1_mprddlctl = 0X35312F3F, 390 /* Write Calibration: DQ/DM delay relative to DQS write access */ 391 .p0_mpwrdlctl = 0X33363B37, 392 .p1_mpwrdlctl = 0X40304239, 393 }; 394 395 static struct mx6_mmdc_calibration mx6sdl_256x64_mmdc_calib = { 396 /* write leveling calibration determine */ 397 .p0_mpwldectrl0 = 0x0048004A, 398 .p0_mpwldectrl1 = 0x003F004A, 399 .p1_mpwldectrl0 = 0x001E0028, 400 .p1_mpwldectrl1 = 0x002C0043, 401 /* Read DQS Gating calibration */ 402 .p0_mpdgctrl0 = 0x02250219, 403 .p0_mpdgctrl1 = 0x01790202, 404 .p1_mpdgctrl0 = 0x02080208, 405 .p1_mpdgctrl1 = 0x016C0175, 406 /* Read Calibration: DQS delay relative to DQ read access */ 407 .p0_mprddlctl = 0x4A4C4D4C, 408 .p1_mprddlctl = 0x494C4A48, 409 /* Write Calibration: DQ/DM delay relative to DQS write access */ 410 .p0_mpwrdlctl = 0x403F3437, 411 .p1_mpwrdlctl = 0x383A3930, 412 }; 413 414 static struct mx6_mmdc_calibration mx6sdl_256x64x2_mmdc_calib = { 415 /* write leveling calibration determine */ 416 .p0_mpwldectrl0 = 0x001F003F, 417 .p0_mpwldectrl1 = 0x001F001F, 418 .p1_mpwldectrl0 = 0x001F004E, 419 .p1_mpwldectrl1 = 0x0059001F, 420 /* Read DQS Gating calibration */ 421 .p0_mpdgctrl0 = 0x42220225, 422 .p0_mpdgctrl1 = 0x0213021F, 423 .p1_mpdgctrl0 = 0x022C0242, 424 .p1_mpdgctrl1 = 0x022C0244, 425 /* Read Calibration: DQS delay relative to DQ read access */ 426 .p0_mprddlctl = 0x474A4C4A, 427 .p1_mprddlctl = 0x48494C45, 428 /* Write Calibration: DQ/DM delay relative to DQS write access */ 429 .p0_mpwrdlctl = 0x3F3F3F36, 430 .p1_mpwrdlctl = 0x3F36363F, 431 }; 432 433 static struct mx6_mmdc_calibration mx6sdl_128x64x2_mmdc_calib = { 434 /* write leveling calibration determine */ 435 .p0_mpwldectrl0 = 0x001F003F, 436 .p0_mpwldectrl1 = 0x001F001F, 437 .p1_mpwldectrl0 = 0x001F004E, 438 .p1_mpwldectrl1 = 0x0059001F, 439 /* Read DQS Gating calibration */ 440 .p0_mpdgctrl0 = 0x42220225, 441 .p0_mpdgctrl1 = 0x0213021F, 442 .p1_mpdgctrl0 = 0x022C0242, 443 .p1_mpdgctrl1 = 0x022C0244, 444 /* Read Calibration: DQS delay relative to DQ read access */ 445 .p0_mprddlctl = 0x474A4C4A, 446 .p1_mprddlctl = 0x48494C45, 447 /* Write Calibration: DQ/DM delay relative to DQS write access */ 448 .p0_mpwrdlctl = 0x3F3F3F36, 449 .p1_mpwrdlctl = 0x3F36363F, 450 }; 451 452 static struct mx6_mmdc_calibration mx6dq_512x32_mmdc_calib = { 453 /* write leveling calibration determine */ 454 .p0_mpwldectrl0 = 0x002A0025, 455 .p0_mpwldectrl1 = 0x003A002A, 456 /* Read DQS Gating calibration */ 457 .p0_mpdgctrl0 = 0x43430356, 458 .p0_mpdgctrl1 = 0x033C0335, 459 /* Read Calibration: DQS delay relative to DQ read access */ 460 .p0_mprddlctl = 0x4B373F42, 461 /* Write Calibration: DQ/DM delay relative to DQS write access */ 462 .p0_mpwrdlctl = 0x303E3C36, 463 }; 464 465 static struct mx6_mmdc_calibration mx6dq_512x64_mmdc_calib = { 466 /* write leveling calibration determine */ 467 .p0_mpwldectrl0 = 0x00230020, 468 .p0_mpwldectrl1 = 0x002F002A, 469 .p1_mpwldectrl0 = 0x001D0027, 470 .p1_mpwldectrl1 = 0x00100023, 471 /* Read DQS Gating calibration */ 472 .p0_mpdgctrl0 = 0x03250339, 473 .p0_mpdgctrl1 = 0x031C0316, 474 .p1_mpdgctrl0 = 0x03210331, 475 .p1_mpdgctrl1 = 0x031C025A, 476 /* Read Calibration: DQS delay relative to DQ read access */ 477 .p0_mprddlctl = 0x40373C40, 478 .p1_mprddlctl = 0x3A373646, 479 /* Write Calibration: DQ/DM delay relative to DQS write access */ 480 .p0_mpwrdlctl = 0x2E353933, 481 .p1_mpwrdlctl = 0x3C2F3F35, 482 }; 483 484 static void spl_dram_init(int width, int size_mb, int board_model) 485 { 486 struct mx6_ddr3_cfg *mem = NULL; 487 struct mx6_mmdc_calibration *calib = NULL; 488 struct mx6_ddr_sysinfo sysinfo = { 489 /* width of data bus:0=16,1=32,2=64 */ 490 .dsize = width/32, 491 /* config for full 4GB range so that get_mem_size() works */ 492 .cs_density = 32, /* 32Gb per CS */ 493 /* single chip select */ 494 .ncs = 1, 495 .cs1_mirror = 0, 496 .rtt_wr = 1 /*DDR3_RTT_60_OHM*/, /* RTT_Wr = RZQ/4 */ 497 #ifdef RTT_NOM_120OHM 498 .rtt_nom = 2 /*DDR3_RTT_120_OHM*/, /* RTT_Nom = RZQ/2 */ 499 #else 500 .rtt_nom = 1 /*DDR3_RTT_60_OHM*/, /* RTT_Nom = RZQ/4 */ 501 #endif 502 .walat = 1, /* Write additional latency */ 503 .ralat = 5, /* Read additional latency */ 504 .mif3_mode = 3, /* Command prediction working mode */ 505 .bi_on = 1, /* Bank interleaving enabled */ 506 .sde_to_rst = 0x10, /* 14 cycles, 200us (JEDEC default) */ 507 .rst_to_cke = 0x23, /* 33 cycles, 500us (JEDEC default) */ 508 .pd_fast_exit = 1, /* enable precharge power-down fast exit */ 509 .ddr_type = DDR_TYPE_DDR3, 510 .refsel = 1, /* Refresh cycles at 32KHz */ 511 .refr = 7, /* 8 refresh commands per refresh cycle */ 512 }; 513 514 /* 515 * MMDC Calibration requires the following data: 516 * mx6_mmdc_calibration - board-specific calibration (routing delays) 517 * these calibration values depend on board routing, SoC, and DDR 518 * mx6_ddr_sysinfo - board-specific memory architecture (width/cs/etc) 519 * mx6_ddr_cfg - chip specific timing/layout details 520 */ 521 if (width == 16 && size_mb == 128) { 522 mem = &mt41k64m16jt_125; 523 if (is_cpu_type(MXC_CPU_MX6Q)) 524 ; 525 else 526 calib = &mx6sdl_64x16_mmdc_calib; 527 debug("1gB density\n"); 528 } else if (width == 16 && size_mb == 256) { 529 /* 1x 2Gb density chip - same calib as 2x 2Gb */ 530 mem = &mt41k128m16jt_125; 531 if (is_cpu_type(MXC_CPU_MX6Q)) 532 calib = &mx6dq_128x32_mmdc_calib; 533 else 534 calib = &mx6sdl_128x32_mmdc_calib; 535 debug("2gB density\n"); 536 } else if (width == 16 && size_mb == 512) { 537 mem = &mt41k256m16ha_125; 538 if (is_cpu_type(MXC_CPU_MX6Q)) 539 calib = &mx6dq_256x16_mmdc_calib; 540 else 541 calib = &mx6sdl_256x16_mmdc_calib; 542 debug("4gB density\n"); 543 } else if (width == 16 && size_mb == 1024) { 544 mem = &mt41k512m16ha_125; 545 if (is_cpu_type(MXC_CPU_MX6Q)) 546 calib = &mx6dq_512x32_mmdc_calib; 547 debug("8gB density\n"); 548 } else if (width == 32 && size_mb == 256) { 549 /* Same calib as width==16, size==128 */ 550 mem = &mt41k64m16jt_125; 551 if (is_cpu_type(MXC_CPU_MX6Q)) 552 ; 553 else 554 calib = &mx6sdl_64x16_mmdc_calib; 555 debug("1gB density\n"); 556 } else if (width == 32 && size_mb == 512) { 557 mem = &mt41k128m16jt_125; 558 if (is_cpu_type(MXC_CPU_MX6Q)) 559 calib = &mx6dq_128x32_mmdc_calib; 560 else 561 calib = &mx6sdl_128x32_mmdc_calib; 562 debug("2gB density\n"); 563 } else if (width == 32 && size_mb == 1024) { 564 mem = &mt41k256m16ha_125; 565 if (is_cpu_type(MXC_CPU_MX6Q)) 566 calib = &mx6dq_256x32_mmdc_calib; 567 else 568 calib = &mx6sdl_256x32_mmdc_calib; 569 debug("4gB density\n"); 570 } else if (width == 32 && size_mb == 2048) { 571 mem = &mt41k512m16ha_125; 572 if (is_cpu_type(MXC_CPU_MX6Q)) 573 calib = &mx6dq_512x32_mmdc_calib; 574 debug("8gB density\n"); 575 } else if (width == 64 && size_mb == 512) { 576 mem = &mt41k64m16jt_125; 577 debug("1gB density\n"); 578 if (is_cpu_type(MXC_CPU_MX6Q)) 579 calib = &mx6dq_64x64_mmdc_calib; 580 else 581 calib = &mx6sdl_64x64_mmdc_calib; 582 } else if (width == 64 && size_mb == 1024) { 583 mem = &mt41k128m16jt_125; 584 if (is_cpu_type(MXC_CPU_MX6Q)) 585 calib = &mx6dq_128x64_mmdc_calib; 586 else 587 calib = &mx6sdl_128x64_mmdc_calib; 588 debug("2gB density\n"); 589 } else if (width == 64 && size_mb == 2048) { 590 switch(board_model) { 591 case GW5905: 592 /* 8xMT41K128M16 (2GiB) fly-by mirrored 2-chipsels */ 593 mem = &mt41k128m16jt_125; 594 debug("2gB density - 2 chipsel\n"); 595 if (!is_cpu_type(MXC_CPU_MX6Q)) { 596 calib = &mx6sdl_128x64x2_mmdc_calib; 597 sysinfo.ncs = 2; 598 sysinfo.cs_density = 10; /* CS0_END=39 */ 599 sysinfo.cs1_mirror = 1; /* mirror enabled */ 600 } 601 break; 602 default: 603 mem = &mt41k256m16ha_125; 604 if (is_cpu_type(MXC_CPU_MX6Q)) 605 calib = &mx6dq_256x64_mmdc_calib; 606 else 607 calib = &mx6sdl_256x64_mmdc_calib; 608 debug("4gB density\n"); 609 break; 610 } 611 } else if (width == 64 && size_mb == 4096) { 612 switch(board_model) { 613 case GW5903: 614 /* 8xMT41K256M16 (4GiB) fly-by mirrored 2-chipsels */ 615 mem = &mt41k256m16ha_125; 616 debug("4gB density - 2 chipsel\n"); 617 if (!is_cpu_type(MXC_CPU_MX6Q)) { 618 calib = &mx6sdl_256x64x2_mmdc_calib; 619 sysinfo.ncs = 2; 620 sysinfo.cs_density = 18; /* CS0_END=71 */ 621 sysinfo.cs1_mirror = 1; /* mirror enabled */ 622 } 623 break; 624 default: 625 mem = &mt41k512m16ha_125; 626 if (is_cpu_type(MXC_CPU_MX6Q)) 627 calib = &mx6dq_512x64_mmdc_calib; 628 debug("8gB density\n"); 629 break; 630 } 631 } 632 633 if (!(mem && calib)) { 634 puts("Error: Invalid Calibration/Board Configuration\n"); 635 printf("MEM : %s\n", mem ? "OKAY" : "NULL"); 636 printf("CALIB : %s\n", calib ? "OKAY" : "NULL"); 637 printf("CPUTYPE: %s\n", 638 is_cpu_type(MXC_CPU_MX6Q) ? "IMX6Q" : "IMX6DL"); 639 printf("SIZE_MB: %d\n", size_mb); 640 printf("WIDTH : %d\n", width); 641 hang(); 642 } 643 644 if (is_cpu_type(MXC_CPU_MX6Q)) 645 mx6dq_dram_iocfg(width, &mx6dq_ddr_ioregs, 646 &mx6dq_grp_ioregs); 647 else 648 mx6sdl_dram_iocfg(width, &mx6sdl_ddr_ioregs, 649 &mx6sdl_grp_ioregs); 650 mx6_dram_cfg(&sysinfo, calib, mem); 651 } 652 653 static void ccgr_init(void) 654 { 655 struct mxc_ccm_reg *ccm = (struct mxc_ccm_reg *)CCM_BASE_ADDR; 656 657 writel(0x00C03F3F, &ccm->CCGR0); 658 writel(0x0030FC03, &ccm->CCGR1); 659 writel(0x0FFFC000, &ccm->CCGR2); 660 writel(0x3FF00000, &ccm->CCGR3); 661 writel(0xFFFFF300, &ccm->CCGR4); /* enable NAND/GPMI/BCH clks */ 662 writel(0x0F0000C3, &ccm->CCGR5); 663 writel(0x000003FF, &ccm->CCGR6); 664 } 665 666 /* 667 * called from C runtime startup code (arch/arm/lib/crt0.S:_main) 668 * - we have a stack and a place to store GD, both in SRAM 669 * - no variable global data is available 670 */ 671 void board_init_f(ulong dummy) 672 { 673 struct ventana_board_info ventana_info; 674 int board_model; 675 676 /* setup clock gating */ 677 ccgr_init(); 678 679 /* setup AIPS and disable watchdog */ 680 arch_cpu_init(); 681 682 /* setup AXI */ 683 gpr_init(); 684 685 /* iomux and setup of uart/i2c */ 686 setup_iomux_uart(); 687 setup_ventana_i2c(0); 688 setup_ventana_i2c(1); 689 690 /* setup GP timer */ 691 timer_init(); 692 693 /* UART clocks enabled and gd valid - init serial console */ 694 preloader_console_init(); 695 696 /* read/validate EEPROM info to determine board model and SDRAM cfg */ 697 board_model = read_eeprom(CONFIG_I2C_GSC, &ventana_info); 698 699 /* configure model-specific gpio */ 700 setup_iomux_gpio(board_model, &ventana_info); 701 702 /* provide some some default: 32bit 128MB */ 703 if (GW_UNKNOWN == board_model) 704 hang(); 705 706 /* configure MMDC for SDRAM width/size and per-model calibration */ 707 spl_dram_init(8 << ventana_info.sdram_width, 708 16 << ventana_info.sdram_size, 709 board_model); 710 } 711 712 void board_boot_order(u32 *spl_boot_list) 713 { 714 spl_boot_list[0] = spl_boot_device(); 715 switch (spl_boot_list[0]) { 716 case BOOT_DEVICE_NAND: 717 spl_boot_list[1] = BOOT_DEVICE_MMC1; 718 spl_boot_list[2] = BOOT_DEVICE_UART; 719 break; 720 case BOOT_DEVICE_MMC1: 721 spl_boot_list[1] = BOOT_DEVICE_UART; 722 break; 723 } 724 } 725 726 /* called from board_init_r after gd setup if CONFIG_SPL_BOARD_INIT defined */ 727 /* its our chance to print info about boot device */ 728 void spl_board_init(void) 729 { 730 /* determine boot device from SRC_SBMR1 (BOOT_CFG[4:1]) or SRC_GPR9 */ 731 u32 boot_device = spl_boot_device(); 732 733 switch (boot_device) { 734 case BOOT_DEVICE_MMC1: 735 puts("Booting from MMC\n"); 736 break; 737 case BOOT_DEVICE_NAND: 738 puts("Booting from NAND\n"); 739 break; 740 case BOOT_DEVICE_SATA: 741 puts("Booting from SATA\n"); 742 break; 743 default: 744 puts("Unknown boot device\n"); 745 } 746 747 /* PMIC init */ 748 setup_pmic(); 749 } 750 751 #ifdef CONFIG_SPL_OS_BOOT 752 /* return 1 if we wish to boot to uboot vs os (falcon mode) */ 753 int spl_start_uboot(void) 754 { 755 unsigned char ret = 1; 756 757 debug("%s\n", __func__); 758 #ifdef CONFIG_SPL_ENV_SUPPORT 759 env_init(); 760 env_load(); 761 debug("boot_os=%s\n", env_get("boot_os")); 762 if (env_get_yesno("boot_os") == 1) 763 ret = 0; 764 #else 765 /* use i2c-0:0x50:0x00 for falcon boot mode (0=linux, else uboot) */ 766 i2c_set_bus_num(0); 767 gsc_i2c_read(0x50, 0x0, 1, &ret, 1); 768 #endif 769 if (!ret) 770 gsc_boot_wd_disable(); 771 772 debug("%s booting %s\n", __func__, ret ? "uboot" : "linux"); 773 return ret; 774 } 775 #endif 776