1 /* 2 * Copyright (C) 2014 Gateworks Corporation 3 * Author: Tim Harvey <tharvey@gateworks.com> 4 * 5 * SPDX-License-Identifier: GPL-2.0+ 6 */ 7 8 #include <common.h> 9 #include <i2c.h> 10 #include <asm/io.h> 11 #include <asm/arch/crm_regs.h> 12 #include <asm/arch/iomux.h> 13 #include <asm/arch/mx6-ddr.h> 14 #include <asm/arch/mx6-pins.h> 15 #include <asm/arch/sys_proto.h> 16 #include <asm/imx-common/boot_mode.h> 17 #include <asm/imx-common/iomux-v3.h> 18 #include <asm/imx-common/mxc_i2c.h> 19 #include <spl.h> 20 21 #include "ventana_eeprom.h" 22 23 DECLARE_GLOBAL_DATA_PTR; 24 25 #define RTT_NOM_120OHM /* use 120ohm Rtt_nom vs 60ohm (lower power) */ 26 #define I2C_GSC 0 27 #define GSC_EEPROM_ADDR 0x51 28 #define GSC_EEPROM_DDR_SIZE 0x2B /* enum (512,1024,2048) MB */ 29 #define GSC_EEPROM_DDR_WIDTH 0x2D /* enum (32,64) bit */ 30 #define I2C_PAD_CTRL (PAD_CTL_PUS_100K_UP | \ 31 PAD_CTL_SPEED_MED | PAD_CTL_DSE_40ohm | PAD_CTL_HYS | \ 32 PAD_CTL_ODE | PAD_CTL_SRE_FAST) 33 #define PC MUX_PAD_CTRL(I2C_PAD_CTRL) 34 #define CONFIG_SYS_I2C_SPEED 100000 35 36 /* I2C1: GSC */ 37 static struct i2c_pads_info mx6q_i2c_pad_info0 = { 38 .scl = { 39 .i2c_mode = MX6Q_PAD_EIM_D21__I2C1_SCL | PC, 40 .gpio_mode = MX6Q_PAD_EIM_D21__GPIO3_IO21 | PC, 41 .gp = IMX_GPIO_NR(3, 21) 42 }, 43 .sda = { 44 .i2c_mode = MX6Q_PAD_EIM_D28__I2C1_SDA | PC, 45 .gpio_mode = MX6Q_PAD_EIM_D28__GPIO3_IO28 | PC, 46 .gp = IMX_GPIO_NR(3, 28) 47 } 48 }; 49 static struct i2c_pads_info mx6dl_i2c_pad_info0 = { 50 .scl = { 51 .i2c_mode = MX6DL_PAD_EIM_D21__I2C1_SCL | PC, 52 .gpio_mode = MX6DL_PAD_EIM_D21__GPIO3_IO21 | PC, 53 .gp = IMX_GPIO_NR(3, 21) 54 }, 55 .sda = { 56 .i2c_mode = MX6DL_PAD_EIM_D28__I2C1_SDA | PC, 57 .gpio_mode = MX6DL_PAD_EIM_D28__GPIO3_IO28 | PC, 58 .gp = IMX_GPIO_NR(3, 28) 59 } 60 }; 61 62 static void i2c_setup_iomux(void) 63 { 64 if (is_cpu_type(MXC_CPU_MX6Q)) 65 setup_i2c(0, CONFIG_SYS_I2C_SPEED, 0x7f, &mx6q_i2c_pad_info0); 66 else 67 setup_i2c(0, CONFIG_SYS_I2C_SPEED, 0x7f, &mx6dl_i2c_pad_info0); 68 } 69 70 /* configure MX6Q/DUAL mmdc DDR io registers */ 71 struct mx6dq_iomux_ddr_regs mx6dq_ddr_ioregs = { 72 /* SDCLK[0:1], CAS, RAS, Reset: Differential input, 40ohm */ 73 .dram_sdclk_0 = 0x00020030, 74 .dram_sdclk_1 = 0x00020030, 75 .dram_cas = 0x00020030, 76 .dram_ras = 0x00020030, 77 .dram_reset = 0x00020030, 78 /* SDCKE[0:1]: 100k pull-up */ 79 .dram_sdcke0 = 0x00003000, 80 .dram_sdcke1 = 0x00003000, 81 /* SDBA2: pull-up disabled */ 82 .dram_sdba2 = 0x00000000, 83 /* SDODT[0:1]: 100k pull-up, 40 ohm */ 84 .dram_sdodt0 = 0x00003030, 85 .dram_sdodt1 = 0x00003030, 86 /* SDQS[0:7]: Differential input, 40 ohm */ 87 .dram_sdqs0 = 0x00000030, 88 .dram_sdqs1 = 0x00000030, 89 .dram_sdqs2 = 0x00000030, 90 .dram_sdqs3 = 0x00000030, 91 .dram_sdqs4 = 0x00000030, 92 .dram_sdqs5 = 0x00000030, 93 .dram_sdqs6 = 0x00000030, 94 .dram_sdqs7 = 0x00000030, 95 96 /* DQM[0:7]: Differential input, 40 ohm */ 97 .dram_dqm0 = 0x00020030, 98 .dram_dqm1 = 0x00020030, 99 .dram_dqm2 = 0x00020030, 100 .dram_dqm3 = 0x00020030, 101 .dram_dqm4 = 0x00020030, 102 .dram_dqm5 = 0x00020030, 103 .dram_dqm6 = 0x00020030, 104 .dram_dqm7 = 0x00020030, 105 }; 106 107 /* configure MX6Q/DUAL mmdc GRP io registers */ 108 struct mx6dq_iomux_grp_regs mx6dq_grp_ioregs = { 109 /* DDR3 */ 110 .grp_ddr_type = 0x000c0000, 111 .grp_ddrmode_ctl = 0x00020000, 112 /* disable DDR pullups */ 113 .grp_ddrpke = 0x00000000, 114 /* ADDR[00:16], SDBA[0:1]: 40 ohm */ 115 .grp_addds = 0x00000030, 116 /* CS0/CS1/SDBA2/CKE0/CKE1/SDWE: 40 ohm */ 117 .grp_ctlds = 0x00000030, 118 /* DATA[00:63]: Differential input, 40 ohm */ 119 .grp_ddrmode = 0x00020000, 120 .grp_b0ds = 0x00000030, 121 .grp_b1ds = 0x00000030, 122 .grp_b2ds = 0x00000030, 123 .grp_b3ds = 0x00000030, 124 .grp_b4ds = 0x00000030, 125 .grp_b5ds = 0x00000030, 126 .grp_b6ds = 0x00000030, 127 .grp_b7ds = 0x00000030, 128 }; 129 130 /* configure MX6SOLO/DUALLITE mmdc DDR io registers */ 131 struct mx6sdl_iomux_ddr_regs mx6sdl_ddr_ioregs = { 132 /* SDCLK[0:1], CAS, RAS, Reset: Differential input, 40ohm */ 133 .dram_sdclk_0 = 0x00020030, 134 .dram_sdclk_1 = 0x00020030, 135 .dram_cas = 0x00020030, 136 .dram_ras = 0x00020030, 137 .dram_reset = 0x00020030, 138 /* SDCKE[0:1]: 100k pull-up */ 139 .dram_sdcke0 = 0x00003000, 140 .dram_sdcke1 = 0x00003000, 141 /* SDBA2: pull-up disabled */ 142 .dram_sdba2 = 0x00000000, 143 /* SDODT[0:1]: 100k pull-up, 40 ohm */ 144 .dram_sdodt0 = 0x00003030, 145 .dram_sdodt1 = 0x00003030, 146 /* SDQS[0:7]: Differential input, 40 ohm */ 147 .dram_sdqs0 = 0x00000030, 148 .dram_sdqs1 = 0x00000030, 149 .dram_sdqs2 = 0x00000030, 150 .dram_sdqs3 = 0x00000030, 151 .dram_sdqs4 = 0x00000030, 152 .dram_sdqs5 = 0x00000030, 153 .dram_sdqs6 = 0x00000030, 154 .dram_sdqs7 = 0x00000030, 155 156 /* DQM[0:7]: Differential input, 40 ohm */ 157 .dram_dqm0 = 0x00020030, 158 .dram_dqm1 = 0x00020030, 159 .dram_dqm2 = 0x00020030, 160 .dram_dqm3 = 0x00020030, 161 .dram_dqm4 = 0x00020030, 162 .dram_dqm5 = 0x00020030, 163 .dram_dqm6 = 0x00020030, 164 .dram_dqm7 = 0x00020030, 165 }; 166 167 /* configure MX6SOLO/DUALLITE mmdc GRP io registers */ 168 struct mx6sdl_iomux_grp_regs mx6sdl_grp_ioregs = { 169 /* DDR3 */ 170 .grp_ddr_type = 0x000c0000, 171 /* SDQS[0:7]: Differential input, 40 ohm */ 172 .grp_ddrmode_ctl = 0x00020000, 173 /* disable DDR pullups */ 174 .grp_ddrpke = 0x00000000, 175 /* ADDR[00:16], SDBA[0:1]: 40 ohm */ 176 .grp_addds = 0x00000030, 177 /* CS0/CS1/SDBA2/CKE0/CKE1/SDWE: 40 ohm */ 178 .grp_ctlds = 0x00000030, 179 /* DATA[00:63]: Differential input, 40 ohm */ 180 .grp_ddrmode = 0x00020000, 181 .grp_b0ds = 0x00000030, 182 .grp_b1ds = 0x00000030, 183 .grp_b2ds = 0x00000030, 184 .grp_b3ds = 0x00000030, 185 .grp_b4ds = 0x00000030, 186 .grp_b5ds = 0x00000030, 187 .grp_b6ds = 0x00000030, 188 .grp_b7ds = 0x00000030, 189 }; 190 191 /* MT41K128M16JT-125 */ 192 static struct mx6_ddr3_cfg mt41k128m16jt_125 = { 193 .mem_speed = 1600, 194 .density = 2, 195 .width = 16, 196 .banks = 8, 197 .rowaddr = 14, 198 .coladdr = 10, 199 .pagesz = 2, 200 .trcd = 1375, 201 .trcmin = 4875, 202 .trasmin = 3500, 203 }; 204 205 /* MT41K256M16HA-125 */ 206 static struct mx6_ddr3_cfg mt41k256m16ha_125 = { 207 .mem_speed = 1600, 208 .density = 4, 209 .width = 16, 210 .banks = 8, 211 .rowaddr = 15, 212 .coladdr = 10, 213 .pagesz = 2, 214 .trcd = 1375, 215 .trcmin = 4875, 216 .trasmin = 3500, 217 }; 218 219 /* 220 * calibration - these are the various CPU/DDR3 combinations we support 221 */ 222 223 static struct mx6_mmdc_calibration mx6dq_128x32_mmdc_calib = { 224 /* write leveling calibration determine */ 225 .p0_mpwldectrl0 = 0x00190017, 226 .p0_mpwldectrl1 = 0x00140026, 227 /* Read DQS Gating calibration */ 228 .p0_mpdgctrl0 = 0x43380347, 229 .p0_mpdgctrl1 = 0x433C034D, 230 /* Read Calibration: DQS delay relative to DQ read access */ 231 .p0_mprddlctl = 0x3C313539, 232 /* Write Calibration: DQ/DM delay relative to DQS write access */ 233 .p0_mpwrdlctl = 0x36393C39, 234 }; 235 236 static struct mx6_mmdc_calibration mx6sdl_128x32_mmdc_calib = { 237 /* write leveling calibration determine */ 238 .p0_mpwldectrl0 = 0x003C003C, 239 .p0_mpwldectrl1 = 0x001F002A, 240 /* Read DQS Gating calibration */ 241 .p0_mpdgctrl0 = 0x42410244, 242 .p0_mpdgctrl1 = 0x4234023A, 243 /* Read Calibration: DQS delay relative to DQ read access */ 244 .p0_mprddlctl = 0x484A4C4B, 245 /* Write Calibration: DQ/DM delay relative to DQS write access */ 246 .p0_mpwrdlctl = 0x33342B32, 247 }; 248 249 static struct mx6_mmdc_calibration mx6dq_128x64_mmdc_calib = { 250 /* write leveling calibration determine */ 251 .p0_mpwldectrl0 = 0x00190017, 252 .p0_mpwldectrl1 = 0x00140026, 253 .p1_mpwldectrl0 = 0x0021001C, 254 .p1_mpwldectrl1 = 0x0011001D, 255 /* Read DQS Gating calibration */ 256 .p0_mpdgctrl0 = 0x43380347, 257 .p0_mpdgctrl1 = 0x433C034D, 258 .p1_mpdgctrl0 = 0x032C0324, 259 .p1_mpdgctrl1 = 0x03310232, 260 /* Read Calibration: DQS delay relative to DQ read access */ 261 .p0_mprddlctl = 0x3C313539, 262 .p1_mprddlctl = 0x37343141, 263 /* Write Calibration: DQ/DM delay relative to DQS write access */ 264 .p0_mpwrdlctl = 0x36393C39, 265 .p1_mpwrdlctl = 0x42344438, 266 }; 267 268 static struct mx6_mmdc_calibration mx6sdl_128x64_mmdc_calib = { 269 /* write leveling calibration determine */ 270 .p0_mpwldectrl0 = 0x003C003C, 271 .p0_mpwldectrl1 = 0x001F002A, 272 .p1_mpwldectrl0 = 0x00330038, 273 .p1_mpwldectrl1 = 0x0022003F, 274 /* Read DQS Gating calibration */ 275 .p0_mpdgctrl0 = 0x42410244, 276 .p0_mpdgctrl1 = 0x4234023A, 277 .p1_mpdgctrl0 = 0x022D022D, 278 .p1_mpdgctrl1 = 0x021C0228, 279 /* Read Calibration: DQS delay relative to DQ read access */ 280 .p0_mprddlctl = 0x484A4C4B, 281 .p1_mprddlctl = 0x4B4D4E4B, 282 /* Write Calibration: DQ/DM delay relative to DQS write access */ 283 .p0_mpwrdlctl = 0x33342B32, 284 .p1_mpwrdlctl = 0x3933332B, 285 }; 286 287 static struct mx6_mmdc_calibration mx6dq_256x32_mmdc_calib = { 288 /* write leveling calibration determine */ 289 .p0_mpwldectrl0 = 0x001E001A, 290 .p0_mpwldectrl1 = 0x0026001F, 291 /* Read DQS Gating calibration */ 292 .p0_mpdgctrl0 = 0x43370349, 293 .p0_mpdgctrl1 = 0x032D0327, 294 /* Read Calibration: DQS delay relative to DQ read access */ 295 .p0_mprddlctl = 0x3D303639, 296 /* Write Calibration: DQ/DM delay relative to DQS write access */ 297 .p0_mpwrdlctl = 0x32363934, 298 }; 299 300 static struct mx6_mmdc_calibration mx6dq_256x64_mmdc_calib = { 301 /* write leveling calibration determine */ 302 .p0_mpwldectrl0 = 0X00220021, 303 .p0_mpwldectrl1 = 0X00200030, 304 .p1_mpwldectrl0 = 0X002D0027, 305 .p1_mpwldectrl1 = 0X00150026, 306 /* Read DQS Gating calibration */ 307 .p0_mpdgctrl0 = 0x43330342, 308 .p0_mpdgctrl1 = 0x0339034A, 309 .p1_mpdgctrl0 = 0x032F0325, 310 .p1_mpdgctrl1 = 0x032F022E, 311 /* Read Calibration: DQS delay relative to DQ read access */ 312 .p0_mprddlctl = 0X3A2E3437, 313 .p1_mprddlctl = 0X35312F3F, 314 /* Write Calibration: DQ/DM delay relative to DQS write access */ 315 .p0_mpwrdlctl = 0X33363B37, 316 .p1_mpwrdlctl = 0X40304239, 317 }; 318 319 static void spl_dram_init(int width, int size_mb, int board_model) 320 { 321 struct mx6_ddr3_cfg *mem = NULL; 322 struct mx6_mmdc_calibration *calib = NULL; 323 struct mx6_ddr_sysinfo sysinfo = { 324 /* width of data bus:0=16,1=32,2=64 */ 325 .dsize = width/32, 326 /* config for full 4GB range so that get_mem_size() works */ 327 .cs_density = 32, /* 32Gb per CS */ 328 /* single chip select */ 329 .ncs = 1, 330 .cs1_mirror = 0, 331 .rtt_wr = 1 /*DDR3_RTT_60_OHM*/, /* RTT_Wr = RZQ/4 */ 332 #ifdef RTT_NOM_120OHM 333 .rtt_nom = 2 /*DDR3_RTT_120_OHM*/, /* RTT_Nom = RZQ/2 */ 334 #else 335 .rtt_nom = 1 /*DDR3_RTT_60_OHM*/, /* RTT_Nom = RZQ/4 */ 336 #endif 337 .walat = 1, /* Write additional latency */ 338 .ralat = 5, /* Read additional latency */ 339 .mif3_mode = 3, /* Command prediction working mode */ 340 .bi_on = 1, /* Bank interleaving enabled */ 341 .sde_to_rst = 0x10, /* 14 cycles, 200us (JEDEC default) */ 342 .rst_to_cke = 0x23, /* 33 cycles, 500us (JEDEC default) */ 343 }; 344 345 /* 346 * MMDC Calibration requires the following data: 347 * mx6_mmdc_calibration - board-specific calibration (routing delays) 348 * these calibration values depend on board routing, SoC, and DDR 349 * mx6_ddr_sysinfo - board-specific memory architecture (width/cs/etc) 350 * mx6_ddr_cfg - chip specific timing/layout details 351 */ 352 if (width == 32 && size_mb == 512) { 353 mem = &mt41k128m16jt_125; 354 if (is_cpu_type(MXC_CPU_MX6Q)) 355 calib = &mx6dq_128x32_mmdc_calib; 356 else 357 calib = &mx6sdl_128x32_mmdc_calib; 358 debug("2gB density\n"); 359 } else if (width == 64 && size_mb == 1024) { 360 mem = &mt41k128m16jt_125; 361 if (is_cpu_type(MXC_CPU_MX6Q)) 362 calib = &mx6dq_128x64_mmdc_calib; 363 else 364 calib = &mx6sdl_128x64_mmdc_calib; 365 debug("2gB density\n"); 366 } else if (width == 32 && size_mb == 1024) { 367 mem = &mt41k256m16ha_125; 368 if (is_cpu_type(MXC_CPU_MX6Q)) 369 calib = &mx6dq_256x32_mmdc_calib; 370 debug("4gB density\n"); 371 } else if (width == 64 && size_mb == 2048) { 372 mem = &mt41k256m16ha_125; 373 if (is_cpu_type(MXC_CPU_MX6Q)) 374 calib = &mx6dq_256x64_mmdc_calib; 375 debug("4gB density\n"); 376 } 377 378 if (!mem) { 379 puts("Error: Invalid Memory Configuration\n"); 380 hang(); 381 } 382 if (!calib) { 383 puts("Error: Invalid Board Calibration Configuration\n"); 384 hang(); 385 } 386 387 if (is_cpu_type(MXC_CPU_MX6Q)) 388 mx6dq_dram_iocfg(width, &mx6dq_ddr_ioregs, 389 &mx6dq_grp_ioregs); 390 else 391 mx6sdl_dram_iocfg(width, &mx6sdl_ddr_ioregs, 392 &mx6sdl_grp_ioregs); 393 mx6_dram_cfg(&sysinfo, calib, mem); 394 } 395 396 static void ccgr_init(void) 397 { 398 struct mxc_ccm_reg *ccm = (struct mxc_ccm_reg *)CCM_BASE_ADDR; 399 400 writel(0x00C03F3F, &ccm->CCGR0); 401 writel(0x0030FC03, &ccm->CCGR1); 402 writel(0x0FFFC000, &ccm->CCGR2); 403 writel(0x3FF00000, &ccm->CCGR3); 404 writel(0xFFFFF300, &ccm->CCGR4); /* enable NAND/GPMI/BCH clks */ 405 writel(0x0F0000C3, &ccm->CCGR5); 406 writel(0x000003FF, &ccm->CCGR6); 407 } 408 409 static void gpr_init(void) 410 { 411 struct iomuxc *iomux = (struct iomuxc *)IOMUXC_BASE_ADDR; 412 413 /* enable AXI cache for VDOA/VPU/IPU */ 414 writel(0xF00000CF, &iomux->gpr[4]); 415 /* set IPU AXI-id0 Qos=0xf(bypass) AXI-id1 Qos=0x7 */ 416 writel(0x007F007F, &iomux->gpr[6]); 417 writel(0x007F007F, &iomux->gpr[7]); 418 } 419 420 /* 421 * called from C runtime startup code (arch/arm/lib/crt0.S:_main) 422 * - we have a stack and a place to store GD, both in SRAM 423 * - no variable global data is available 424 */ 425 void board_init_f(ulong dummy) 426 { 427 struct ventana_board_info ventana_info; 428 int board_model; 429 430 /* setup AIPS and disable watchdog */ 431 arch_cpu_init(); 432 433 ccgr_init(); 434 gpr_init(); 435 436 /* iomux and setup of i2c */ 437 board_early_init_f(); 438 i2c_setup_iomux(); 439 440 /* setup GP timer */ 441 timer_init(); 442 443 /* UART clocks enabled and gd valid - init serial console */ 444 preloader_console_init(); 445 446 /* read/validate EEPROM info to determine board model and SDRAM cfg */ 447 board_model = read_eeprom(I2C_GSC, &ventana_info); 448 449 /* provide some some default: 32bit 128MB */ 450 if (GW_UNKNOWN == board_model) { 451 ventana_info.sdram_width = 2; 452 ventana_info.sdram_size = 3; 453 } 454 455 /* configure MMDC for SDRAM width/size and per-model calibration */ 456 spl_dram_init(8 << ventana_info.sdram_width, 457 16 << ventana_info.sdram_size, 458 board_model); 459 460 /* Clear the BSS. */ 461 memset(__bss_start, 0, __bss_end - __bss_start); 462 463 /* load/boot image from boot device */ 464 board_init_r(NULL, 0); 465 } 466 467 void reset_cpu(ulong addr) 468 { 469 } 470