1 /* 2 * Copyright (C) 2014 Gateworks Corporation 3 * Author: Tim Harvey <tharvey@gateworks.com> 4 * 5 * SPDX-License-Identifier: GPL-2.0+ 6 */ 7 8 #include <common.h> 9 #include <asm/io.h> 10 #include <asm/arch/crm_regs.h> 11 #include <asm/arch/mx6-ddr.h> 12 #include <asm/arch/mx6-pins.h> 13 #include <asm/arch/sys_proto.h> 14 #include <asm/imx-common/boot_mode.h> 15 #include <asm/imx-common/iomux-v3.h> 16 #include <asm/imx-common/mxc_i2c.h> 17 #include <environment.h> 18 #include <spl.h> 19 20 #include "gsc.h" 21 #include "common.h" 22 23 DECLARE_GLOBAL_DATA_PTR; 24 25 #define RTT_NOM_120OHM /* use 120ohm Rtt_nom vs 60ohm (lower power) */ 26 #define GSC_EEPROM_DDR_SIZE 0x2B /* enum (512,1024,2048) MB */ 27 #define GSC_EEPROM_DDR_WIDTH 0x2D /* enum (32,64) bit */ 28 29 /* configure MX6Q/DUAL mmdc DDR io registers */ 30 struct mx6dq_iomux_ddr_regs mx6dq_ddr_ioregs = { 31 /* SDCLK[0:1], CAS, RAS, Reset: Differential input, 40ohm */ 32 .dram_sdclk_0 = 0x00020030, 33 .dram_sdclk_1 = 0x00020030, 34 .dram_cas = 0x00020030, 35 .dram_ras = 0x00020030, 36 .dram_reset = 0x00020030, 37 /* SDCKE[0:1]: 100k pull-up */ 38 .dram_sdcke0 = 0x00003000, 39 .dram_sdcke1 = 0x00003000, 40 /* SDBA2: pull-up disabled */ 41 .dram_sdba2 = 0x00000000, 42 /* SDODT[0:1]: 100k pull-up, 40 ohm */ 43 .dram_sdodt0 = 0x00003030, 44 .dram_sdodt1 = 0x00003030, 45 /* SDQS[0:7]: Differential input, 40 ohm */ 46 .dram_sdqs0 = 0x00000030, 47 .dram_sdqs1 = 0x00000030, 48 .dram_sdqs2 = 0x00000030, 49 .dram_sdqs3 = 0x00000030, 50 .dram_sdqs4 = 0x00000030, 51 .dram_sdqs5 = 0x00000030, 52 .dram_sdqs6 = 0x00000030, 53 .dram_sdqs7 = 0x00000030, 54 55 /* DQM[0:7]: Differential input, 40 ohm */ 56 .dram_dqm0 = 0x00020030, 57 .dram_dqm1 = 0x00020030, 58 .dram_dqm2 = 0x00020030, 59 .dram_dqm3 = 0x00020030, 60 .dram_dqm4 = 0x00020030, 61 .dram_dqm5 = 0x00020030, 62 .dram_dqm6 = 0x00020030, 63 .dram_dqm7 = 0x00020030, 64 }; 65 66 /* configure MX6Q/DUAL mmdc GRP io registers */ 67 struct mx6dq_iomux_grp_regs mx6dq_grp_ioregs = { 68 /* DDR3 */ 69 .grp_ddr_type = 0x000c0000, 70 .grp_ddrmode_ctl = 0x00020000, 71 /* disable DDR pullups */ 72 .grp_ddrpke = 0x00000000, 73 /* ADDR[00:16], SDBA[0:1]: 40 ohm */ 74 .grp_addds = 0x00000030, 75 /* CS0/CS1/SDBA2/CKE0/CKE1/SDWE: 40 ohm */ 76 .grp_ctlds = 0x00000030, 77 /* DATA[00:63]: Differential input, 40 ohm */ 78 .grp_ddrmode = 0x00020000, 79 .grp_b0ds = 0x00000030, 80 .grp_b1ds = 0x00000030, 81 .grp_b2ds = 0x00000030, 82 .grp_b3ds = 0x00000030, 83 .grp_b4ds = 0x00000030, 84 .grp_b5ds = 0x00000030, 85 .grp_b6ds = 0x00000030, 86 .grp_b7ds = 0x00000030, 87 }; 88 89 /* configure MX6SOLO/DUALLITE mmdc DDR io registers */ 90 struct mx6sdl_iomux_ddr_regs mx6sdl_ddr_ioregs = { 91 /* SDCLK[0:1], CAS, RAS, Reset: Differential input, 40ohm */ 92 .dram_sdclk_0 = 0x00020030, 93 .dram_sdclk_1 = 0x00020030, 94 .dram_cas = 0x00020030, 95 .dram_ras = 0x00020030, 96 .dram_reset = 0x00020030, 97 /* SDCKE[0:1]: 100k pull-up */ 98 .dram_sdcke0 = 0x00003000, 99 .dram_sdcke1 = 0x00003000, 100 /* SDBA2: pull-up disabled */ 101 .dram_sdba2 = 0x00000000, 102 /* SDODT[0:1]: 100k pull-up, 40 ohm */ 103 .dram_sdodt0 = 0x00003030, 104 .dram_sdodt1 = 0x00003030, 105 /* SDQS[0:7]: Differential input, 40 ohm */ 106 .dram_sdqs0 = 0x00000030, 107 .dram_sdqs1 = 0x00000030, 108 .dram_sdqs2 = 0x00000030, 109 .dram_sdqs3 = 0x00000030, 110 .dram_sdqs4 = 0x00000030, 111 .dram_sdqs5 = 0x00000030, 112 .dram_sdqs6 = 0x00000030, 113 .dram_sdqs7 = 0x00000030, 114 115 /* DQM[0:7]: Differential input, 40 ohm */ 116 .dram_dqm0 = 0x00020030, 117 .dram_dqm1 = 0x00020030, 118 .dram_dqm2 = 0x00020030, 119 .dram_dqm3 = 0x00020030, 120 .dram_dqm4 = 0x00020030, 121 .dram_dqm5 = 0x00020030, 122 .dram_dqm6 = 0x00020030, 123 .dram_dqm7 = 0x00020030, 124 }; 125 126 /* configure MX6SOLO/DUALLITE mmdc GRP io registers */ 127 struct mx6sdl_iomux_grp_regs mx6sdl_grp_ioregs = { 128 /* DDR3 */ 129 .grp_ddr_type = 0x000c0000, 130 /* SDQS[0:7]: Differential input, 40 ohm */ 131 .grp_ddrmode_ctl = 0x00020000, 132 /* disable DDR pullups */ 133 .grp_ddrpke = 0x00000000, 134 /* ADDR[00:16], SDBA[0:1]: 40 ohm */ 135 .grp_addds = 0x00000030, 136 /* CS0/CS1/SDBA2/CKE0/CKE1/SDWE: 40 ohm */ 137 .grp_ctlds = 0x00000030, 138 /* DATA[00:63]: Differential input, 40 ohm */ 139 .grp_ddrmode = 0x00020000, 140 .grp_b0ds = 0x00000030, 141 .grp_b1ds = 0x00000030, 142 .grp_b2ds = 0x00000030, 143 .grp_b3ds = 0x00000030, 144 .grp_b4ds = 0x00000030, 145 .grp_b5ds = 0x00000030, 146 .grp_b6ds = 0x00000030, 147 .grp_b7ds = 0x00000030, 148 }; 149 150 /* MT41K64M16JT-125 (1Gb density) */ 151 static struct mx6_ddr3_cfg mt41k64m16jt_125 = { 152 .mem_speed = 1600, 153 .density = 1, 154 .width = 16, 155 .banks = 8, 156 .rowaddr = 13, 157 .coladdr = 10, 158 .pagesz = 2, 159 .trcd = 1375, 160 .trcmin = 4875, 161 .trasmin = 3500, 162 }; 163 164 /* MT41K128M16JT-125 (2Gb density) */ 165 static struct mx6_ddr3_cfg mt41k128m16jt_125 = { 166 .mem_speed = 1600, 167 .density = 2, 168 .width = 16, 169 .banks = 8, 170 .rowaddr = 14, 171 .coladdr = 10, 172 .pagesz = 2, 173 .trcd = 1375, 174 .trcmin = 4875, 175 .trasmin = 3500, 176 }; 177 178 /* MT41K256M16HA-125 (4Gb density) */ 179 static struct mx6_ddr3_cfg mt41k256m16ha_125 = { 180 .mem_speed = 1600, 181 .density = 4, 182 .width = 16, 183 .banks = 8, 184 .rowaddr = 15, 185 .coladdr = 10, 186 .pagesz = 2, 187 .trcd = 1375, 188 .trcmin = 4875, 189 .trasmin = 3500, 190 }; 191 192 /* 193 * calibration - these are the various CPU/DDR3 combinations we support 194 */ 195 static struct mx6_mmdc_calibration mx6sdl_64x16_mmdc_calib = { 196 /* write leveling calibration determine */ 197 .p0_mpwldectrl0 = 0x004C004E, 198 .p0_mpwldectrl1 = 0x00440044, 199 /* Read DQS Gating calibration */ 200 .p0_mpdgctrl0 = 0x42440247, 201 .p0_mpdgctrl1 = 0x02310232, 202 /* Read Calibration: DQS delay relative to DQ read access */ 203 .p0_mprddlctl = 0x45424746, 204 /* Write Calibration: DQ/DM delay relative to DQS write access */ 205 .p0_mpwrdlctl = 0x33382C31, 206 }; 207 208 static struct mx6_mmdc_calibration mx6dq_256x16_mmdc_calib = { 209 /* write leveling calibration determine */ 210 .p0_mpwldectrl0 = 0x001B0016, 211 .p0_mpwldectrl1 = 0x000C000E, 212 /* Read DQS Gating calibration */ 213 .p0_mpdgctrl0 = 0x4324033A, 214 .p0_mpdgctrl1 = 0x00000000, 215 /* Read Calibration: DQS delay relative to DQ read access */ 216 .p0_mprddlctl = 0x40403438, 217 /* Write Calibration: DQ/DM delay relative to DQS write access */ 218 .p0_mpwrdlctl = 0x40403D36, 219 }; 220 221 static struct mx6_mmdc_calibration mx6sdl_256x16_mmdc_calib = { 222 /* write leveling calibration determine */ 223 .p0_mpwldectrl0 = 0x00420043, 224 .p0_mpwldectrl1 = 0x0016001A, 225 /* Read DQS Gating calibration */ 226 .p0_mpdgctrl0 = 0x4238023B, 227 .p0_mpdgctrl1 = 0x00000000, 228 /* Read Calibration: DQS delay relative to DQ read access */ 229 .p0_mprddlctl = 0x40404849, 230 /* Write Calibration: DQ/DM delay relative to DQS write access */ 231 .p0_mpwrdlctl = 0x40402E2F, 232 }; 233 234 static struct mx6_mmdc_calibration mx6dq_128x32_mmdc_calib = { 235 /* write leveling calibration determine */ 236 .p0_mpwldectrl0 = 0x00190017, 237 .p0_mpwldectrl1 = 0x00140026, 238 /* Read DQS Gating calibration */ 239 .p0_mpdgctrl0 = 0x43380347, 240 .p0_mpdgctrl1 = 0x433C034D, 241 /* Read Calibration: DQS delay relative to DQ read access */ 242 .p0_mprddlctl = 0x3C313539, 243 /* Write Calibration: DQ/DM delay relative to DQS write access */ 244 .p0_mpwrdlctl = 0x36393C39, 245 }; 246 247 static struct mx6_mmdc_calibration mx6sdl_128x32_mmdc_calib = { 248 /* write leveling calibration determine */ 249 .p0_mpwldectrl0 = 0x003C003C, 250 .p0_mpwldectrl1 = 0x001F002A, 251 /* Read DQS Gating calibration */ 252 .p0_mpdgctrl0 = 0x42410244, 253 .p0_mpdgctrl1 = 0x4234023A, 254 /* Read Calibration: DQS delay relative to DQ read access */ 255 .p0_mprddlctl = 0x484A4C4B, 256 /* Write Calibration: DQ/DM delay relative to DQS write access */ 257 .p0_mpwrdlctl = 0x33342B32, 258 }; 259 260 static struct mx6_mmdc_calibration mx6dq_128x64_mmdc_calib = { 261 /* write leveling calibration determine */ 262 .p0_mpwldectrl0 = 0x00190017, 263 .p0_mpwldectrl1 = 0x00140026, 264 .p1_mpwldectrl0 = 0x0021001C, 265 .p1_mpwldectrl1 = 0x0011001D, 266 /* Read DQS Gating calibration */ 267 .p0_mpdgctrl0 = 0x43380347, 268 .p0_mpdgctrl1 = 0x433C034D, 269 .p1_mpdgctrl0 = 0x032C0324, 270 .p1_mpdgctrl1 = 0x03310232, 271 /* Read Calibration: DQS delay relative to DQ read access */ 272 .p0_mprddlctl = 0x3C313539, 273 .p1_mprddlctl = 0x37343141, 274 /* Write Calibration: DQ/DM delay relative to DQS write access */ 275 .p0_mpwrdlctl = 0x36393C39, 276 .p1_mpwrdlctl = 0x42344438, 277 }; 278 279 static struct mx6_mmdc_calibration mx6sdl_128x64_mmdc_calib = { 280 /* write leveling calibration determine */ 281 .p0_mpwldectrl0 = 0x003C003C, 282 .p0_mpwldectrl1 = 0x001F002A, 283 .p1_mpwldectrl0 = 0x00330038, 284 .p1_mpwldectrl1 = 0x0022003F, 285 /* Read DQS Gating calibration */ 286 .p0_mpdgctrl0 = 0x42410244, 287 .p0_mpdgctrl1 = 0x4234023A, 288 .p1_mpdgctrl0 = 0x022D022D, 289 .p1_mpdgctrl1 = 0x021C0228, 290 /* Read Calibration: DQS delay relative to DQ read access */ 291 .p0_mprddlctl = 0x484A4C4B, 292 .p1_mprddlctl = 0x4B4D4E4B, 293 /* Write Calibration: DQ/DM delay relative to DQS write access */ 294 .p0_mpwrdlctl = 0x33342B32, 295 .p1_mpwrdlctl = 0x3933332B, 296 }; 297 298 static struct mx6_mmdc_calibration mx6dq_256x32_mmdc_calib = { 299 /* write leveling calibration determine */ 300 .p0_mpwldectrl0 = 0x001E001A, 301 .p0_mpwldectrl1 = 0x0026001F, 302 /* Read DQS Gating calibration */ 303 .p0_mpdgctrl0 = 0x43370349, 304 .p0_mpdgctrl1 = 0x032D0327, 305 /* Read Calibration: DQS delay relative to DQ read access */ 306 .p0_mprddlctl = 0x3D303639, 307 /* Write Calibration: DQ/DM delay relative to DQS write access */ 308 .p0_mpwrdlctl = 0x32363934, 309 }; 310 311 static struct mx6_mmdc_calibration mx6sdl_256x32_mmdc_calib = { 312 /* write leveling calibration determine */ 313 .p0_mpwldectrl0 = 0X00480047, 314 .p0_mpwldectrl1 = 0X003D003F, 315 /* Read DQS Gating calibration */ 316 .p0_mpdgctrl0 = 0X423E0241, 317 .p0_mpdgctrl1 = 0X022B022C, 318 /* Read Calibration: DQS delay relative to DQ read access */ 319 .p0_mprddlctl = 0X49454A4A, 320 /* Write Calibration: DQ/DM delay relative to DQS write access */ 321 .p0_mpwrdlctl = 0X2E372C32, 322 }; 323 324 static struct mx6_mmdc_calibration mx6dq_256x64_mmdc_calib = { 325 /* write leveling calibration determine */ 326 .p0_mpwldectrl0 = 0X00220021, 327 .p0_mpwldectrl1 = 0X00200030, 328 .p1_mpwldectrl0 = 0X002D0027, 329 .p1_mpwldectrl1 = 0X00150026, 330 /* Read DQS Gating calibration */ 331 .p0_mpdgctrl0 = 0x43330342, 332 .p0_mpdgctrl1 = 0x0339034A, 333 .p1_mpdgctrl0 = 0x032F0325, 334 .p1_mpdgctrl1 = 0x032F022E, 335 /* Read Calibration: DQS delay relative to DQ read access */ 336 .p0_mprddlctl = 0X3A2E3437, 337 .p1_mprddlctl = 0X35312F3F, 338 /* Write Calibration: DQ/DM delay relative to DQS write access */ 339 .p0_mpwrdlctl = 0X33363B37, 340 .p1_mpwrdlctl = 0X40304239, 341 }; 342 343 static void spl_dram_init(int width, int size_mb, int board_model) 344 { 345 struct mx6_ddr3_cfg *mem = NULL; 346 struct mx6_mmdc_calibration *calib = NULL; 347 struct mx6_ddr_sysinfo sysinfo = { 348 /* width of data bus:0=16,1=32,2=64 */ 349 .dsize = width/32, 350 /* config for full 4GB range so that get_mem_size() works */ 351 .cs_density = 32, /* 32Gb per CS */ 352 /* single chip select */ 353 .ncs = 1, 354 .cs1_mirror = 0, 355 .rtt_wr = 1 /*DDR3_RTT_60_OHM*/, /* RTT_Wr = RZQ/4 */ 356 #ifdef RTT_NOM_120OHM 357 .rtt_nom = 2 /*DDR3_RTT_120_OHM*/, /* RTT_Nom = RZQ/2 */ 358 #else 359 .rtt_nom = 1 /*DDR3_RTT_60_OHM*/, /* RTT_Nom = RZQ/4 */ 360 #endif 361 .walat = 1, /* Write additional latency */ 362 .ralat = 5, /* Read additional latency */ 363 .mif3_mode = 3, /* Command prediction working mode */ 364 .bi_on = 1, /* Bank interleaving enabled */ 365 .sde_to_rst = 0x10, /* 14 cycles, 200us (JEDEC default) */ 366 .rst_to_cke = 0x23, /* 33 cycles, 500us (JEDEC default) */ 367 .pd_fast_exit = 1, /* enable precharge power-down fast exit */ 368 }; 369 370 /* 371 * MMDC Calibration requires the following data: 372 * mx6_mmdc_calibration - board-specific calibration (routing delays) 373 * these calibration values depend on board routing, SoC, and DDR 374 * mx6_ddr_sysinfo - board-specific memory architecture (width/cs/etc) 375 * mx6_ddr_cfg - chip specific timing/layout details 376 */ 377 if (width == 16 && size_mb == 128) { 378 mem = &mt41k64m16jt_125; 379 if (is_cpu_type(MXC_CPU_MX6Q)) 380 ; 381 else 382 calib = &mx6sdl_64x16_mmdc_calib; 383 debug("1gB density\n"); 384 } else if (width == 16 && size_mb == 256) { 385 /* 1x 2Gb density chip - same calib as 2x 2Gb */ 386 mem = &mt41k128m16jt_125; 387 if (is_cpu_type(MXC_CPU_MX6Q)) 388 calib = &mx6dq_128x32_mmdc_calib; 389 else 390 calib = &mx6sdl_128x32_mmdc_calib; 391 debug("2gB density\n"); 392 } else if (width == 16 && size_mb == 512) { 393 mem = &mt41k256m16ha_125; 394 if (is_cpu_type(MXC_CPU_MX6Q)) 395 calib = &mx6dq_256x16_mmdc_calib; 396 else 397 calib = &mx6sdl_256x16_mmdc_calib; 398 debug("4gB density\n"); 399 } else if (width == 32 && size_mb == 256) { 400 /* Same calib as width==16, size==128 */ 401 mem = &mt41k64m16jt_125; 402 if (is_cpu_type(MXC_CPU_MX6Q)) 403 ; 404 else 405 calib = &mx6sdl_64x16_mmdc_calib; 406 debug("1gB density\n"); 407 } else if (width == 32 && size_mb == 512) { 408 mem = &mt41k128m16jt_125; 409 if (is_cpu_type(MXC_CPU_MX6Q)) 410 calib = &mx6dq_128x32_mmdc_calib; 411 else 412 calib = &mx6sdl_128x32_mmdc_calib; 413 debug("2gB density\n"); 414 } else if (width == 32 && size_mb == 1024) { 415 mem = &mt41k256m16ha_125; 416 if (is_cpu_type(MXC_CPU_MX6Q)) 417 calib = &mx6dq_256x32_mmdc_calib; 418 else 419 calib = &mx6sdl_256x32_mmdc_calib; 420 debug("4gB density\n"); 421 } else if (width == 64 && size_mb == 512) { 422 mem = &mt41k64m16jt_125; 423 debug("1gB density\n"); 424 } else if (width == 64 && size_mb == 1024) { 425 mem = &mt41k128m16jt_125; 426 if (is_cpu_type(MXC_CPU_MX6Q)) 427 calib = &mx6dq_128x64_mmdc_calib; 428 else 429 calib = &mx6sdl_128x64_mmdc_calib; 430 debug("2gB density\n"); 431 } else if (width == 64 && size_mb == 2048) { 432 mem = &mt41k256m16ha_125; 433 if (is_cpu_type(MXC_CPU_MX6Q)) 434 calib = &mx6dq_256x64_mmdc_calib; 435 debug("4gB density\n"); 436 } 437 438 if (!(mem && calib)) { 439 puts("Error: Invalid Calibration/Board Configuration\n"); 440 printf("MEM : %s\n", mem ? "OKAY" : "NULL"); 441 printf("CALIB : %s\n", calib ? "OKAY" : "NULL"); 442 printf("CPUTYPE: %s\n", 443 is_cpu_type(MXC_CPU_MX6Q) ? "IMX6Q" : "IMX6DL"); 444 printf("SIZE_MB: %d\n", size_mb); 445 printf("WIDTH : %d\n", width); 446 hang(); 447 } 448 449 if (is_cpu_type(MXC_CPU_MX6Q)) 450 mx6dq_dram_iocfg(width, &mx6dq_ddr_ioregs, 451 &mx6dq_grp_ioregs); 452 else 453 mx6sdl_dram_iocfg(width, &mx6sdl_ddr_ioregs, 454 &mx6sdl_grp_ioregs); 455 mx6_dram_cfg(&sysinfo, calib, mem); 456 } 457 458 static void ccgr_init(void) 459 { 460 struct mxc_ccm_reg *ccm = (struct mxc_ccm_reg *)CCM_BASE_ADDR; 461 462 writel(0x00C03F3F, &ccm->CCGR0); 463 writel(0x0030FC03, &ccm->CCGR1); 464 writel(0x0FFFC000, &ccm->CCGR2); 465 writel(0x3FF00000, &ccm->CCGR3); 466 writel(0xFFFFF300, &ccm->CCGR4); /* enable NAND/GPMI/BCH clks */ 467 writel(0x0F0000C3, &ccm->CCGR5); 468 writel(0x000003FF, &ccm->CCGR6); 469 } 470 471 static void gpr_init(void) 472 { 473 struct iomuxc *iomux = (struct iomuxc *)IOMUXC_BASE_ADDR; 474 475 /* enable AXI cache for VDOA/VPU/IPU */ 476 writel(0xF00000CF, &iomux->gpr[4]); 477 /* set IPU AXI-id0 Qos=0xf(bypass) AXI-id1 Qos=0x7 */ 478 writel(0x007F007F, &iomux->gpr[6]); 479 writel(0x007F007F, &iomux->gpr[7]); 480 } 481 482 /* 483 * called from C runtime startup code (arch/arm/lib/crt0.S:_main) 484 * - we have a stack and a place to store GD, both in SRAM 485 * - no variable global data is available 486 */ 487 void board_init_f(ulong dummy) 488 { 489 struct ventana_board_info ventana_info; 490 int board_model; 491 492 /* setup clock gating */ 493 ccgr_init(); 494 495 /* setup AIPS and disable watchdog */ 496 arch_cpu_init(); 497 498 /* setup AXI */ 499 gpr_init(); 500 501 /* iomux and setup of i2c */ 502 setup_iomux_uart(); 503 setup_ventana_i2c(); 504 505 /* setup GP timer */ 506 timer_init(); 507 508 /* UART clocks enabled and gd valid - init serial console */ 509 preloader_console_init(); 510 511 /* read/validate EEPROM info to determine board model and SDRAM cfg */ 512 board_model = read_eeprom(CONFIG_I2C_GSC, &ventana_info); 513 514 /* configure model-specific gpio */ 515 setup_iomux_gpio(board_model, &ventana_info); 516 517 /* provide some some default: 32bit 128MB */ 518 if (GW_UNKNOWN == board_model) 519 hang(); 520 521 /* configure MMDC for SDRAM width/size and per-model calibration */ 522 spl_dram_init(8 << ventana_info.sdram_width, 523 16 << ventana_info.sdram_size, 524 board_model); 525 526 /* Clear the BSS. */ 527 memset(__bss_start, 0, __bss_end - __bss_start); 528 529 /* disable boot watchdog */ 530 gsc_boot_wd_disable(); 531 } 532 533 /* called from board_init_r after gd setup if CONFIG_SPL_BOARD_INIT defined */ 534 /* its our chance to print info about boot device */ 535 void spl_board_init(void) 536 { 537 /* determine boot device from SRC_SBMR1 (BOOT_CFG[4:1]) or SRC_GPR9 */ 538 u32 boot_device = spl_boot_device(); 539 540 switch (boot_device) { 541 case BOOT_DEVICE_MMC1: 542 puts("Booting from MMC\n"); 543 break; 544 case BOOT_DEVICE_NAND: 545 puts("Booting from NAND\n"); 546 break; 547 case BOOT_DEVICE_SATA: 548 puts("Booting from SATA\n"); 549 break; 550 default: 551 puts("Unknown boot device\n"); 552 } 553 554 /* PMIC init */ 555 setup_pmic(); 556 } 557 558 #ifdef CONFIG_SPL_OS_BOOT 559 /* return 1 if we wish to boot to uboot vs os (falcon mode) */ 560 int spl_start_uboot(void) 561 { 562 int ret = 1; 563 564 debug("%s\n", __func__); 565 #ifdef CONFIG_SPL_ENV_SUPPORT 566 env_init(); 567 env_relocate_spec(); 568 debug("boot_os=%s\n", getenv("boot_os")); 569 if (getenv_yesno("boot_os") == 1) 570 ret = 0; 571 #endif 572 debug("%s booting %s\n", __func__, ret ? "uboot" : "linux"); 573 return ret; 574 } 575 #endif 576 577 void reset_cpu(ulong addr) 578 { 579 } 580