1 /* 2 * Copyright (C) 2014 Gateworks Corporation 3 * Author: Tim Harvey <tharvey@gateworks.com> 4 * 5 * SPDX-License-Identifier: GPL-2.0+ 6 */ 7 8 #include <common.h> 9 #include <asm/io.h> 10 #include <asm/arch/crm_regs.h> 11 #include <asm/arch/mx6-ddr.h> 12 #include <asm/arch/mx6-pins.h> 13 #include <asm/arch/sys_proto.h> 14 #include <asm/imx-common/boot_mode.h> 15 #include <asm/imx-common/iomux-v3.h> 16 #include <asm/imx-common/mxc_i2c.h> 17 #include <environment.h> 18 #include <i2c.h> 19 #include <spl.h> 20 21 #include "gsc.h" 22 #include "common.h" 23 24 DECLARE_GLOBAL_DATA_PTR; 25 26 #define RTT_NOM_120OHM /* use 120ohm Rtt_nom vs 60ohm (lower power) */ 27 #define GSC_EEPROM_DDR_SIZE 0x2B /* enum (512,1024,2048) MB */ 28 #define GSC_EEPROM_DDR_WIDTH 0x2D /* enum (32,64) bit */ 29 30 /* configure MX6Q/DUAL mmdc DDR io registers */ 31 struct mx6dq_iomux_ddr_regs mx6dq_ddr_ioregs = { 32 /* SDCLK[0:1], CAS, RAS, Reset: Differential input, 40ohm */ 33 .dram_sdclk_0 = 0x00020030, 34 .dram_sdclk_1 = 0x00020030, 35 .dram_cas = 0x00020030, 36 .dram_ras = 0x00020030, 37 .dram_reset = 0x00020030, 38 /* SDCKE[0:1]: 100k pull-up */ 39 .dram_sdcke0 = 0x00003000, 40 .dram_sdcke1 = 0x00003000, 41 /* SDBA2: pull-up disabled */ 42 .dram_sdba2 = 0x00000000, 43 /* SDODT[0:1]: 100k pull-up, 40 ohm */ 44 .dram_sdodt0 = 0x00003030, 45 .dram_sdodt1 = 0x00003030, 46 /* SDQS[0:7]: Differential input, 40 ohm */ 47 .dram_sdqs0 = 0x00000030, 48 .dram_sdqs1 = 0x00000030, 49 .dram_sdqs2 = 0x00000030, 50 .dram_sdqs3 = 0x00000030, 51 .dram_sdqs4 = 0x00000030, 52 .dram_sdqs5 = 0x00000030, 53 .dram_sdqs6 = 0x00000030, 54 .dram_sdqs7 = 0x00000030, 55 56 /* DQM[0:7]: Differential input, 40 ohm */ 57 .dram_dqm0 = 0x00020030, 58 .dram_dqm1 = 0x00020030, 59 .dram_dqm2 = 0x00020030, 60 .dram_dqm3 = 0x00020030, 61 .dram_dqm4 = 0x00020030, 62 .dram_dqm5 = 0x00020030, 63 .dram_dqm6 = 0x00020030, 64 .dram_dqm7 = 0x00020030, 65 }; 66 67 /* configure MX6Q/DUAL mmdc GRP io registers */ 68 struct mx6dq_iomux_grp_regs mx6dq_grp_ioregs = { 69 /* DDR3 */ 70 .grp_ddr_type = 0x000c0000, 71 .grp_ddrmode_ctl = 0x00020000, 72 /* disable DDR pullups */ 73 .grp_ddrpke = 0x00000000, 74 /* ADDR[00:16], SDBA[0:1]: 40 ohm */ 75 .grp_addds = 0x00000030, 76 /* CS0/CS1/SDBA2/CKE0/CKE1/SDWE: 40 ohm */ 77 .grp_ctlds = 0x00000030, 78 /* DATA[00:63]: Differential input, 40 ohm */ 79 .grp_ddrmode = 0x00020000, 80 .grp_b0ds = 0x00000030, 81 .grp_b1ds = 0x00000030, 82 .grp_b2ds = 0x00000030, 83 .grp_b3ds = 0x00000030, 84 .grp_b4ds = 0x00000030, 85 .grp_b5ds = 0x00000030, 86 .grp_b6ds = 0x00000030, 87 .grp_b7ds = 0x00000030, 88 }; 89 90 /* configure MX6SOLO/DUALLITE mmdc DDR io registers */ 91 struct mx6sdl_iomux_ddr_regs mx6sdl_ddr_ioregs = { 92 /* SDCLK[0:1], CAS, RAS, Reset: Differential input, 40ohm */ 93 .dram_sdclk_0 = 0x00020030, 94 .dram_sdclk_1 = 0x00020030, 95 .dram_cas = 0x00020030, 96 .dram_ras = 0x00020030, 97 .dram_reset = 0x00020030, 98 /* SDCKE[0:1]: 100k pull-up */ 99 .dram_sdcke0 = 0x00003000, 100 .dram_sdcke1 = 0x00003000, 101 /* SDBA2: pull-up disabled */ 102 .dram_sdba2 = 0x00000000, 103 /* SDODT[0:1]: 100k pull-up, 40 ohm */ 104 .dram_sdodt0 = 0x00003030, 105 .dram_sdodt1 = 0x00003030, 106 /* SDQS[0:7]: Differential input, 40 ohm */ 107 .dram_sdqs0 = 0x00000030, 108 .dram_sdqs1 = 0x00000030, 109 .dram_sdqs2 = 0x00000030, 110 .dram_sdqs3 = 0x00000030, 111 .dram_sdqs4 = 0x00000030, 112 .dram_sdqs5 = 0x00000030, 113 .dram_sdqs6 = 0x00000030, 114 .dram_sdqs7 = 0x00000030, 115 116 /* DQM[0:7]: Differential input, 40 ohm */ 117 .dram_dqm0 = 0x00020030, 118 .dram_dqm1 = 0x00020030, 119 .dram_dqm2 = 0x00020030, 120 .dram_dqm3 = 0x00020030, 121 .dram_dqm4 = 0x00020030, 122 .dram_dqm5 = 0x00020030, 123 .dram_dqm6 = 0x00020030, 124 .dram_dqm7 = 0x00020030, 125 }; 126 127 /* configure MX6SOLO/DUALLITE mmdc GRP io registers */ 128 struct mx6sdl_iomux_grp_regs mx6sdl_grp_ioregs = { 129 /* DDR3 */ 130 .grp_ddr_type = 0x000c0000, 131 /* SDQS[0:7]: Differential input, 40 ohm */ 132 .grp_ddrmode_ctl = 0x00020000, 133 /* disable DDR pullups */ 134 .grp_ddrpke = 0x00000000, 135 /* ADDR[00:16], SDBA[0:1]: 40 ohm */ 136 .grp_addds = 0x00000030, 137 /* CS0/CS1/SDBA2/CKE0/CKE1/SDWE: 40 ohm */ 138 .grp_ctlds = 0x00000030, 139 /* DATA[00:63]: Differential input, 40 ohm */ 140 .grp_ddrmode = 0x00020000, 141 .grp_b0ds = 0x00000030, 142 .grp_b1ds = 0x00000030, 143 .grp_b2ds = 0x00000030, 144 .grp_b3ds = 0x00000030, 145 .grp_b4ds = 0x00000030, 146 .grp_b5ds = 0x00000030, 147 .grp_b6ds = 0x00000030, 148 .grp_b7ds = 0x00000030, 149 }; 150 151 /* MT41K64M16JT-125 (1Gb density) */ 152 static struct mx6_ddr3_cfg mt41k64m16jt_125 = { 153 .mem_speed = 1600, 154 .density = 1, 155 .width = 16, 156 .banks = 8, 157 .rowaddr = 13, 158 .coladdr = 10, 159 .pagesz = 2, 160 .trcd = 1375, 161 .trcmin = 4875, 162 .trasmin = 3500, 163 }; 164 165 /* MT41K128M16JT-125 (2Gb density) */ 166 static struct mx6_ddr3_cfg mt41k128m16jt_125 = { 167 .mem_speed = 1600, 168 .density = 2, 169 .width = 16, 170 .banks = 8, 171 .rowaddr = 14, 172 .coladdr = 10, 173 .pagesz = 2, 174 .trcd = 1375, 175 .trcmin = 4875, 176 .trasmin = 3500, 177 }; 178 179 /* MT41K256M16HA-125 (4Gb density) */ 180 static struct mx6_ddr3_cfg mt41k256m16ha_125 = { 181 .mem_speed = 1600, 182 .density = 4, 183 .width = 16, 184 .banks = 8, 185 .rowaddr = 15, 186 .coladdr = 10, 187 .pagesz = 2, 188 .trcd = 1375, 189 .trcmin = 4875, 190 .trasmin = 3500, 191 }; 192 193 /* MT41K512M16HA-125 (8Gb density) */ 194 static struct mx6_ddr3_cfg mt41k512m16ha_125 = { 195 .mem_speed = 1600, 196 .density = 8, 197 .width = 16, 198 .banks = 8, 199 .rowaddr = 16, 200 .coladdr = 10, 201 .pagesz = 2, 202 .trcd = 1375, 203 .trcmin = 4875, 204 .trasmin = 3500, 205 }; 206 207 /* 208 * calibration - these are the various CPU/DDR3 combinations we support 209 */ 210 static struct mx6_mmdc_calibration mx6sdl_64x16_mmdc_calib = { 211 /* write leveling calibration determine */ 212 .p0_mpwldectrl0 = 0x004C004E, 213 .p0_mpwldectrl1 = 0x00440044, 214 /* Read DQS Gating calibration */ 215 .p0_mpdgctrl0 = 0x42440247, 216 .p0_mpdgctrl1 = 0x02310232, 217 /* Read Calibration: DQS delay relative to DQ read access */ 218 .p0_mprddlctl = 0x45424746, 219 /* Write Calibration: DQ/DM delay relative to DQS write access */ 220 .p0_mpwrdlctl = 0x33382C31, 221 }; 222 223 static struct mx6_mmdc_calibration mx6dq_256x16_mmdc_calib = { 224 /* write leveling calibration determine */ 225 .p0_mpwldectrl0 = 0x001B0016, 226 .p0_mpwldectrl1 = 0x000C000E, 227 /* Read DQS Gating calibration */ 228 .p0_mpdgctrl0 = 0x4324033A, 229 .p0_mpdgctrl1 = 0x00000000, 230 /* Read Calibration: DQS delay relative to DQ read access */ 231 .p0_mprddlctl = 0x40403438, 232 /* Write Calibration: DQ/DM delay relative to DQS write access */ 233 .p0_mpwrdlctl = 0x40403D36, 234 }; 235 236 static struct mx6_mmdc_calibration mx6sdl_256x16_mmdc_calib = { 237 /* write leveling calibration determine */ 238 .p0_mpwldectrl0 = 0x00420043, 239 .p0_mpwldectrl1 = 0x0016001A, 240 /* Read DQS Gating calibration */ 241 .p0_mpdgctrl0 = 0x4238023B, 242 .p0_mpdgctrl1 = 0x00000000, 243 /* Read Calibration: DQS delay relative to DQ read access */ 244 .p0_mprddlctl = 0x40404849, 245 /* Write Calibration: DQ/DM delay relative to DQS write access */ 246 .p0_mpwrdlctl = 0x40402E2F, 247 }; 248 249 static struct mx6_mmdc_calibration mx6dq_128x32_mmdc_calib = { 250 /* write leveling calibration determine */ 251 .p0_mpwldectrl0 = 0x00190017, 252 .p0_mpwldectrl1 = 0x00140026, 253 /* Read DQS Gating calibration */ 254 .p0_mpdgctrl0 = 0x43380347, 255 .p0_mpdgctrl1 = 0x433C034D, 256 /* Read Calibration: DQS delay relative to DQ read access */ 257 .p0_mprddlctl = 0x3C313539, 258 /* Write Calibration: DQ/DM delay relative to DQS write access */ 259 .p0_mpwrdlctl = 0x36393C39, 260 }; 261 262 static struct mx6_mmdc_calibration mx6sdl_128x32_mmdc_calib = { 263 /* write leveling calibration determine */ 264 .p0_mpwldectrl0 = 0x003C003C, 265 .p0_mpwldectrl1 = 0x001F002A, 266 /* Read DQS Gating calibration */ 267 .p0_mpdgctrl0 = 0x42410244, 268 .p0_mpdgctrl1 = 0x4234023A, 269 /* Read Calibration: DQS delay relative to DQ read access */ 270 .p0_mprddlctl = 0x484A4C4B, 271 /* Write Calibration: DQ/DM delay relative to DQS write access */ 272 .p0_mpwrdlctl = 0x33342B32, 273 }; 274 275 static struct mx6_mmdc_calibration mx6dq_128x64_mmdc_calib = { 276 /* write leveling calibration determine */ 277 .p0_mpwldectrl0 = 0x00190017, 278 .p0_mpwldectrl1 = 0x00140026, 279 .p1_mpwldectrl0 = 0x0021001C, 280 .p1_mpwldectrl1 = 0x0011001D, 281 /* Read DQS Gating calibration */ 282 .p0_mpdgctrl0 = 0x43380347, 283 .p0_mpdgctrl1 = 0x433C034D, 284 .p1_mpdgctrl0 = 0x032C0324, 285 .p1_mpdgctrl1 = 0x03310232, 286 /* Read Calibration: DQS delay relative to DQ read access */ 287 .p0_mprddlctl = 0x3C313539, 288 .p1_mprddlctl = 0x37343141, 289 /* Write Calibration: DQ/DM delay relative to DQS write access */ 290 .p0_mpwrdlctl = 0x36393C39, 291 .p1_mpwrdlctl = 0x42344438, 292 }; 293 294 static struct mx6_mmdc_calibration mx6sdl_128x64_mmdc_calib = { 295 /* write leveling calibration determine */ 296 .p0_mpwldectrl0 = 0x003C003C, 297 .p0_mpwldectrl1 = 0x001F002A, 298 .p1_mpwldectrl0 = 0x00330038, 299 .p1_mpwldectrl1 = 0x0022003F, 300 /* Read DQS Gating calibration */ 301 .p0_mpdgctrl0 = 0x42410244, 302 .p0_mpdgctrl1 = 0x4234023A, 303 .p1_mpdgctrl0 = 0x022D022D, 304 .p1_mpdgctrl1 = 0x021C0228, 305 /* Read Calibration: DQS delay relative to DQ read access */ 306 .p0_mprddlctl = 0x484A4C4B, 307 .p1_mprddlctl = 0x4B4D4E4B, 308 /* Write Calibration: DQ/DM delay relative to DQS write access */ 309 .p0_mpwrdlctl = 0x33342B32, 310 .p1_mpwrdlctl = 0x3933332B, 311 }; 312 313 static struct mx6_mmdc_calibration mx6dq_256x32_mmdc_calib = { 314 /* write leveling calibration determine */ 315 .p0_mpwldectrl0 = 0x001E001A, 316 .p0_mpwldectrl1 = 0x0026001F, 317 /* Read DQS Gating calibration */ 318 .p0_mpdgctrl0 = 0x43370349, 319 .p0_mpdgctrl1 = 0x032D0327, 320 /* Read Calibration: DQS delay relative to DQ read access */ 321 .p0_mprddlctl = 0x3D303639, 322 /* Write Calibration: DQ/DM delay relative to DQS write access */ 323 .p0_mpwrdlctl = 0x32363934, 324 }; 325 326 static struct mx6_mmdc_calibration mx6sdl_256x32_mmdc_calib = { 327 /* write leveling calibration determine */ 328 .p0_mpwldectrl0 = 0X00480047, 329 .p0_mpwldectrl1 = 0X003D003F, 330 /* Read DQS Gating calibration */ 331 .p0_mpdgctrl0 = 0X423E0241, 332 .p0_mpdgctrl1 = 0X022B022C, 333 /* Read Calibration: DQS delay relative to DQ read access */ 334 .p0_mprddlctl = 0X49454A4A, 335 /* Write Calibration: DQ/DM delay relative to DQS write access */ 336 .p0_mpwrdlctl = 0X2E372C32, 337 }; 338 339 static struct mx6_mmdc_calibration mx6dq_256x64_mmdc_calib = { 340 /* write leveling calibration determine */ 341 .p0_mpwldectrl0 = 0X00220021, 342 .p0_mpwldectrl1 = 0X00200030, 343 .p1_mpwldectrl0 = 0X002D0027, 344 .p1_mpwldectrl1 = 0X00150026, 345 /* Read DQS Gating calibration */ 346 .p0_mpdgctrl0 = 0x43330342, 347 .p0_mpdgctrl1 = 0x0339034A, 348 .p1_mpdgctrl0 = 0x032F0325, 349 .p1_mpdgctrl1 = 0x032F022E, 350 /* Read Calibration: DQS delay relative to DQ read access */ 351 .p0_mprddlctl = 0X3A2E3437, 352 .p1_mprddlctl = 0X35312F3F, 353 /* Write Calibration: DQ/DM delay relative to DQS write access */ 354 .p0_mpwrdlctl = 0X33363B37, 355 .p1_mpwrdlctl = 0X40304239, 356 }; 357 358 static struct mx6_mmdc_calibration mx6sdl_256x64_mmdc_calib = { 359 /* write leveling calibration determine */ 360 .p0_mpwldectrl0 = 0x0048004A, 361 .p0_mpwldectrl1 = 0x003F004A, 362 .p1_mpwldectrl0 = 0x001E0028, 363 .p1_mpwldectrl1 = 0x002C0043, 364 /* Read DQS Gating calibration */ 365 .p0_mpdgctrl0 = 0x02250219, 366 .p0_mpdgctrl1 = 0x01790202, 367 .p1_mpdgctrl0 = 0x02080208, 368 .p1_mpdgctrl1 = 0x016C0175, 369 /* Read Calibration: DQS delay relative to DQ read access */ 370 .p0_mprddlctl = 0x4A4C4D4C, 371 .p1_mprddlctl = 0x494C4A48, 372 /* Write Calibration: DQ/DM delay relative to DQS write access */ 373 .p0_mpwrdlctl = 0x403F3437, 374 .p1_mpwrdlctl = 0x383A3930, 375 }; 376 377 static struct mx6_mmdc_calibration mx6dq_512x32_mmdc_calib = { 378 /* write leveling calibration determine */ 379 .p0_mpwldectrl0 = 0x002A0025, 380 .p0_mpwldectrl1 = 0x003A002A, 381 /* Read DQS Gating calibration */ 382 .p0_mpdgctrl0 = 0x43430356, 383 .p0_mpdgctrl1 = 0x033C0335, 384 /* Read Calibration: DQS delay relative to DQ read access */ 385 .p0_mprddlctl = 0x4B373F42, 386 /* Write Calibration: DQ/DM delay relative to DQS write access */ 387 .p0_mpwrdlctl = 0x303E3C36, 388 }; 389 390 static struct mx6_mmdc_calibration mx6dq_512x64_mmdc_calib = { 391 /* write leveling calibration determine */ 392 .p0_mpwldectrl0 = 0x00230020, 393 .p0_mpwldectrl1 = 0x002F002A, 394 .p1_mpwldectrl0 = 0x001D0027, 395 .p1_mpwldectrl1 = 0x00100023, 396 /* Read DQS Gating calibration */ 397 .p0_mpdgctrl0 = 0x03250339, 398 .p0_mpdgctrl1 = 0x031C0316, 399 .p1_mpdgctrl0 = 0x03210331, 400 .p1_mpdgctrl1 = 0x031C025A, 401 /* Read Calibration: DQS delay relative to DQ read access */ 402 .p0_mprddlctl = 0x40373C40, 403 .p1_mprddlctl = 0x3A373646, 404 /* Write Calibration: DQ/DM delay relative to DQS write access */ 405 .p0_mpwrdlctl = 0x2E353933, 406 .p1_mpwrdlctl = 0x3C2F3F35, 407 }; 408 409 static void spl_dram_init(int width, int size_mb, int board_model) 410 { 411 struct mx6_ddr3_cfg *mem = NULL; 412 struct mx6_mmdc_calibration *calib = NULL; 413 struct mx6_ddr_sysinfo sysinfo = { 414 /* width of data bus:0=16,1=32,2=64 */ 415 .dsize = width/32, 416 /* config for full 4GB range so that get_mem_size() works */ 417 .cs_density = 32, /* 32Gb per CS */ 418 /* single chip select */ 419 .ncs = 1, 420 .cs1_mirror = 0, 421 .rtt_wr = 1 /*DDR3_RTT_60_OHM*/, /* RTT_Wr = RZQ/4 */ 422 #ifdef RTT_NOM_120OHM 423 .rtt_nom = 2 /*DDR3_RTT_120_OHM*/, /* RTT_Nom = RZQ/2 */ 424 #else 425 .rtt_nom = 1 /*DDR3_RTT_60_OHM*/, /* RTT_Nom = RZQ/4 */ 426 #endif 427 .walat = 1, /* Write additional latency */ 428 .ralat = 5, /* Read additional latency */ 429 .mif3_mode = 3, /* Command prediction working mode */ 430 .bi_on = 1, /* Bank interleaving enabled */ 431 .sde_to_rst = 0x10, /* 14 cycles, 200us (JEDEC default) */ 432 .rst_to_cke = 0x23, /* 33 cycles, 500us (JEDEC default) */ 433 .pd_fast_exit = 1, /* enable precharge power-down fast exit */ 434 .ddr_type = DDR_TYPE_DDR3, 435 .refsel = 1, /* Refresh cycles at 32KHz */ 436 .refr = 7, /* 8 refresh commands per refresh cycle */ 437 }; 438 439 /* 440 * MMDC Calibration requires the following data: 441 * mx6_mmdc_calibration - board-specific calibration (routing delays) 442 * these calibration values depend on board routing, SoC, and DDR 443 * mx6_ddr_sysinfo - board-specific memory architecture (width/cs/etc) 444 * mx6_ddr_cfg - chip specific timing/layout details 445 */ 446 if (width == 16 && size_mb == 128) { 447 mem = &mt41k64m16jt_125; 448 if (is_cpu_type(MXC_CPU_MX6Q)) 449 ; 450 else 451 calib = &mx6sdl_64x16_mmdc_calib; 452 debug("1gB density\n"); 453 } else if (width == 16 && size_mb == 256) { 454 /* 1x 2Gb density chip - same calib as 2x 2Gb */ 455 mem = &mt41k128m16jt_125; 456 if (is_cpu_type(MXC_CPU_MX6Q)) 457 calib = &mx6dq_128x32_mmdc_calib; 458 else 459 calib = &mx6sdl_128x32_mmdc_calib; 460 debug("2gB density\n"); 461 } else if (width == 16 && size_mb == 512) { 462 mem = &mt41k256m16ha_125; 463 if (is_cpu_type(MXC_CPU_MX6Q)) 464 calib = &mx6dq_256x16_mmdc_calib; 465 else 466 calib = &mx6sdl_256x16_mmdc_calib; 467 debug("4gB density\n"); 468 } else if (width == 32 && size_mb == 256) { 469 /* Same calib as width==16, size==128 */ 470 mem = &mt41k64m16jt_125; 471 if (is_cpu_type(MXC_CPU_MX6Q)) 472 ; 473 else 474 calib = &mx6sdl_64x16_mmdc_calib; 475 debug("1gB density\n"); 476 } else if (width == 32 && size_mb == 512) { 477 mem = &mt41k128m16jt_125; 478 if (is_cpu_type(MXC_CPU_MX6Q)) 479 calib = &mx6dq_128x32_mmdc_calib; 480 else 481 calib = &mx6sdl_128x32_mmdc_calib; 482 debug("2gB density\n"); 483 } else if (width == 32 && size_mb == 1024) { 484 mem = &mt41k256m16ha_125; 485 if (is_cpu_type(MXC_CPU_MX6Q)) 486 calib = &mx6dq_256x32_mmdc_calib; 487 else 488 calib = &mx6sdl_256x32_mmdc_calib; 489 debug("4gB density\n"); 490 } else if (width == 32 && size_mb == 2048) { 491 mem = &mt41k512m16ha_125; 492 if (is_cpu_type(MXC_CPU_MX6Q)) 493 calib = &mx6dq_512x32_mmdc_calib; 494 debug("8gB density\n"); 495 } else if (width == 64 && size_mb == 512) { 496 mem = &mt41k64m16jt_125; 497 debug("1gB density\n"); 498 } else if (width == 64 && size_mb == 1024) { 499 mem = &mt41k128m16jt_125; 500 if (is_cpu_type(MXC_CPU_MX6Q)) 501 calib = &mx6dq_128x64_mmdc_calib; 502 else 503 calib = &mx6sdl_128x64_mmdc_calib; 504 debug("2gB density\n"); 505 } else if (width == 64 && size_mb == 2048) { 506 mem = &mt41k256m16ha_125; 507 if (is_cpu_type(MXC_CPU_MX6Q)) 508 calib = &mx6dq_256x64_mmdc_calib; 509 else 510 calib = &mx6sdl_256x64_mmdc_calib; 511 debug("4gB density\n"); 512 } else if (width == 64 && size_mb == 4096) { 513 mem = &mt41k512m16ha_125; 514 if (is_cpu_type(MXC_CPU_MX6Q)) 515 calib = &mx6dq_512x64_mmdc_calib; 516 debug("8gB density\n"); 517 } 518 519 if (!(mem && calib)) { 520 puts("Error: Invalid Calibration/Board Configuration\n"); 521 printf("MEM : %s\n", mem ? "OKAY" : "NULL"); 522 printf("CALIB : %s\n", calib ? "OKAY" : "NULL"); 523 printf("CPUTYPE: %s\n", 524 is_cpu_type(MXC_CPU_MX6Q) ? "IMX6Q" : "IMX6DL"); 525 printf("SIZE_MB: %d\n", size_mb); 526 printf("WIDTH : %d\n", width); 527 hang(); 528 } 529 530 if (is_cpu_type(MXC_CPU_MX6Q)) 531 mx6dq_dram_iocfg(width, &mx6dq_ddr_ioregs, 532 &mx6dq_grp_ioregs); 533 else 534 mx6sdl_dram_iocfg(width, &mx6sdl_ddr_ioregs, 535 &mx6sdl_grp_ioregs); 536 mx6_dram_cfg(&sysinfo, calib, mem); 537 } 538 539 static void ccgr_init(void) 540 { 541 struct mxc_ccm_reg *ccm = (struct mxc_ccm_reg *)CCM_BASE_ADDR; 542 543 writel(0x00C03F3F, &ccm->CCGR0); 544 writel(0x0030FC03, &ccm->CCGR1); 545 writel(0x0FFFC000, &ccm->CCGR2); 546 writel(0x3FF00000, &ccm->CCGR3); 547 writel(0xFFFFF300, &ccm->CCGR4); /* enable NAND/GPMI/BCH clks */ 548 writel(0x0F0000C3, &ccm->CCGR5); 549 writel(0x000003FF, &ccm->CCGR6); 550 } 551 552 static void gpr_init(void) 553 { 554 struct iomuxc *iomux = (struct iomuxc *)IOMUXC_BASE_ADDR; 555 556 /* enable AXI cache for VDOA/VPU/IPU */ 557 writel(0xF00000CF, &iomux->gpr[4]); 558 /* set IPU AXI-id0 Qos=0xf(bypass) AXI-id1 Qos=0x7 */ 559 writel(0x007F007F, &iomux->gpr[6]); 560 writel(0x007F007F, &iomux->gpr[7]); 561 } 562 563 /* 564 * called from C runtime startup code (arch/arm/lib/crt0.S:_main) 565 * - we have a stack and a place to store GD, both in SRAM 566 * - no variable global data is available 567 */ 568 void board_init_f(ulong dummy) 569 { 570 struct ventana_board_info ventana_info; 571 int board_model; 572 573 /* setup clock gating */ 574 ccgr_init(); 575 576 /* setup AIPS and disable watchdog */ 577 arch_cpu_init(); 578 579 /* setup AXI */ 580 gpr_init(); 581 582 /* iomux and setup of i2c */ 583 setup_iomux_uart(); 584 setup_ventana_i2c(); 585 586 /* setup GP timer */ 587 timer_init(); 588 589 /* UART clocks enabled and gd valid - init serial console */ 590 preloader_console_init(); 591 592 /* read/validate EEPROM info to determine board model and SDRAM cfg */ 593 board_model = read_eeprom(CONFIG_I2C_GSC, &ventana_info); 594 595 /* configure model-specific gpio */ 596 setup_iomux_gpio(board_model, &ventana_info); 597 598 /* provide some some default: 32bit 128MB */ 599 if (GW_UNKNOWN == board_model) 600 hang(); 601 602 /* configure MMDC for SDRAM width/size and per-model calibration */ 603 spl_dram_init(8 << ventana_info.sdram_width, 604 16 << ventana_info.sdram_size, 605 board_model); 606 607 /* Clear the BSS. */ 608 memset(__bss_start, 0, __bss_end - __bss_start); 609 } 610 611 /* called from board_init_r after gd setup if CONFIG_SPL_BOARD_INIT defined */ 612 /* its our chance to print info about boot device */ 613 void spl_board_init(void) 614 { 615 /* determine boot device from SRC_SBMR1 (BOOT_CFG[4:1]) or SRC_GPR9 */ 616 u32 boot_device = spl_boot_device(); 617 618 switch (boot_device) { 619 case BOOT_DEVICE_MMC1: 620 puts("Booting from MMC\n"); 621 break; 622 case BOOT_DEVICE_NAND: 623 puts("Booting from NAND\n"); 624 break; 625 case BOOT_DEVICE_SATA: 626 puts("Booting from SATA\n"); 627 break; 628 default: 629 puts("Unknown boot device\n"); 630 } 631 632 /* PMIC init */ 633 setup_pmic(); 634 } 635 636 #ifdef CONFIG_SPL_OS_BOOT 637 /* return 1 if we wish to boot to uboot vs os (falcon mode) */ 638 int spl_start_uboot(void) 639 { 640 unsigned char ret = 1; 641 642 debug("%s\n", __func__); 643 #ifdef CONFIG_SPL_ENV_SUPPORT 644 env_init(); 645 env_relocate_spec(); 646 debug("boot_os=%s\n", getenv("boot_os")); 647 if (getenv_yesno("boot_os") == 1) 648 ret = 0; 649 #else 650 /* use i2c-0:0x50:0x00 for falcon boot mode (0=linux, else uboot) */ 651 i2c_set_bus_num(0); 652 gsc_i2c_read(0x50, 0x0, 1, &ret, 1); 653 #endif 654 if (!ret) 655 gsc_boot_wd_disable(); 656 657 debug("%s booting %s\n", __func__, ret ? "uboot" : "linux"); 658 return ret; 659 } 660 #endif 661