1 /* 2 * Copyright (C) 2013 Gateworks Corporation 3 * 4 * Author: Tim Harvey <tharvey@gateworks.com> 5 * 6 * SPDX-License-Identifier: GPL-2.0+ 7 */ 8 9 #include <common.h> 10 #include <asm/io.h> 11 #include <asm/arch/clock.h> 12 #include <asm/arch/imx-regs.h> 13 #include <asm/arch/iomux.h> 14 #include <asm/arch/mx6-pins.h> 15 #include <asm/arch/mxc_hdmi.h> 16 #include <asm/arch/crm_regs.h> 17 #include <asm/arch/sys_proto.h> 18 #include <asm/gpio.h> 19 #include <asm/imx-common/iomux-v3.h> 20 #include <asm/imx-common/mxc_i2c.h> 21 #include <asm/imx-common/boot_mode.h> 22 #include <asm/imx-common/sata.h> 23 #include <asm/imx-common/video.h> 24 #include <jffs2/load_kernel.h> 25 #include <hwconfig.h> 26 #include <i2c.h> 27 #include <linux/ctype.h> 28 #include <fdt_support.h> 29 #include <fsl_esdhc.h> 30 #include <miiphy.h> 31 #include <mmc.h> 32 #include <mtd_node.h> 33 #include <netdev.h> 34 #include <power/pmic.h> 35 #include <power/ltc3676_pmic.h> 36 #include <power/pfuze100_pmic.h> 37 #include <fdt_support.h> 38 #include <jffs2/load_kernel.h> 39 #include <spi_flash.h> 40 41 #include "gsc.h" 42 #include "ventana_eeprom.h" 43 44 DECLARE_GLOBAL_DATA_PTR; 45 46 /* GPIO's common to all baseboards */ 47 #define GP_PHY_RST IMX_GPIO_NR(1, 30) 48 #define GP_USB_OTG_PWR IMX_GPIO_NR(3, 22) 49 #define GP_SD3_CD IMX_GPIO_NR(7, 0) 50 #define GP_RS232_EN IMX_GPIO_NR(2, 11) 51 #define GP_MSATA_SEL IMX_GPIO_NR(2, 8) 52 53 /* I2C bus numbers */ 54 #define I2C_GSC 0 55 #define I2C_PMIC 1 56 57 #define UART_PAD_CTRL (PAD_CTL_PKE | PAD_CTL_PUE | \ 58 PAD_CTL_PUS_100K_UP | PAD_CTL_SPEED_MED | \ 59 PAD_CTL_DSE_40ohm | PAD_CTL_SRE_FAST | PAD_CTL_HYS) 60 61 #define USDHC_PAD_CTRL (PAD_CTL_PKE | PAD_CTL_PUE | \ 62 PAD_CTL_PUS_47K_UP | PAD_CTL_SPEED_LOW | \ 63 PAD_CTL_DSE_80ohm | PAD_CTL_SRE_FAST | PAD_CTL_HYS) 64 65 #define ENET_PAD_CTRL (PAD_CTL_PKE | PAD_CTL_PUE | \ 66 PAD_CTL_PUS_100K_UP | PAD_CTL_SPEED_MED | \ 67 PAD_CTL_DSE_40ohm | PAD_CTL_HYS) 68 69 #define SPI_PAD_CTRL (PAD_CTL_HYS | \ 70 PAD_CTL_PUS_100K_DOWN | PAD_CTL_SPEED_MED | \ 71 PAD_CTL_DSE_40ohm | PAD_CTL_SRE_FAST) 72 73 #define DIO_PAD_CTRL (PAD_CTL_PKE | PAD_CTL_PUE | \ 74 PAD_CTL_PUS_100K_UP | PAD_CTL_SPEED_MED | \ 75 PAD_CTL_DSE_34ohm | PAD_CTL_HYS | PAD_CTL_SRE_FAST) 76 77 #define I2C_PAD_CTRL (PAD_CTL_PUS_100K_UP | \ 78 PAD_CTL_SPEED_MED | PAD_CTL_DSE_40ohm | PAD_CTL_HYS | \ 79 PAD_CTL_ODE | PAD_CTL_SRE_FAST) 80 81 /* 82 * EEPROM board info struct populated by read_eeprom so that we only have to 83 * read it once. 84 */ 85 static struct ventana_board_info ventana_info; 86 87 enum { 88 GW54proto, /* original GW5400-A prototype */ 89 GW51xx, 90 GW52xx, 91 GW53xx, 92 GW54xx, 93 GW_UNKNOWN, 94 }; 95 96 int board_type; 97 98 /* UART1: Function varies per baseboard */ 99 iomux_v3_cfg_t const uart1_pads[] = { 100 MX6_PAD_SD3_DAT6__UART1_RX_DATA | MUX_PAD_CTRL(UART_PAD_CTRL), 101 MX6_PAD_SD3_DAT7__UART1_TX_DATA | MUX_PAD_CTRL(UART_PAD_CTRL), 102 }; 103 104 /* UART2: Serial Console */ 105 iomux_v3_cfg_t const uart2_pads[] = { 106 MX6_PAD_SD4_DAT7__UART2_TX_DATA | MUX_PAD_CTRL(UART_PAD_CTRL), 107 MX6_PAD_SD4_DAT4__UART2_RX_DATA | MUX_PAD_CTRL(UART_PAD_CTRL), 108 }; 109 110 #define PC MUX_PAD_CTRL(I2C_PAD_CTRL) 111 112 /* I2C1: GSC */ 113 struct i2c_pads_info i2c_pad_info0 = { 114 .scl = { 115 .i2c_mode = MX6_PAD_EIM_D21__I2C1_SCL | PC, 116 .gpio_mode = MX6_PAD_EIM_D21__GPIO3_IO21 | PC, 117 .gp = IMX_GPIO_NR(3, 21) 118 }, 119 .sda = { 120 .i2c_mode = MX6_PAD_EIM_D28__I2C1_SDA | PC, 121 .gpio_mode = MX6_PAD_EIM_D28__GPIO3_IO28 | PC, 122 .gp = IMX_GPIO_NR(3, 28) 123 } 124 }; 125 126 /* I2C2: PMIC/PCIe Switch/PCIe Clock/Mezz */ 127 struct i2c_pads_info i2c_pad_info1 = { 128 .scl = { 129 .i2c_mode = MX6_PAD_KEY_COL3__I2C2_SCL | PC, 130 .gpio_mode = MX6_PAD_KEY_COL3__GPIO4_IO12 | PC, 131 .gp = IMX_GPIO_NR(4, 12) 132 }, 133 .sda = { 134 .i2c_mode = MX6_PAD_KEY_ROW3__I2C2_SDA | PC, 135 .gpio_mode = MX6_PAD_KEY_ROW3__GPIO4_IO13 | PC, 136 .gp = IMX_GPIO_NR(4, 13) 137 } 138 }; 139 140 /* I2C3: Misc/Expansion */ 141 struct i2c_pads_info i2c_pad_info2 = { 142 .scl = { 143 .i2c_mode = MX6_PAD_GPIO_3__I2C3_SCL | PC, 144 .gpio_mode = MX6_PAD_GPIO_3__GPIO1_IO03 | PC, 145 .gp = IMX_GPIO_NR(1, 3) 146 }, 147 .sda = { 148 .i2c_mode = MX6_PAD_GPIO_6__I2C3_SDA | PC, 149 .gpio_mode = MX6_PAD_GPIO_6__GPIO1_IO06 | PC, 150 .gp = IMX_GPIO_NR(1, 6) 151 } 152 }; 153 154 /* MMC */ 155 iomux_v3_cfg_t const usdhc3_pads[] = { 156 MX6_PAD_SD3_CLK__SD3_CLK | MUX_PAD_CTRL(USDHC_PAD_CTRL), 157 MX6_PAD_SD3_CMD__SD3_CMD | MUX_PAD_CTRL(USDHC_PAD_CTRL), 158 MX6_PAD_SD3_DAT0__SD3_DATA0 | MUX_PAD_CTRL(USDHC_PAD_CTRL), 159 MX6_PAD_SD3_DAT1__SD3_DATA1 | MUX_PAD_CTRL(USDHC_PAD_CTRL), 160 MX6_PAD_SD3_DAT2__SD3_DATA2 | MUX_PAD_CTRL(USDHC_PAD_CTRL), 161 MX6_PAD_SD3_DAT3__SD3_DATA3 | MUX_PAD_CTRL(USDHC_PAD_CTRL), 162 MX6_PAD_SD3_DAT5__GPIO7_IO00 | MUX_PAD_CTRL(NO_PAD_CTRL), /* CD */ 163 }; 164 165 /* ENET */ 166 iomux_v3_cfg_t const enet_pads[] = { 167 MX6_PAD_ENET_MDIO__ENET_MDIO | MUX_PAD_CTRL(ENET_PAD_CTRL), 168 MX6_PAD_ENET_MDC__ENET_MDC | MUX_PAD_CTRL(ENET_PAD_CTRL), 169 MX6_PAD_RGMII_TXC__RGMII_TXC | MUX_PAD_CTRL(ENET_PAD_CTRL), 170 MX6_PAD_RGMII_TD0__RGMII_TD0 | MUX_PAD_CTRL(ENET_PAD_CTRL), 171 MX6_PAD_RGMII_TD1__RGMII_TD1 | MUX_PAD_CTRL(ENET_PAD_CTRL), 172 MX6_PAD_RGMII_TD2__RGMII_TD2 | MUX_PAD_CTRL(ENET_PAD_CTRL), 173 MX6_PAD_RGMII_TD3__RGMII_TD3 | MUX_PAD_CTRL(ENET_PAD_CTRL), 174 MX6_PAD_RGMII_TX_CTL__RGMII_TX_CTL | MUX_PAD_CTRL(ENET_PAD_CTRL), 175 MX6_PAD_ENET_REF_CLK__ENET_TX_CLK | MUX_PAD_CTRL(ENET_PAD_CTRL), 176 MX6_PAD_RGMII_RXC__RGMII_RXC | MUX_PAD_CTRL(ENET_PAD_CTRL), 177 MX6_PAD_RGMII_RD0__RGMII_RD0 | MUX_PAD_CTRL(ENET_PAD_CTRL), 178 MX6_PAD_RGMII_RD1__RGMII_RD1 | MUX_PAD_CTRL(ENET_PAD_CTRL), 179 MX6_PAD_RGMII_RD2__RGMII_RD2 | MUX_PAD_CTRL(ENET_PAD_CTRL), 180 MX6_PAD_RGMII_RD3__RGMII_RD3 | MUX_PAD_CTRL(ENET_PAD_CTRL), 181 MX6_PAD_RGMII_RX_CTL__RGMII_RX_CTL | MUX_PAD_CTRL(ENET_PAD_CTRL), 182 /* PHY nRST */ 183 MX6_PAD_ENET_TXD0__GPIO1_IO30 | MUX_PAD_CTRL(NO_PAD_CTRL), 184 }; 185 186 /* NAND */ 187 iomux_v3_cfg_t const nfc_pads[] = { 188 MX6_PAD_NANDF_CLE__NAND_CLE | MUX_PAD_CTRL(NO_PAD_CTRL), 189 MX6_PAD_NANDF_ALE__NAND_ALE | MUX_PAD_CTRL(NO_PAD_CTRL), 190 MX6_PAD_NANDF_WP_B__NAND_WP_B | MUX_PAD_CTRL(NO_PAD_CTRL), 191 MX6_PAD_NANDF_RB0__NAND_READY_B | MUX_PAD_CTRL(NO_PAD_CTRL), 192 MX6_PAD_NANDF_CS0__NAND_CE0_B | MUX_PAD_CTRL(NO_PAD_CTRL), 193 MX6_PAD_SD4_CMD__NAND_RE_B | MUX_PAD_CTRL(NO_PAD_CTRL), 194 MX6_PAD_SD4_CLK__NAND_WE_B | MUX_PAD_CTRL(NO_PAD_CTRL), 195 MX6_PAD_NANDF_D0__NAND_DATA00 | MUX_PAD_CTRL(NO_PAD_CTRL), 196 MX6_PAD_NANDF_D1__NAND_DATA01 | MUX_PAD_CTRL(NO_PAD_CTRL), 197 MX6_PAD_NANDF_D2__NAND_DATA02 | MUX_PAD_CTRL(NO_PAD_CTRL), 198 MX6_PAD_NANDF_D3__NAND_DATA03 | MUX_PAD_CTRL(NO_PAD_CTRL), 199 MX6_PAD_NANDF_D4__NAND_DATA04 | MUX_PAD_CTRL(NO_PAD_CTRL), 200 MX6_PAD_NANDF_D5__NAND_DATA05 | MUX_PAD_CTRL(NO_PAD_CTRL), 201 MX6_PAD_NANDF_D6__NAND_DATA06 | MUX_PAD_CTRL(NO_PAD_CTRL), 202 MX6_PAD_NANDF_D7__NAND_DATA07 | MUX_PAD_CTRL(NO_PAD_CTRL), 203 }; 204 205 #ifdef CONFIG_CMD_NAND 206 static void setup_gpmi_nand(void) 207 { 208 struct mxc_ccm_reg *mxc_ccm = (struct mxc_ccm_reg *)CCM_BASE_ADDR; 209 210 /* config gpmi nand iomux */ 211 imx_iomux_v3_setup_multiple_pads(nfc_pads, ARRAY_SIZE(nfc_pads)); 212 213 /* config gpmi and bch clock to 100 MHz */ 214 clrsetbits_le32(&mxc_ccm->cs2cdr, 215 MXC_CCM_CS2CDR_ENFC_CLK_PODF_MASK | 216 MXC_CCM_CS2CDR_ENFC_CLK_PRED_MASK | 217 MXC_CCM_CS2CDR_ENFC_CLK_SEL_MASK, 218 MXC_CCM_CS2CDR_ENFC_CLK_PODF(0) | 219 MXC_CCM_CS2CDR_ENFC_CLK_PRED(3) | 220 MXC_CCM_CS2CDR_ENFC_CLK_SEL(3)); 221 222 /* enable gpmi and bch clock gating */ 223 setbits_le32(&mxc_ccm->CCGR4, 224 MXC_CCM_CCGR4_RAWNAND_U_BCH_INPUT_APB_MASK | 225 MXC_CCM_CCGR4_RAWNAND_U_GPMI_BCH_INPUT_BCH_MASK | 226 MXC_CCM_CCGR4_RAWNAND_U_GPMI_BCH_INPUT_GPMI_IO_MASK | 227 MXC_CCM_CCGR4_RAWNAND_U_GPMI_INPUT_APB_MASK | 228 MXC_CCM_CCGR4_PL301_MX6QPER1_BCH_OFFSET); 229 230 /* enable apbh clock gating */ 231 setbits_le32(&mxc_ccm->CCGR0, MXC_CCM_CCGR0_APBHDMA_MASK); 232 } 233 #endif 234 235 static void setup_iomux_enet(void) 236 { 237 imx_iomux_v3_setup_multiple_pads(enet_pads, ARRAY_SIZE(enet_pads)); 238 239 /* toggle PHY_RST# */ 240 gpio_direction_output(GP_PHY_RST, 0); 241 mdelay(2); 242 gpio_set_value(GP_PHY_RST, 1); 243 } 244 245 static void setup_iomux_uart(void) 246 { 247 imx_iomux_v3_setup_multiple_pads(uart1_pads, ARRAY_SIZE(uart1_pads)); 248 imx_iomux_v3_setup_multiple_pads(uart2_pads, ARRAY_SIZE(uart2_pads)); 249 } 250 251 #ifdef CONFIG_USB_EHCI_MX6 252 iomux_v3_cfg_t const usb_pads[] = { 253 MX6_PAD_GPIO_1__USB_OTG_ID | MUX_PAD_CTRL(DIO_PAD_CTRL), 254 MX6_PAD_KEY_COL4__USB_OTG_OC | MUX_PAD_CTRL(DIO_PAD_CTRL), 255 MX6_PAD_EIM_D22__GPIO3_IO22 | MUX_PAD_CTRL(DIO_PAD_CTRL), /* OTG PWR */ 256 }; 257 258 int board_ehci_hcd_init(int port) 259 { 260 struct ventana_board_info *info = &ventana_info; 261 262 imx_iomux_v3_setup_multiple_pads(usb_pads, ARRAY_SIZE(usb_pads)); 263 264 /* Reset USB HUB (present on GW54xx/GW53xx) */ 265 switch (info->model[3]) { 266 case '3': /* GW53xx */ 267 imx_iomux_v3_setup_pad(MX6_PAD_GPIO_9__GPIO1_IO09| 268 MUX_PAD_CTRL(NO_PAD_CTRL)); 269 gpio_direction_output(IMX_GPIO_NR(1, 9), 0); 270 mdelay(2); 271 gpio_set_value(IMX_GPIO_NR(1, 9), 1); 272 break; 273 case '4': /* GW54xx */ 274 imx_iomux_v3_setup_pad(MX6_PAD_SD1_DAT0__GPIO1_IO16 | 275 MUX_PAD_CTRL(NO_PAD_CTRL)); 276 gpio_direction_output(IMX_GPIO_NR(1, 16), 0); 277 mdelay(2); 278 gpio_set_value(IMX_GPIO_NR(1, 16), 1); 279 break; 280 } 281 282 return 0; 283 } 284 285 int board_ehci_power(int port, int on) 286 { 287 if (port) 288 return 0; 289 gpio_set_value(GP_USB_OTG_PWR, on); 290 return 0; 291 } 292 #endif /* CONFIG_USB_EHCI_MX6 */ 293 294 #ifdef CONFIG_FSL_ESDHC 295 struct fsl_esdhc_cfg usdhc_cfg = { USDHC3_BASE_ADDR }; 296 297 int board_mmc_getcd(struct mmc *mmc) 298 { 299 /* Card Detect */ 300 gpio_direction_input(GP_SD3_CD); 301 return !gpio_get_value(GP_SD3_CD); 302 } 303 304 int board_mmc_init(bd_t *bis) 305 { 306 /* Only one USDHC controller on Ventana */ 307 imx_iomux_v3_setup_multiple_pads(usdhc3_pads, ARRAY_SIZE(usdhc3_pads)); 308 usdhc_cfg.sdhc_clk = mxc_get_clock(MXC_ESDHC3_CLK); 309 usdhc_cfg.max_bus_width = 4; 310 311 return fsl_esdhc_initialize(bis, &usdhc_cfg); 312 } 313 #endif /* CONFIG_FSL_ESDHC */ 314 315 #ifdef CONFIG_MXC_SPI 316 iomux_v3_cfg_t const ecspi1_pads[] = { 317 /* SS1 */ 318 MX6_PAD_EIM_D19__GPIO3_IO19 | MUX_PAD_CTRL(SPI_PAD_CTRL), 319 MX6_PAD_EIM_D17__ECSPI1_MISO | MUX_PAD_CTRL(SPI_PAD_CTRL), 320 MX6_PAD_EIM_D18__ECSPI1_MOSI | MUX_PAD_CTRL(SPI_PAD_CTRL), 321 MX6_PAD_EIM_D16__ECSPI1_SCLK | MUX_PAD_CTRL(SPI_PAD_CTRL), 322 }; 323 324 static void setup_spi(void) 325 { 326 gpio_direction_output(CONFIG_SF_DEFAULT_CS, 1); 327 imx_iomux_v3_setup_multiple_pads(ecspi1_pads, 328 ARRAY_SIZE(ecspi1_pads)); 329 } 330 #endif 331 332 /* configure eth0 PHY board-specific LED behavior */ 333 int board_phy_config(struct phy_device *phydev) 334 { 335 unsigned short val; 336 337 /* Marvel 88E1510 */ 338 if (phydev->phy_id == 0x1410dd1) { 339 /* 340 * Page 3, Register 16: LED[2:0] Function Control Register 341 * LED[0] (SPD:Amber) R16_3.3:0 to 0111: on-GbE link 342 * LED[1] (LNK:Green) R16_3.7:4 to 0001: on-link, blink-activity 343 */ 344 phy_write(phydev, MDIO_DEVAD_NONE, 22, 3); 345 val = phy_read(phydev, MDIO_DEVAD_NONE, 16); 346 val &= 0xff00; 347 val |= 0x0017; 348 phy_write(phydev, MDIO_DEVAD_NONE, 16, val); 349 phy_write(phydev, MDIO_DEVAD_NONE, 22, 0); 350 } 351 352 if (phydev->drv->config) 353 phydev->drv->config(phydev); 354 355 return 0; 356 } 357 358 int board_eth_init(bd_t *bis) 359 { 360 setup_iomux_enet(); 361 362 #ifdef CONFIG_FEC_MXC 363 cpu_eth_init(bis); 364 #endif 365 366 #ifdef CONFIG_CI_UDC 367 /* For otg ethernet*/ 368 usb_eth_initialize(bis); 369 #endif 370 371 return 0; 372 } 373 374 #if defined(CONFIG_VIDEO_IPUV3) 375 376 static void enable_hdmi(struct display_info_t const *dev) 377 { 378 imx_enable_hdmi_phy(); 379 } 380 381 static int detect_i2c(struct display_info_t const *dev) 382 { 383 return i2c_set_bus_num(dev->bus) == 0 && 384 i2c_probe(dev->addr) == 0; 385 } 386 387 static void enable_lvds(struct display_info_t const *dev) 388 { 389 struct iomuxc *iomux = (struct iomuxc *) 390 IOMUXC_BASE_ADDR; 391 392 /* set CH0 data width to 24bit (IOMUXC_GPR2:5 0=18bit, 1=24bit) */ 393 u32 reg = readl(&iomux->gpr[2]); 394 reg |= IOMUXC_GPR2_DATA_WIDTH_CH0_24BIT; 395 writel(reg, &iomux->gpr[2]); 396 397 /* Enable Backlight */ 398 imx_iomux_v3_setup_pad(MX6_PAD_SD1_CMD__GPIO1_IO18 | 399 MUX_PAD_CTRL(NO_PAD_CTRL)); 400 gpio_direction_output(IMX_GPIO_NR(1, 18), 1); 401 } 402 403 struct display_info_t const displays[] = {{ 404 /* HDMI Output */ 405 .bus = -1, 406 .addr = 0, 407 .pixfmt = IPU_PIX_FMT_RGB24, 408 .detect = detect_hdmi, 409 .enable = enable_hdmi, 410 .mode = { 411 .name = "HDMI", 412 .refresh = 60, 413 .xres = 1024, 414 .yres = 768, 415 .pixclock = 15385, 416 .left_margin = 220, 417 .right_margin = 40, 418 .upper_margin = 21, 419 .lower_margin = 7, 420 .hsync_len = 60, 421 .vsync_len = 10, 422 .sync = FB_SYNC_EXT, 423 .vmode = FB_VMODE_NONINTERLACED 424 } }, { 425 /* Freescale MXC-LVDS1: HannStar HSD100PXN1-A00 w/ egalx_ts cont */ 426 .bus = 2, 427 .addr = 0x4, 428 .pixfmt = IPU_PIX_FMT_LVDS666, 429 .detect = detect_i2c, 430 .enable = enable_lvds, 431 .mode = { 432 .name = "Hannstar-XGA", 433 .refresh = 60, 434 .xres = 1024, 435 .yres = 768, 436 .pixclock = 15385, 437 .left_margin = 220, 438 .right_margin = 40, 439 .upper_margin = 21, 440 .lower_margin = 7, 441 .hsync_len = 60, 442 .vsync_len = 10, 443 .sync = FB_SYNC_EXT, 444 .vmode = FB_VMODE_NONINTERLACED 445 } } }; 446 size_t display_count = ARRAY_SIZE(displays); 447 448 static void setup_display(void) 449 { 450 struct mxc_ccm_reg *mxc_ccm = (struct mxc_ccm_reg *)CCM_BASE_ADDR; 451 struct iomuxc *iomux = (struct iomuxc *)IOMUXC_BASE_ADDR; 452 int reg; 453 454 enable_ipu_clock(); 455 imx_setup_hdmi(); 456 /* Turn on LDB0,IPU,IPU DI0 clocks */ 457 reg = __raw_readl(&mxc_ccm->CCGR3); 458 reg |= MXC_CCM_CCGR3_LDB_DI0_MASK; 459 writel(reg, &mxc_ccm->CCGR3); 460 461 /* set LDB0, LDB1 clk select to 011/011 */ 462 reg = readl(&mxc_ccm->cs2cdr); 463 reg &= ~(MXC_CCM_CS2CDR_LDB_DI0_CLK_SEL_MASK 464 |MXC_CCM_CS2CDR_LDB_DI1_CLK_SEL_MASK); 465 reg |= (3<<MXC_CCM_CS2CDR_LDB_DI0_CLK_SEL_OFFSET) 466 |(3<<MXC_CCM_CS2CDR_LDB_DI1_CLK_SEL_OFFSET); 467 writel(reg, &mxc_ccm->cs2cdr); 468 469 reg = readl(&mxc_ccm->cscmr2); 470 reg |= MXC_CCM_CSCMR2_LDB_DI0_IPU_DIV; 471 writel(reg, &mxc_ccm->cscmr2); 472 473 reg = readl(&mxc_ccm->chsccdr); 474 reg |= (CHSCCDR_CLK_SEL_LDB_DI0 475 <<MXC_CCM_CHSCCDR_IPU1_DI0_CLK_SEL_OFFSET); 476 writel(reg, &mxc_ccm->chsccdr); 477 478 reg = IOMUXC_GPR2_BGREF_RRMODE_EXTERNAL_RES 479 |IOMUXC_GPR2_DI1_VS_POLARITY_ACTIVE_HIGH 480 |IOMUXC_GPR2_DI0_VS_POLARITY_ACTIVE_LOW 481 |IOMUXC_GPR2_BIT_MAPPING_CH1_SPWG 482 |IOMUXC_GPR2_DATA_WIDTH_CH1_18BIT 483 |IOMUXC_GPR2_BIT_MAPPING_CH0_SPWG 484 |IOMUXC_GPR2_DATA_WIDTH_CH0_18BIT 485 |IOMUXC_GPR2_LVDS_CH1_MODE_DISABLED 486 |IOMUXC_GPR2_LVDS_CH0_MODE_ENABLED_DI0; 487 writel(reg, &iomux->gpr[2]); 488 489 reg = readl(&iomux->gpr[3]); 490 reg = (reg & ~IOMUXC_GPR3_LVDS0_MUX_CTL_MASK) 491 | (IOMUXC_GPR3_MUX_SRC_IPU1_DI0 492 <<IOMUXC_GPR3_LVDS0_MUX_CTL_OFFSET); 493 writel(reg, &iomux->gpr[3]); 494 495 /* Backlight CABEN on LVDS connector */ 496 imx_iomux_v3_setup_pad(MX6_PAD_SD2_CLK__GPIO1_IO10 | 497 MUX_PAD_CTRL(NO_PAD_CTRL)); 498 gpio_direction_output(IMX_GPIO_NR(1, 10), 0); 499 } 500 #endif /* CONFIG_VIDEO_IPUV3 */ 501 502 /* read ventana EEPROM, check for validity, and return baseboard type */ 503 static int 504 read_eeprom(void) 505 { 506 int i; 507 int chksum; 508 char baseboard; 509 int type; 510 struct ventana_board_info *info = &ventana_info; 511 unsigned char *buf = (unsigned char *)&ventana_info; 512 513 memset(info, 0, sizeof(ventana_info)); 514 515 /* 516 * On a board with a missing/depleted backup battery for GSC, the 517 * board may be ready to probe the GSC before its firmware is 518 * running. We will wait here indefinately for the GSC/EEPROM. 519 */ 520 while (1) { 521 if (0 == i2c_set_bus_num(I2C_GSC) && 522 0 == i2c_probe(GSC_EEPROM_ADDR)) 523 break; 524 mdelay(1); 525 } 526 527 /* read eeprom config section */ 528 if (gsc_i2c_read(GSC_EEPROM_ADDR, 0x00, 1, buf, sizeof(ventana_info))) { 529 puts("EEPROM: Failed to read EEPROM\n"); 530 info->model[0] = 0; 531 return GW_UNKNOWN; 532 } 533 534 /* sanity checks */ 535 if (info->model[0] != 'G' || info->model[1] != 'W') { 536 puts("EEPROM: Invalid Model in EEPROM\n"); 537 info->model[0] = 0; 538 return GW_UNKNOWN; 539 } 540 541 /* validate checksum */ 542 for (chksum = 0, i = 0; i < sizeof(*info)-2; i++) 543 chksum += buf[i]; 544 if ((info->chksum[0] != chksum>>8) || 545 (info->chksum[1] != (chksum&0xff))) { 546 puts("EEPROM: Failed EEPROM checksum\n"); 547 info->model[0] = 0; 548 return GW_UNKNOWN; 549 } 550 551 /* original GW5400-A prototype */ 552 baseboard = info->model[3]; 553 if (strncasecmp((const char *)info->model, "GW5400-A", 8) == 0) 554 baseboard = '0'; 555 556 switch (baseboard) { 557 case '0': /* original GW5400-A prototype */ 558 type = GW54proto; 559 break; 560 case '1': 561 type = GW51xx; 562 break; 563 case '2': 564 type = GW52xx; 565 break; 566 case '3': 567 type = GW53xx; 568 break; 569 case '4': 570 type = GW54xx; 571 break; 572 default: 573 printf("EEPROM: Unknown model in EEPROM: %s\n", info->model); 574 type = GW_UNKNOWN; 575 break; 576 } 577 return type; 578 } 579 580 /* 581 * Baseboard specific GPIO 582 */ 583 584 /* common to add baseboards */ 585 static iomux_v3_cfg_t const gw_gpio_pads[] = { 586 /* MSATA_EN */ 587 MX6_PAD_SD4_DAT0__GPIO2_IO08 | MUX_PAD_CTRL(NO_PAD_CTRL), 588 /* RS232_EN# */ 589 MX6_PAD_SD4_DAT3__GPIO2_IO11 | MUX_PAD_CTRL(NO_PAD_CTRL), 590 }; 591 592 /* prototype */ 593 static iomux_v3_cfg_t const gwproto_gpio_pads[] = { 594 /* PANLEDG# */ 595 MX6_PAD_KEY_COL0__GPIO4_IO06 | MUX_PAD_CTRL(NO_PAD_CTRL), 596 /* PANLEDR# */ 597 MX6_PAD_KEY_ROW0__GPIO4_IO07 | MUX_PAD_CTRL(NO_PAD_CTRL), 598 /* LOCLED# */ 599 MX6_PAD_KEY_ROW4__GPIO4_IO15 | MUX_PAD_CTRL(NO_PAD_CTRL), 600 /* RS485_EN */ 601 MX6_PAD_SD3_DAT4__GPIO7_IO01 | MUX_PAD_CTRL(NO_PAD_CTRL), 602 /* IOEXP_PWREN# */ 603 MX6_PAD_EIM_A19__GPIO2_IO19 | MUX_PAD_CTRL(NO_PAD_CTRL), 604 /* IOEXP_IRQ# */ 605 MX6_PAD_EIM_A20__GPIO2_IO18 | MUX_PAD_CTRL(NO_PAD_CTRL), 606 /* VID_EN */ 607 MX6_PAD_EIM_D31__GPIO3_IO31 | MUX_PAD_CTRL(NO_PAD_CTRL), 608 /* DIOI2C_DIS# */ 609 MX6_PAD_GPIO_19__GPIO4_IO05 | MUX_PAD_CTRL(NO_PAD_CTRL), 610 /* PCICK_SSON */ 611 MX6_PAD_SD1_CLK__GPIO1_IO20 | MUX_PAD_CTRL(NO_PAD_CTRL), 612 /* PCI_RST# */ 613 MX6_PAD_ENET_TXD1__GPIO1_IO29 | MUX_PAD_CTRL(NO_PAD_CTRL), 614 }; 615 616 static iomux_v3_cfg_t const gw51xx_gpio_pads[] = { 617 /* PANLEDG# */ 618 MX6_PAD_KEY_COL0__GPIO4_IO06 | MUX_PAD_CTRL(NO_PAD_CTRL), 619 /* PANLEDR# */ 620 MX6_PAD_KEY_ROW0__GPIO4_IO07 | MUX_PAD_CTRL(NO_PAD_CTRL), 621 /* IOEXP_PWREN# */ 622 MX6_PAD_EIM_A19__GPIO2_IO19 | MUX_PAD_CTRL(NO_PAD_CTRL), 623 /* IOEXP_IRQ# */ 624 MX6_PAD_EIM_A20__GPIO2_IO18 | MUX_PAD_CTRL(NO_PAD_CTRL), 625 626 /* GPS_SHDN */ 627 MX6_PAD_GPIO_2__GPIO1_IO02 | MUX_PAD_CTRL(NO_PAD_CTRL), 628 /* VID_PWR */ 629 MX6_PAD_CSI0_DATA_EN__GPIO5_IO20 | MUX_PAD_CTRL(NO_PAD_CTRL), 630 /* PCI_RST# */ 631 MX6_PAD_GPIO_0__GPIO1_IO00 | MUX_PAD_CTRL(NO_PAD_CTRL), 632 }; 633 634 static iomux_v3_cfg_t const gw52xx_gpio_pads[] = { 635 /* PANLEDG# */ 636 MX6_PAD_KEY_COL0__GPIO4_IO06 | MUX_PAD_CTRL(NO_PAD_CTRL), 637 /* PANLEDR# */ 638 MX6_PAD_KEY_ROW0__GPIO4_IO07 | MUX_PAD_CTRL(NO_PAD_CTRL), 639 /* IOEXP_PWREN# */ 640 MX6_PAD_EIM_A19__GPIO2_IO19 | MUX_PAD_CTRL(NO_PAD_CTRL), 641 /* IOEXP_IRQ# */ 642 MX6_PAD_EIM_A20__GPIO2_IO18 | MUX_PAD_CTRL(NO_PAD_CTRL), 643 644 /* MX6_LOCLED# */ 645 MX6_PAD_KEY_ROW4__GPIO4_IO15 | MUX_PAD_CTRL(NO_PAD_CTRL), 646 /* GPS_SHDN */ 647 MX6_PAD_ENET_RXD0__GPIO1_IO27 | MUX_PAD_CTRL(NO_PAD_CTRL), 648 /* USBOTG_SEL */ 649 MX6_PAD_GPIO_2__GPIO1_IO02 | MUX_PAD_CTRL(NO_PAD_CTRL), 650 /* VID_PWR */ 651 MX6_PAD_EIM_D31__GPIO3_IO31 | MUX_PAD_CTRL(NO_PAD_CTRL), 652 /* PCI_RST# */ 653 MX6_PAD_ENET_TXD1__GPIO1_IO29 | MUX_PAD_CTRL(NO_PAD_CTRL), 654 }; 655 656 static iomux_v3_cfg_t const gw53xx_gpio_pads[] = { 657 /* PANLEDG# */ 658 MX6_PAD_KEY_COL0__GPIO4_IO06 | MUX_PAD_CTRL(NO_PAD_CTRL), 659 /* PANLEDR# */ 660 MX6_PAD_KEY_ROW0__GPIO4_IO07 | MUX_PAD_CTRL(NO_PAD_CTRL), 661 /* IOEXP_PWREN# */ 662 MX6_PAD_EIM_A19__GPIO2_IO19 | MUX_PAD_CTRL(NO_PAD_CTRL), 663 /* IOEXP_IRQ# */ 664 MX6_PAD_EIM_A20__GPIO2_IO18 | MUX_PAD_CTRL(NO_PAD_CTRL), 665 666 /* MX6_LOCLED# */ 667 MX6_PAD_KEY_ROW4__GPIO4_IO15 | MUX_PAD_CTRL(NO_PAD_CTRL), 668 /* GPS_SHDN */ 669 MX6_PAD_ENET_RXD0__GPIO1_IO27 | MUX_PAD_CTRL(NO_PAD_CTRL), 670 /* VID_EN */ 671 MX6_PAD_EIM_D31__GPIO3_IO31 | MUX_PAD_CTRL(NO_PAD_CTRL), 672 /* PCI_RST# */ 673 MX6_PAD_ENET_TXD1__GPIO1_IO29 | MUX_PAD_CTRL(NO_PAD_CTRL), 674 }; 675 676 static iomux_v3_cfg_t const gw54xx_gpio_pads[] = { 677 /* PANLEDG# */ 678 MX6_PAD_KEY_COL0__GPIO4_IO06 | MUX_PAD_CTRL(NO_PAD_CTRL), 679 /* PANLEDR# */ 680 MX6_PAD_KEY_COL2__GPIO4_IO10 | MUX_PAD_CTRL(NO_PAD_CTRL), 681 /* MX6_LOCLED# */ 682 MX6_PAD_KEY_ROW4__GPIO4_IO15 | MUX_PAD_CTRL(NO_PAD_CTRL), 683 /* MIPI_DIO */ 684 MX6_PAD_SD1_DAT3__GPIO1_IO21 | MUX_PAD_CTRL(NO_PAD_CTRL), 685 /* RS485_EN */ 686 MX6_PAD_EIM_D24__GPIO3_IO24 | MUX_PAD_CTRL(NO_PAD_CTRL), 687 /* IOEXP_PWREN# */ 688 MX6_PAD_KEY_ROW0__GPIO4_IO07 | MUX_PAD_CTRL(NO_PAD_CTRL), 689 /* IOEXP_IRQ# */ 690 MX6_PAD_KEY_ROW1__GPIO4_IO09 | MUX_PAD_CTRL(NO_PAD_CTRL), 691 /* DIOI2C_DIS# */ 692 MX6_PAD_GPIO_19__GPIO4_IO05 | MUX_PAD_CTRL(NO_PAD_CTRL), 693 /* DIOI2C_DIS# */ 694 MX6_PAD_GPIO_19__GPIO4_IO05 | MUX_PAD_CTRL(NO_PAD_CTRL), 695 /* PCICK_SSON */ 696 MX6_PAD_SD1_CLK__GPIO1_IO20 | MUX_PAD_CTRL(NO_PAD_CTRL), 697 /* PCI_RST# */ 698 MX6_PAD_ENET_TXD1__GPIO1_IO29 | MUX_PAD_CTRL(NO_PAD_CTRL), 699 }; 700 701 /* 702 * each baseboard has 4 user configurable Digital IO lines which can 703 * be pinmuxed as a GPIO or in some cases a PWM 704 */ 705 struct dio_cfg { 706 iomux_v3_cfg_t gpio_padmux; 707 unsigned gpio_param; 708 iomux_v3_cfg_t pwm_padmux; 709 unsigned pwm_param; 710 }; 711 712 struct ventana { 713 /* pinmux */ 714 iomux_v3_cfg_t const *gpio_pads; 715 int num_pads; 716 /* DIO pinmux/val */ 717 struct dio_cfg dio_cfg[4]; 718 /* various gpios (0 if non-existent) */ 719 int leds[3]; 720 int pcie_rst; 721 int mezz_pwren; 722 int mezz_irq; 723 int rs485en; 724 int gps_shdn; 725 int vidin_en; 726 int dioi2c_en; 727 int pcie_sson; 728 int usb_sel; 729 }; 730 731 struct ventana gpio_cfg[] = { 732 /* GW5400proto */ 733 { 734 .gpio_pads = gw54xx_gpio_pads, 735 .num_pads = ARRAY_SIZE(gw54xx_gpio_pads), 736 .dio_cfg = { 737 { MX6_PAD_GPIO_9__GPIO1_IO09, IMX_GPIO_NR(1, 9), 738 MX6_PAD_GPIO_9__PWM1_OUT, 1 }, 739 { MX6_PAD_SD1_DAT2__GPIO1_IO19, IMX_GPIO_NR(1, 19), 740 MX6_PAD_SD1_DAT2__PWM2_OUT, 2 }, 741 { MX6_PAD_SD4_DAT1__GPIO2_IO09, IMX_GPIO_NR(2, 9), 742 MX6_PAD_SD4_DAT1__PWM3_OUT, 3 }, 743 { MX6_PAD_SD4_DAT2__GPIO2_IO10, IMX_GPIO_NR(2, 10), 744 MX6_PAD_SD4_DAT2__PWM4_OUT, 4 }, 745 }, 746 .leds = { 747 IMX_GPIO_NR(4, 6), 748 IMX_GPIO_NR(4, 10), 749 IMX_GPIO_NR(4, 15), 750 }, 751 .pcie_rst = IMX_GPIO_NR(1, 29), 752 .mezz_pwren = IMX_GPIO_NR(4, 7), 753 .mezz_irq = IMX_GPIO_NR(4, 9), 754 .rs485en = IMX_GPIO_NR(3, 24), 755 .dioi2c_en = IMX_GPIO_NR(4, 5), 756 .pcie_sson = IMX_GPIO_NR(1, 20), 757 }, 758 759 /* GW51xx */ 760 { 761 .gpio_pads = gw51xx_gpio_pads, 762 .num_pads = ARRAY_SIZE(gw51xx_gpio_pads), 763 .dio_cfg = { 764 { MX6_PAD_SD1_DAT0__GPIO1_IO16, IMX_GPIO_NR(1, 16), 765 0, 0 }, 766 { MX6_PAD_SD1_DAT2__GPIO1_IO19, IMX_GPIO_NR(1, 19), 767 MX6_PAD_SD1_DAT2__PWM2_OUT, 2 }, 768 { MX6_PAD_SD1_DAT1__GPIO1_IO17, IMX_GPIO_NR(1, 17), 769 MX6_PAD_SD1_DAT1__PWM3_OUT, 3 }, 770 { MX6_PAD_SD1_CMD__GPIO1_IO18, IMX_GPIO_NR(1, 18), 771 MX6_PAD_SD1_CMD__PWM4_OUT, 4 }, 772 }, 773 .leds = { 774 IMX_GPIO_NR(4, 6), 775 IMX_GPIO_NR(4, 10), 776 }, 777 .pcie_rst = IMX_GPIO_NR(1, 0), 778 .mezz_pwren = IMX_GPIO_NR(2, 19), 779 .mezz_irq = IMX_GPIO_NR(2, 18), 780 .gps_shdn = IMX_GPIO_NR(1, 2), 781 .vidin_en = IMX_GPIO_NR(5, 20), 782 }, 783 784 /* GW52xx */ 785 { 786 .gpio_pads = gw52xx_gpio_pads, 787 .num_pads = ARRAY_SIZE(gw52xx_gpio_pads), 788 .dio_cfg = { 789 { MX6_PAD_SD1_DAT0__GPIO1_IO16, IMX_GPIO_NR(1, 16), 790 0, 0 }, 791 { MX6_PAD_SD1_DAT2__GPIO1_IO19, IMX_GPIO_NR(1, 19), 792 MX6_PAD_SD1_DAT2__PWM2_OUT, 2 }, 793 { MX6_PAD_SD1_DAT1__GPIO1_IO17, IMX_GPIO_NR(1, 17), 794 MX6_PAD_SD1_DAT1__PWM3_OUT, 3 }, 795 { MX6_PAD_SD1_CLK__GPIO1_IO20, IMX_GPIO_NR(1, 20), 796 0, 0 }, 797 }, 798 .leds = { 799 IMX_GPIO_NR(4, 6), 800 IMX_GPIO_NR(4, 7), 801 IMX_GPIO_NR(4, 15), 802 }, 803 .pcie_rst = IMX_GPIO_NR(1, 29), 804 .mezz_pwren = IMX_GPIO_NR(2, 19), 805 .mezz_irq = IMX_GPIO_NR(2, 18), 806 .gps_shdn = IMX_GPIO_NR(1, 27), 807 .vidin_en = IMX_GPIO_NR(3, 31), 808 .usb_sel = IMX_GPIO_NR(1, 2), 809 }, 810 811 /* GW53xx */ 812 { 813 .gpio_pads = gw53xx_gpio_pads, 814 .num_pads = ARRAY_SIZE(gw53xx_gpio_pads), 815 .dio_cfg = { 816 { MX6_PAD_SD1_DAT0__GPIO1_IO16, IMX_GPIO_NR(1, 16), 817 0, 0 }, 818 { MX6_PAD_SD1_DAT2__GPIO1_IO19, IMX_GPIO_NR(1, 19), 819 MX6_PAD_SD1_DAT2__PWM2_OUT, 2 }, 820 { MX6_PAD_SD1_DAT1__GPIO1_IO17, IMX_GPIO_NR(1, 17), 821 MX6_PAD_SD1_DAT1__PWM3_OUT, 3 }, 822 { MX6_PAD_SD1_CLK__GPIO1_IO20, IMX_GPIO_NR(1, 20), 823 0, 0 }, 824 }, 825 .leds = { 826 IMX_GPIO_NR(4, 6), 827 IMX_GPIO_NR(4, 7), 828 IMX_GPIO_NR(4, 15), 829 }, 830 .pcie_rst = IMX_GPIO_NR(1, 29), 831 .mezz_pwren = IMX_GPIO_NR(2, 19), 832 .mezz_irq = IMX_GPIO_NR(2, 18), 833 .gps_shdn = IMX_GPIO_NR(1, 27), 834 .vidin_en = IMX_GPIO_NR(3, 31), 835 }, 836 837 /* GW54xx */ 838 { 839 .gpio_pads = gw54xx_gpio_pads, 840 .num_pads = ARRAY_SIZE(gw54xx_gpio_pads), 841 .dio_cfg = { 842 { MX6_PAD_GPIO_9__GPIO1_IO09, IMX_GPIO_NR(1, 9), 843 MX6_PAD_GPIO_9__PWM1_OUT, 1 }, 844 { MX6_PAD_SD1_DAT2__GPIO1_IO19, IMX_GPIO_NR(1, 19), 845 MX6_PAD_SD1_DAT2__PWM2_OUT, 2 }, 846 { MX6_PAD_SD4_DAT1__GPIO2_IO09, IMX_GPIO_NR(2, 9), 847 MX6_PAD_SD4_DAT1__PWM3_OUT, 3 }, 848 { MX6_PAD_SD4_DAT2__GPIO2_IO10, IMX_GPIO_NR(2, 10), 849 MX6_PAD_SD4_DAT2__PWM4_OUT, 4 }, 850 }, 851 .leds = { 852 IMX_GPIO_NR(4, 6), 853 IMX_GPIO_NR(4, 7), 854 IMX_GPIO_NR(4, 15), 855 }, 856 .pcie_rst = IMX_GPIO_NR(1, 29), 857 .mezz_pwren = IMX_GPIO_NR(2, 19), 858 .mezz_irq = IMX_GPIO_NR(2, 18), 859 .rs485en = IMX_GPIO_NR(7, 1), 860 .vidin_en = IMX_GPIO_NR(3, 31), 861 .dioi2c_en = IMX_GPIO_NR(4, 5), 862 .pcie_sson = IMX_GPIO_NR(1, 20), 863 }, 864 }; 865 866 /* setup board specific PMIC */ 867 int power_init_board(void) 868 { 869 struct pmic *p; 870 u32 reg; 871 872 /* configure PFUZE100 PMIC */ 873 if (board_type == GW54xx || board_type == GW54proto) { 874 power_pfuze100_init(I2C_PMIC); 875 p = pmic_get("PFUZE100_PMIC"); 876 if (p && !pmic_probe(p)) { 877 pmic_reg_read(p, PFUZE100_DEVICEID, ®); 878 printf("PMIC: PFUZE100 ID=0x%02x\n", reg); 879 880 /* Set VGEN1 to 1.5V and enable */ 881 pmic_reg_read(p, PFUZE100_VGEN1VOL, ®); 882 reg &= ~(LDO_VOL_MASK); 883 reg |= (LDOA_1_50V | LDO_EN); 884 pmic_reg_write(p, PFUZE100_VGEN1VOL, reg); 885 886 /* Set SWBST to 5.0V and enable */ 887 pmic_reg_read(p, PFUZE100_SWBSTCON1, ®); 888 reg &= ~(SWBST_MODE_MASK | SWBST_VOL_MASK); 889 reg |= (SWBST_5_00V | SWBST_MODE_AUTO); 890 pmic_reg_write(p, PFUZE100_SWBSTCON1, reg); 891 } 892 } 893 894 /* configure LTC3676 PMIC */ 895 else { 896 power_ltc3676_init(I2C_PMIC); 897 p = pmic_get("LTC3676_PMIC"); 898 if (p && !pmic_probe(p)) { 899 puts("PMIC: LTC3676\n"); 900 /* set board-specific scalar to 1225mV for IMX6Q@1GHz */ 901 if (is_cpu_type(MXC_CPU_MX6Q)) { 902 /* mask PGOOD during SW1 transition */ 903 reg = 0x1d | LTC3676_PGOOD_MASK; 904 pmic_reg_write(p, LTC3676_DVB1B, reg); 905 /* set SW1 (VDD_SOC) to 1259mV */ 906 reg = 0x1d; 907 pmic_reg_write(p, LTC3676_DVB1A, reg); 908 909 /* mask PGOOD during SW3 transition */ 910 reg = 0x1d | LTC3676_PGOOD_MASK; 911 pmic_reg_write(p, LTC3676_DVB3B, reg); 912 /*set SW3 (VDD_ARM) to 1259mV */ 913 reg = 0x1d; 914 pmic_reg_write(p, LTC3676_DVB3A, reg); 915 } 916 } 917 } 918 919 return 0; 920 } 921 922 /* setup GPIO pinmux and default configuration per baseboard */ 923 static void setup_board_gpio(int board) 924 { 925 struct ventana_board_info *info = &ventana_info; 926 const char *s; 927 char arg[10]; 928 size_t len; 929 int i; 930 int quiet = simple_strtol(getenv("quiet"), NULL, 10); 931 932 if (board >= GW_UNKNOWN) 933 return; 934 935 /* RS232_EN# */ 936 gpio_direction_output(GP_RS232_EN, (hwconfig("rs232")) ? 0 : 1); 937 938 /* MSATA Enable */ 939 if (is_cpu_type(MXC_CPU_MX6Q) && 940 test_bit(EECONFIG_SATA, info->config)) { 941 gpio_direction_output(GP_MSATA_SEL, 942 (hwconfig("msata")) ? 1 : 0); 943 } else { 944 gpio_direction_output(GP_MSATA_SEL, 0); 945 } 946 947 /* 948 * assert PCI_RST# (released by OS when clock is valid) 949 * TODO: figure out why leaving this de-asserted from PCI scan on boot 950 * causes linux pcie driver to hang during enumeration 951 */ 952 gpio_direction_output(gpio_cfg[board].pcie_rst, 0); 953 954 /* turn off (active-high) user LED's */ 955 for (i = 0; i < 4; i++) { 956 if (gpio_cfg[board].leds[i]) 957 gpio_direction_output(gpio_cfg[board].leds[i], 1); 958 } 959 960 /* Expansion Mezzanine IO */ 961 gpio_direction_output(gpio_cfg[board].mezz_pwren, 0); 962 gpio_direction_input(gpio_cfg[board].mezz_irq); 963 964 /* RS485 Transmit Enable */ 965 if (gpio_cfg[board].rs485en) 966 gpio_direction_output(gpio_cfg[board].rs485en, 0); 967 968 /* GPS_SHDN */ 969 if (gpio_cfg[board].gps_shdn) 970 gpio_direction_output(gpio_cfg[board].gps_shdn, 1); 971 972 /* Analog video codec power enable */ 973 if (gpio_cfg[board].vidin_en) 974 gpio_direction_output(gpio_cfg[board].vidin_en, 1); 975 976 /* DIOI2C_DIS# */ 977 if (gpio_cfg[board].dioi2c_en) 978 gpio_direction_output(gpio_cfg[board].dioi2c_en, 0); 979 980 /* PCICK_SSON: disable spread-spectrum clock */ 981 if (gpio_cfg[board].pcie_sson) 982 gpio_direction_output(gpio_cfg[board].pcie_sson, 0); 983 984 /* USBOTG Select (PCISKT or FrontPanel) */ 985 if (gpio_cfg[board].usb_sel) 986 gpio_direction_output(gpio_cfg[board].usb_sel, 0); 987 988 /* 989 * Configure DIO pinmux/padctl registers 990 * see IMX6DQRM/IMX6SDLRM IOMUXC_SW_PAD_CTL_PAD_* register definitions 991 */ 992 for (i = 0; i < 4; i++) { 993 struct dio_cfg *cfg = &gpio_cfg[board].dio_cfg[i]; 994 unsigned ctrl = DIO_PAD_CTRL; 995 996 sprintf(arg, "dio%d", i); 997 if (!hwconfig(arg)) 998 continue; 999 s = hwconfig_subarg(arg, "padctrl", &len); 1000 if (s) 1001 ctrl = simple_strtoul(s, NULL, 16) & 0x3ffff; 1002 if (hwconfig_subarg_cmp(arg, "mode", "gpio")) { 1003 if (!quiet) { 1004 printf("DIO%d: GPIO%d_IO%02d (gpio-%d)\n", i, 1005 (cfg->gpio_param/32)+1, 1006 cfg->gpio_param%32, 1007 cfg->gpio_param); 1008 } 1009 imx_iomux_v3_setup_pad(cfg->gpio_padmux | 1010 MUX_PAD_CTRL(ctrl)); 1011 gpio_direction_input(cfg->gpio_param); 1012 } else if (hwconfig_subarg_cmp("dio2", "mode", "pwm") && 1013 cfg->pwm_padmux) { 1014 if (!quiet) 1015 printf("DIO%d: pwm%d\n", i, cfg->pwm_param); 1016 imx_iomux_v3_setup_pad(cfg->pwm_padmux | 1017 MUX_PAD_CTRL(ctrl)); 1018 } 1019 } 1020 1021 if (!quiet) { 1022 if (is_cpu_type(MXC_CPU_MX6Q) && 1023 (test_bit(EECONFIG_SATA, info->config))) { 1024 printf("MSATA: %s\n", (hwconfig("msata") ? 1025 "enabled" : "disabled")); 1026 } 1027 printf("RS232: %s\n", (hwconfig("rs232")) ? 1028 "enabled" : "disabled"); 1029 } 1030 } 1031 1032 #if defined(CONFIG_CMD_PCI) 1033 int imx6_pcie_toggle_reset(void) 1034 { 1035 if (board_type < GW_UNKNOWN) { 1036 gpio_direction_output(gpio_cfg[board_type].pcie_rst, 0); 1037 mdelay(50); 1038 gpio_direction_output(gpio_cfg[board_type].pcie_rst, 1); 1039 } 1040 return 0; 1041 } 1042 #endif /* CONFIG_CMD_PCI */ 1043 1044 #ifdef CONFIG_SERIAL_TAG 1045 /* 1046 * called when setting up ATAGS before booting kernel 1047 * populate serialnum from the following (in order of priority): 1048 * serial# env var 1049 * eeprom 1050 */ 1051 void get_board_serial(struct tag_serialnr *serialnr) 1052 { 1053 char *serial = getenv("serial#"); 1054 1055 if (serial) { 1056 serialnr->high = 0; 1057 serialnr->low = simple_strtoul(serial, NULL, 10); 1058 } else if (ventana_info.model[0]) { 1059 serialnr->high = 0; 1060 serialnr->low = ventana_info.serial; 1061 } else { 1062 serialnr->high = 0; 1063 serialnr->low = 0; 1064 } 1065 } 1066 #endif 1067 1068 /* 1069 * Board Support 1070 */ 1071 1072 int board_early_init_f(void) 1073 { 1074 setup_iomux_uart(); 1075 gpio_direction_output(GP_USB_OTG_PWR, 0); /* OTG power off */ 1076 1077 #if defined(CONFIG_VIDEO_IPUV3) 1078 setup_display(); 1079 #endif 1080 return 0; 1081 } 1082 1083 int dram_init(void) 1084 { 1085 gd->ram_size = get_ram_size((void *)PHYS_SDRAM, 1086 CONFIG_DDR_MB*1024*1024); 1087 1088 return 0; 1089 } 1090 1091 int board_init(void) 1092 { 1093 struct iomuxc_base_regs *const iomuxc_regs 1094 = (struct iomuxc_base_regs *)IOMUXC_BASE_ADDR; 1095 1096 clrsetbits_le32(&iomuxc_regs->gpr[1], 1097 IOMUXC_GPR1_OTG_ID_MASK, 1098 IOMUXC_GPR1_OTG_ID_GPIO1); 1099 1100 /* address of linux boot parameters */ 1101 gd->bd->bi_boot_params = PHYS_SDRAM + 0x100; 1102 1103 #ifdef CONFIG_CMD_NAND 1104 setup_gpmi_nand(); 1105 #endif 1106 #ifdef CONFIG_MXC_SPI 1107 setup_spi(); 1108 #endif 1109 setup_i2c(0, CONFIG_SYS_I2C_SPEED, 0x7f, &i2c_pad_info0); 1110 setup_i2c(1, CONFIG_SYS_I2C_SPEED, 0x7f, &i2c_pad_info1); 1111 setup_i2c(2, CONFIG_SYS_I2C_SPEED, 0x7f, &i2c_pad_info2); 1112 1113 #ifdef CONFIG_CMD_SATA 1114 setup_sata(); 1115 #endif 1116 /* read Gateworks EEPROM into global struct (used later) */ 1117 board_type = read_eeprom(); 1118 1119 /* board-specifc GPIO iomux */ 1120 if (board_type < GW_UNKNOWN) { 1121 imx_iomux_v3_setup_multiple_pads(gw_gpio_pads, 1122 ARRAY_SIZE(gw_gpio_pads)); 1123 imx_iomux_v3_setup_multiple_pads(gpio_cfg[board_type].gpio_pads, 1124 gpio_cfg[board_type].num_pads); 1125 } 1126 1127 return 0; 1128 } 1129 1130 #if defined(CONFIG_DISPLAY_BOARDINFO_LATE) 1131 /* 1132 * called during late init (after relocation and after board_init()) 1133 * by virtue of CONFIG_DISPLAY_BOARDINFO_LATE as we needed i2c initialized and 1134 * EEPROM read. 1135 */ 1136 int checkboard(void) 1137 { 1138 struct ventana_board_info *info = &ventana_info; 1139 unsigned char buf[4]; 1140 const char *p; 1141 int quiet; /* Quiet or minimal output mode */ 1142 1143 quiet = 0; 1144 p = getenv("quiet"); 1145 if (p) 1146 quiet = simple_strtol(p, NULL, 10); 1147 else 1148 setenv("quiet", "0"); 1149 1150 puts("\nGateworks Corporation Copyright 2014\n"); 1151 if (info->model[0]) { 1152 printf("Model: %s\n", info->model); 1153 printf("MFGDate: %02x-%02x-%02x%02x\n", 1154 info->mfgdate[0], info->mfgdate[1], 1155 info->mfgdate[2], info->mfgdate[3]); 1156 printf("Serial:%d\n", info->serial); 1157 } else { 1158 puts("Invalid EEPROM - board will not function fully\n"); 1159 } 1160 if (quiet) 1161 return 0; 1162 1163 /* Display GSC firmware revision/CRC/status */ 1164 i2c_set_bus_num(I2C_GSC); 1165 if (!gsc_i2c_read(GSC_SC_ADDR, GSC_SC_FWVER, 1, buf, 1)) { 1166 printf("GSC: v%d", buf[0]); 1167 if (!gsc_i2c_read(GSC_SC_ADDR, GSC_SC_STATUS, 1, buf, 4)) { 1168 printf(" 0x%04x", buf[2] | buf[3]<<8); /* CRC */ 1169 printf(" 0x%02x", buf[0]); /* irq status */ 1170 } 1171 puts("\n"); 1172 } 1173 /* Display RTC */ 1174 if (!gsc_i2c_read(GSC_RTC_ADDR, 0x00, 1, buf, 4)) { 1175 printf("RTC: %d\n", 1176 buf[0] | buf[1]<<8 | buf[2]<<16 | buf[3]<<24); 1177 } 1178 1179 return 0; 1180 } 1181 #endif 1182 1183 #ifdef CONFIG_CMD_BMODE 1184 /* 1185 * BOOT_CFG1, BOOT_CFG2, BOOT_CFG3, BOOT_CFG4 1186 * see Table 8-11 and Table 5-9 1187 * BOOT_CFG1[7] = 1 (boot from NAND) 1188 * BOOT_CFG1[5] = 0 - raw NAND 1189 * BOOT_CFG1[4] = 0 - default pad settings 1190 * BOOT_CFG1[3:2] = 00 - devices = 1 1191 * BOOT_CFG1[1:0] = 00 - Row Address Cycles = 3 1192 * BOOT_CFG2[4:3] = 00 - Boot Search Count = 2 1193 * BOOT_CFG2[2:1] = 01 - Pages In Block = 64 1194 * BOOT_CFG2[0] = 0 - Reset time 12ms 1195 */ 1196 static const struct boot_mode board_boot_modes[] = { 1197 /* NAND: 64pages per block, 3 row addr cycles, 2 copies of FCB/DBBT */ 1198 { "nand", MAKE_CFGVAL(0x80, 0x02, 0x00, 0x00) }, 1199 { NULL, 0 }, 1200 }; 1201 #endif 1202 1203 /* late init */ 1204 int misc_init_r(void) 1205 { 1206 struct ventana_board_info *info = &ventana_info; 1207 unsigned char reg; 1208 1209 /* set env vars based on EEPROM data */ 1210 if (ventana_info.model[0]) { 1211 char str[16], fdt[36]; 1212 char *p; 1213 const char *cputype = ""; 1214 int i; 1215 1216 /* 1217 * FDT name will be prefixed with CPU type. Three versions 1218 * will be created each increasingly generic and bootloader 1219 * env scripts will try loading each from most specific to 1220 * least. 1221 */ 1222 if (is_cpu_type(MXC_CPU_MX6Q)) 1223 cputype = "imx6q"; 1224 else if (is_cpu_type(MXC_CPU_MX6DL)) 1225 cputype = "imx6dl"; 1226 memset(str, 0, sizeof(str)); 1227 for (i = 0; i < (sizeof(str)-1) && info->model[i]; i++) 1228 str[i] = tolower(info->model[i]); 1229 if (!getenv("model")) 1230 setenv("model", str); 1231 if (!getenv("fdt_file")) { 1232 sprintf(fdt, "%s-%s.dtb", cputype, str); 1233 setenv("fdt_file", fdt); 1234 } 1235 p = strchr(str, '-'); 1236 if (p) { 1237 *p++ = 0; 1238 1239 setenv("model_base", str); 1240 if (!getenv("fdt_file1")) { 1241 sprintf(fdt, "%s-%s.dtb", cputype, str); 1242 setenv("fdt_file1", fdt); 1243 } 1244 str[4] = 'x'; 1245 str[5] = 'x'; 1246 str[6] = 0; 1247 if (!getenv("fdt_file2")) { 1248 sprintf(fdt, "%s-%s.dtb", cputype, str); 1249 setenv("fdt_file2", fdt); 1250 } 1251 } 1252 1253 /* initialize env from EEPROM */ 1254 if (test_bit(EECONFIG_ETH0, info->config) && 1255 !getenv("ethaddr")) { 1256 eth_setenv_enetaddr("ethaddr", info->mac0); 1257 } 1258 if (test_bit(EECONFIG_ETH1, info->config) && 1259 !getenv("eth1addr")) { 1260 eth_setenv_enetaddr("eth1addr", info->mac1); 1261 } 1262 1263 /* board serial-number */ 1264 sprintf(str, "%6d", info->serial); 1265 setenv("serial#", str); 1266 } 1267 1268 1269 /* setup baseboard specific GPIO pinmux and config */ 1270 setup_board_gpio(board_type); 1271 1272 #ifdef CONFIG_CMD_BMODE 1273 add_board_boot_modes(board_boot_modes); 1274 #endif 1275 1276 /* 1277 * The Gateworks System Controller implements a boot 1278 * watchdog (always enabled) as a workaround for IMX6 boot related 1279 * errata such as: 1280 * ERR005768 - no fix 1281 * ERR006282 - fixed in silicon r1.3 1282 * ERR007117 - fixed in silicon r1.3 1283 * ERR007220 - fixed in silicon r1.3 1284 * see http://cache.freescale.com/files/32bit/doc/errata/IMX6DQCE.pdf 1285 * 1286 * Disable the boot watchdog and display/clear the timeout flag if set 1287 */ 1288 i2c_set_bus_num(I2C_GSC); 1289 if (!gsc_i2c_read(GSC_SC_ADDR, GSC_SC_CTRL1, 1, ®, 1)) { 1290 reg |= (1 << GSC_SC_CTRL1_WDDIS); 1291 if (gsc_i2c_write(GSC_SC_ADDR, GSC_SC_CTRL1, 1, ®, 1)) 1292 puts("Error: could not disable GSC Watchdog\n"); 1293 } else { 1294 puts("Error: could not disable GSC Watchdog\n"); 1295 } 1296 if (!gsc_i2c_read(GSC_SC_ADDR, GSC_SC_STATUS, 1, ®, 1)) { 1297 if (reg & (1 << GSC_SC_IRQ_WATCHDOG)) { /* watchdog timeout */ 1298 puts("GSC boot watchdog timeout detected"); 1299 reg &= ~(1 << GSC_SC_IRQ_WATCHDOG); /* clear flag */ 1300 gsc_i2c_write(GSC_SC_ADDR, GSC_SC_STATUS, 1, ®, 1); 1301 } 1302 } 1303 1304 return 0; 1305 } 1306 1307 #if defined(CONFIG_OF_LIBFDT) && defined(CONFIG_OF_BOARD_SETUP) 1308 1309 /* FDT aliases associated with EEPROM config bits */ 1310 const char *fdt_aliases[] = { 1311 "ethernet0", 1312 "ethernet1", 1313 "hdmi_out", 1314 "ahci0", 1315 "pcie", 1316 "ssi0", 1317 "ssi1", 1318 "lcd0", 1319 "lvds0", 1320 "lvds1", 1321 "usb0", 1322 "usb1", 1323 "mmc0", 1324 "mmc1", 1325 "mmc2", 1326 "mmc3", 1327 "uart0", 1328 "uart1", 1329 "uart2", 1330 "uart3", 1331 "uart4", 1332 "ipu0", 1333 "ipu1", 1334 "can0", 1335 "mipi_dsi", 1336 "mipi_csi", 1337 "tzasc0", 1338 "tzasc1", 1339 "i2c0", 1340 "i2c1", 1341 "i2c2", 1342 "vpu", 1343 "csi0", 1344 "csi1", 1345 "caam", 1346 NULL, 1347 NULL, 1348 NULL, 1349 NULL, 1350 NULL, 1351 "spi0", 1352 "spi1", 1353 "spi2", 1354 "spi3", 1355 "spi4", 1356 "spi5", 1357 NULL, 1358 NULL, 1359 "pps", 1360 NULL, 1361 NULL, 1362 NULL, 1363 "hdmi_in", 1364 "cvbs_out", 1365 "cvbs_in", 1366 "nand", 1367 NULL, 1368 NULL, 1369 NULL, 1370 NULL, 1371 NULL, 1372 NULL, 1373 NULL, 1374 NULL, 1375 }; 1376 1377 /* 1378 * called prior to booting kernel or by 'fdt boardsetup' command 1379 * 1380 * unless 'fdt_noauto' env var is set we will update the following in the DTB: 1381 * - mtd partitions based on mtdparts/mtdids env 1382 * - system-serial (board serial num from EEPROM) 1383 * - board (full model from EEPROM) 1384 * - peripherals removed from DTB if not loaded on board (per EEPROM config) 1385 */ 1386 void ft_board_setup(void *blob, bd_t *bd) 1387 { 1388 int bit; 1389 struct ventana_board_info *info = &ventana_info; 1390 struct node_info nodes[] = { 1391 { "sst,w25q256", MTD_DEV_TYPE_NOR, }, /* SPI flash */ 1392 { "fsl,imx6q-gpmi-nand", MTD_DEV_TYPE_NAND, }, /* NAND flash */ 1393 }; 1394 const char *model = getenv("model"); 1395 1396 if (getenv("fdt_noauto")) { 1397 puts(" Skiping ft_board_setup (fdt_noauto defined)\n"); 1398 return; 1399 } 1400 1401 /* Update partition nodes using info from mtdparts env var */ 1402 puts(" Updating MTD partitions...\n"); 1403 fdt_fixup_mtdparts(blob, nodes, ARRAY_SIZE(nodes)); 1404 1405 if (!model) { 1406 puts("invalid board info: Leaving FDT fully enabled\n"); 1407 return; 1408 } 1409 printf(" Adjusting FDT per EEPROM for %s...\n", model); 1410 1411 /* board serial number */ 1412 fdt_setprop(blob, 0, "system-serial", getenv("serial#"), 1413 strlen(getenv("serial#")) + 1); 1414 1415 /* board (model contains model from device-tree) */ 1416 fdt_setprop(blob, 0, "board", info->model, 1417 strlen((const char *)info->model) + 1); 1418 1419 /* 1420 * Peripheral Config: 1421 * remove nodes by alias path if EEPROM config tells us the 1422 * peripheral is not loaded on the board. 1423 */ 1424 for (bit = 0; bit < 64; bit++) { 1425 if (!test_bit(bit, info->config)) 1426 fdt_del_node_and_alias(blob, fdt_aliases[bit]); 1427 } 1428 } 1429 #endif /* defined(CONFIG_OF_FLAT_TREE) && defined(CONFIG_OF_BOARD_SETUP) */ 1430 1431