1 /* 2 * Copyright (C) 2013 Gateworks Corporation 3 * 4 * Author: Tim Harvey <tharvey@gateworks.com> 5 * 6 * SPDX-License-Identifier: GPL-2.0+ 7 */ 8 9 #include <common.h> 10 #include <asm/io.h> 11 #include <asm/arch/clock.h> 12 #include <asm/arch/imx-regs.h> 13 #include <asm/arch/iomux.h> 14 #include <asm/arch/mx6-pins.h> 15 #include <asm/arch/mxc_hdmi.h> 16 #include <asm/arch/crm_regs.h> 17 #include <asm/arch/sys_proto.h> 18 #include <asm/gpio.h> 19 #include <asm/imx-common/iomux-v3.h> 20 #include <asm/imx-common/mxc_i2c.h> 21 #include <asm/imx-common/boot_mode.h> 22 #include <asm/imx-common/sata.h> 23 #include <asm/imx-common/video.h> 24 #include <jffs2/load_kernel.h> 25 #include <hwconfig.h> 26 #include <i2c.h> 27 #include <linux/ctype.h> 28 #include <fdt_support.h> 29 #include <fsl_esdhc.h> 30 #include <miiphy.h> 31 #include <mmc.h> 32 #include <mtd_node.h> 33 #include <netdev.h> 34 #include <pci.h> 35 #include <power/pmic.h> 36 #include <power/ltc3676_pmic.h> 37 #include <power/pfuze100_pmic.h> 38 #include <fdt_support.h> 39 #include <jffs2/load_kernel.h> 40 #include <spi_flash.h> 41 42 #include "gsc.h" 43 #include "ventana_eeprom.h" 44 45 DECLARE_GLOBAL_DATA_PTR; 46 47 /* GPIO's common to all baseboards */ 48 #define GP_PHY_RST IMX_GPIO_NR(1, 30) 49 #define GP_USB_OTG_PWR IMX_GPIO_NR(3, 22) 50 #define GP_SD3_CD IMX_GPIO_NR(7, 0) 51 #define GP_RS232_EN IMX_GPIO_NR(2, 11) 52 #define GP_MSATA_SEL IMX_GPIO_NR(2, 8) 53 54 #define UART_PAD_CTRL (PAD_CTL_PKE | PAD_CTL_PUE | \ 55 PAD_CTL_PUS_100K_UP | PAD_CTL_SPEED_MED | \ 56 PAD_CTL_DSE_40ohm | PAD_CTL_SRE_FAST | PAD_CTL_HYS) 57 58 #define USDHC_PAD_CTRL (PAD_CTL_PKE | PAD_CTL_PUE | \ 59 PAD_CTL_PUS_47K_UP | PAD_CTL_SPEED_LOW | \ 60 PAD_CTL_DSE_80ohm | PAD_CTL_SRE_FAST | PAD_CTL_HYS) 61 62 #define ENET_PAD_CTRL (PAD_CTL_PKE | PAD_CTL_PUE | \ 63 PAD_CTL_PUS_100K_UP | PAD_CTL_SPEED_MED | \ 64 PAD_CTL_DSE_40ohm | PAD_CTL_HYS) 65 66 #define SPI_PAD_CTRL (PAD_CTL_HYS | \ 67 PAD_CTL_PUS_100K_DOWN | PAD_CTL_SPEED_MED | \ 68 PAD_CTL_DSE_40ohm | PAD_CTL_SRE_FAST) 69 70 #define DIO_PAD_CTRL (PAD_CTL_PKE | PAD_CTL_PUE | \ 71 PAD_CTL_PUS_100K_UP | PAD_CTL_SPEED_MED | \ 72 PAD_CTL_DSE_34ohm | PAD_CTL_HYS | PAD_CTL_SRE_FAST) 73 74 #define I2C_PAD_CTRL (PAD_CTL_PUS_100K_UP | \ 75 PAD_CTL_SPEED_MED | PAD_CTL_DSE_40ohm | PAD_CTL_HYS | \ 76 PAD_CTL_ODE | PAD_CTL_SRE_FAST) 77 78 #define IRQ_PAD_CTRL (PAD_CTL_PKE | PAD_CTL_PUE | \ 79 PAD_CTL_PUS_100K_UP | PAD_CTL_SPEED_MED | \ 80 PAD_CTL_DSE_34ohm | PAD_CTL_HYS | PAD_CTL_SRE_FAST) 81 82 #define DIO_PAD_CFG (MUX_PAD_CTRL(DIO_PAD_CTRL) | MUX_MODE_SION) 83 84 85 /* 86 * EEPROM board info struct populated by read_eeprom so that we only have to 87 * read it once. 88 */ 89 struct ventana_board_info ventana_info; 90 91 int board_type; 92 93 /* UART1: Function varies per baseboard */ 94 iomux_v3_cfg_t const uart1_pads[] = { 95 IOMUX_PADS(PAD_SD3_DAT6__UART1_RX_DATA | MUX_PAD_CTRL(UART_PAD_CTRL)), 96 IOMUX_PADS(PAD_SD3_DAT7__UART1_TX_DATA | MUX_PAD_CTRL(UART_PAD_CTRL)), 97 }; 98 99 /* UART2: Serial Console */ 100 iomux_v3_cfg_t const uart2_pads[] = { 101 IOMUX_PADS(PAD_SD4_DAT7__UART2_TX_DATA | MUX_PAD_CTRL(UART_PAD_CTRL)), 102 IOMUX_PADS(PAD_SD4_DAT4__UART2_RX_DATA | MUX_PAD_CTRL(UART_PAD_CTRL)), 103 }; 104 105 #define PC MUX_PAD_CTRL(I2C_PAD_CTRL) 106 107 /* I2C1: GSC */ 108 struct i2c_pads_info mx6q_i2c_pad_info0 = { 109 .scl = { 110 .i2c_mode = MX6Q_PAD_EIM_D21__I2C1_SCL | PC, 111 .gpio_mode = MX6Q_PAD_EIM_D21__GPIO3_IO21 | PC, 112 .gp = IMX_GPIO_NR(3, 21) 113 }, 114 .sda = { 115 .i2c_mode = MX6Q_PAD_EIM_D28__I2C1_SDA | PC, 116 .gpio_mode = MX6Q_PAD_EIM_D28__GPIO3_IO28 | PC, 117 .gp = IMX_GPIO_NR(3, 28) 118 } 119 }; 120 struct i2c_pads_info mx6dl_i2c_pad_info0 = { 121 .scl = { 122 .i2c_mode = MX6DL_PAD_EIM_D21__I2C1_SCL | PC, 123 .gpio_mode = MX6DL_PAD_EIM_D21__GPIO3_IO21 | PC, 124 .gp = IMX_GPIO_NR(3, 21) 125 }, 126 .sda = { 127 .i2c_mode = MX6DL_PAD_EIM_D28__I2C1_SDA | PC, 128 .gpio_mode = MX6DL_PAD_EIM_D28__GPIO3_IO28 | PC, 129 .gp = IMX_GPIO_NR(3, 28) 130 } 131 }; 132 133 /* I2C2: PMIC/PCIe Switch/PCIe Clock/Mezz */ 134 struct i2c_pads_info mx6q_i2c_pad_info1 = { 135 .scl = { 136 .i2c_mode = MX6Q_PAD_KEY_COL3__I2C2_SCL | PC, 137 .gpio_mode = MX6Q_PAD_KEY_COL3__GPIO4_IO12 | PC, 138 .gp = IMX_GPIO_NR(4, 12) 139 }, 140 .sda = { 141 .i2c_mode = MX6Q_PAD_KEY_ROW3__I2C2_SDA | PC, 142 .gpio_mode = MX6Q_PAD_KEY_ROW3__GPIO4_IO13 | PC, 143 .gp = IMX_GPIO_NR(4, 13) 144 } 145 }; 146 struct i2c_pads_info mx6dl_i2c_pad_info1 = { 147 .scl = { 148 .i2c_mode = MX6DL_PAD_KEY_COL3__I2C2_SCL | PC, 149 .gpio_mode = MX6DL_PAD_KEY_COL3__GPIO4_IO12 | PC, 150 .gp = IMX_GPIO_NR(4, 12) 151 }, 152 .sda = { 153 .i2c_mode = MX6DL_PAD_KEY_ROW3__I2C2_SDA | PC, 154 .gpio_mode = MX6DL_PAD_KEY_ROW3__GPIO4_IO13 | PC, 155 .gp = IMX_GPIO_NR(4, 13) 156 } 157 }; 158 159 /* I2C3: Misc/Expansion */ 160 struct i2c_pads_info mx6q_i2c_pad_info2 = { 161 .scl = { 162 .i2c_mode = MX6Q_PAD_GPIO_3__I2C3_SCL | PC, 163 .gpio_mode = MX6Q_PAD_GPIO_3__GPIO1_IO03 | PC, 164 .gp = IMX_GPIO_NR(1, 3) 165 }, 166 .sda = { 167 .i2c_mode = MX6Q_PAD_GPIO_6__I2C3_SDA | PC, 168 .gpio_mode = MX6Q_PAD_GPIO_6__GPIO1_IO06 | PC, 169 .gp = IMX_GPIO_NR(1, 6) 170 } 171 }; 172 struct i2c_pads_info mx6dl_i2c_pad_info2 = { 173 .scl = { 174 .i2c_mode = MX6DL_PAD_GPIO_3__I2C3_SCL | PC, 175 .gpio_mode = MX6DL_PAD_GPIO_3__GPIO1_IO03 | PC, 176 .gp = IMX_GPIO_NR(1, 3) 177 }, 178 .sda = { 179 .i2c_mode = MX6DL_PAD_GPIO_6__I2C3_SDA | PC, 180 .gpio_mode = MX6DL_PAD_GPIO_6__GPIO1_IO06 | PC, 181 .gp = IMX_GPIO_NR(1, 6) 182 } 183 }; 184 185 /* MMC */ 186 iomux_v3_cfg_t const usdhc3_pads[] = { 187 IOMUX_PADS(PAD_SD3_CLK__SD3_CLK | MUX_PAD_CTRL(USDHC_PAD_CTRL)), 188 IOMUX_PADS(PAD_SD3_CMD__SD3_CMD | MUX_PAD_CTRL(USDHC_PAD_CTRL)), 189 IOMUX_PADS(PAD_SD3_DAT0__SD3_DATA0 | MUX_PAD_CTRL(USDHC_PAD_CTRL)), 190 IOMUX_PADS(PAD_SD3_DAT1__SD3_DATA1 | MUX_PAD_CTRL(USDHC_PAD_CTRL)), 191 IOMUX_PADS(PAD_SD3_DAT2__SD3_DATA2 | MUX_PAD_CTRL(USDHC_PAD_CTRL)), 192 IOMUX_PADS(PAD_SD3_DAT3__SD3_DATA3 | MUX_PAD_CTRL(USDHC_PAD_CTRL)), 193 /* CD */ 194 IOMUX_PADS(PAD_SD3_DAT5__GPIO7_IO00 | MUX_PAD_CTRL(IRQ_PAD_CTRL)), 195 }; 196 197 /* ENET */ 198 iomux_v3_cfg_t const enet_pads[] = { 199 IOMUX_PADS(PAD_ENET_MDIO__ENET_MDIO | MUX_PAD_CTRL(ENET_PAD_CTRL)), 200 IOMUX_PADS(PAD_ENET_MDC__ENET_MDC | MUX_PAD_CTRL(ENET_PAD_CTRL)), 201 IOMUX_PADS(PAD_RGMII_TXC__RGMII_TXC | MUX_PAD_CTRL(ENET_PAD_CTRL)), 202 IOMUX_PADS(PAD_RGMII_TD0__RGMII_TD0 | MUX_PAD_CTRL(ENET_PAD_CTRL)), 203 IOMUX_PADS(PAD_RGMII_TD1__RGMII_TD1 | MUX_PAD_CTRL(ENET_PAD_CTRL)), 204 IOMUX_PADS(PAD_RGMII_TD2__RGMII_TD2 | MUX_PAD_CTRL(ENET_PAD_CTRL)), 205 IOMUX_PADS(PAD_RGMII_TD3__RGMII_TD3 | MUX_PAD_CTRL(ENET_PAD_CTRL)), 206 IOMUX_PADS(PAD_RGMII_TX_CTL__RGMII_TX_CTL | 207 MUX_PAD_CTRL(ENET_PAD_CTRL)), 208 IOMUX_PADS(PAD_ENET_REF_CLK__ENET_TX_CLK | 209 MUX_PAD_CTRL(ENET_PAD_CTRL)), 210 IOMUX_PADS(PAD_RGMII_RXC__RGMII_RXC | MUX_PAD_CTRL(ENET_PAD_CTRL)), 211 IOMUX_PADS(PAD_RGMII_RD0__RGMII_RD0 | MUX_PAD_CTRL(ENET_PAD_CTRL)), 212 IOMUX_PADS(PAD_RGMII_RD1__RGMII_RD1 | MUX_PAD_CTRL(ENET_PAD_CTRL)), 213 IOMUX_PADS(PAD_RGMII_RD2__RGMII_RD2 | MUX_PAD_CTRL(ENET_PAD_CTRL)), 214 IOMUX_PADS(PAD_RGMII_RD3__RGMII_RD3 | MUX_PAD_CTRL(ENET_PAD_CTRL)), 215 IOMUX_PADS(PAD_RGMII_RX_CTL__RGMII_RX_CTL | 216 MUX_PAD_CTRL(ENET_PAD_CTRL)), 217 /* PHY nRST */ 218 IOMUX_PADS(PAD_ENET_TXD0__GPIO1_IO30 | DIO_PAD_CFG), 219 }; 220 221 /* NAND */ 222 iomux_v3_cfg_t const nfc_pads[] = { 223 IOMUX_PADS(PAD_NANDF_CLE__NAND_CLE | MUX_PAD_CTRL(NO_PAD_CTRL)), 224 IOMUX_PADS(PAD_NANDF_ALE__NAND_ALE | MUX_PAD_CTRL(NO_PAD_CTRL)), 225 IOMUX_PADS(PAD_NANDF_WP_B__NAND_WP_B | MUX_PAD_CTRL(NO_PAD_CTRL)), 226 IOMUX_PADS(PAD_NANDF_RB0__NAND_READY_B | MUX_PAD_CTRL(NO_PAD_CTRL)), 227 IOMUX_PADS(PAD_NANDF_CS0__NAND_CE0_B | MUX_PAD_CTRL(NO_PAD_CTRL)), 228 IOMUX_PADS(PAD_SD4_CMD__NAND_RE_B | MUX_PAD_CTRL(NO_PAD_CTRL)), 229 IOMUX_PADS(PAD_SD4_CLK__NAND_WE_B | MUX_PAD_CTRL(NO_PAD_CTRL)), 230 IOMUX_PADS(PAD_NANDF_D0__NAND_DATA00 | MUX_PAD_CTRL(NO_PAD_CTRL)), 231 IOMUX_PADS(PAD_NANDF_D1__NAND_DATA01 | MUX_PAD_CTRL(NO_PAD_CTRL)), 232 IOMUX_PADS(PAD_NANDF_D2__NAND_DATA02 | MUX_PAD_CTRL(NO_PAD_CTRL)), 233 IOMUX_PADS(PAD_NANDF_D3__NAND_DATA03 | MUX_PAD_CTRL(NO_PAD_CTRL)), 234 IOMUX_PADS(PAD_NANDF_D4__NAND_DATA04 | MUX_PAD_CTRL(NO_PAD_CTRL)), 235 IOMUX_PADS(PAD_NANDF_D5__NAND_DATA05 | MUX_PAD_CTRL(NO_PAD_CTRL)), 236 IOMUX_PADS(PAD_NANDF_D6__NAND_DATA06 | MUX_PAD_CTRL(NO_PAD_CTRL)), 237 IOMUX_PADS(PAD_NANDF_D7__NAND_DATA07 | MUX_PAD_CTRL(NO_PAD_CTRL)), 238 }; 239 240 #ifdef CONFIG_CMD_NAND 241 static void setup_gpmi_nand(void) 242 { 243 struct mxc_ccm_reg *mxc_ccm = (struct mxc_ccm_reg *)CCM_BASE_ADDR; 244 245 /* config gpmi nand iomux */ 246 SETUP_IOMUX_PADS(nfc_pads); 247 248 /* config gpmi and bch clock to 100 MHz */ 249 clrsetbits_le32(&mxc_ccm->cs2cdr, 250 MXC_CCM_CS2CDR_ENFC_CLK_PODF_MASK | 251 MXC_CCM_CS2CDR_ENFC_CLK_PRED_MASK | 252 MXC_CCM_CS2CDR_ENFC_CLK_SEL_MASK, 253 MXC_CCM_CS2CDR_ENFC_CLK_PODF(0) | 254 MXC_CCM_CS2CDR_ENFC_CLK_PRED(3) | 255 MXC_CCM_CS2CDR_ENFC_CLK_SEL(3)); 256 257 /* enable gpmi and bch clock gating */ 258 setbits_le32(&mxc_ccm->CCGR4, 259 MXC_CCM_CCGR4_RAWNAND_U_BCH_INPUT_APB_MASK | 260 MXC_CCM_CCGR4_RAWNAND_U_GPMI_BCH_INPUT_BCH_MASK | 261 MXC_CCM_CCGR4_RAWNAND_U_GPMI_BCH_INPUT_GPMI_IO_MASK | 262 MXC_CCM_CCGR4_RAWNAND_U_GPMI_INPUT_APB_MASK | 263 MXC_CCM_CCGR4_PL301_MX6QPER1_BCH_OFFSET); 264 265 /* enable apbh clock gating */ 266 setbits_le32(&mxc_ccm->CCGR0, MXC_CCM_CCGR0_APBHDMA_MASK); 267 } 268 #endif 269 270 static void setup_iomux_enet(void) 271 { 272 SETUP_IOMUX_PADS(enet_pads); 273 274 /* toggle PHY_RST# */ 275 gpio_direction_output(GP_PHY_RST, 0); 276 mdelay(2); 277 gpio_set_value(GP_PHY_RST, 1); 278 } 279 280 static void setup_iomux_uart(void) 281 { 282 SETUP_IOMUX_PADS(uart1_pads); 283 SETUP_IOMUX_PADS(uart2_pads); 284 } 285 286 #ifdef CONFIG_USB_EHCI_MX6 287 iomux_v3_cfg_t const usb_pads[] = { 288 IOMUX_PADS(PAD_GPIO_1__USB_OTG_ID | DIO_PAD_CFG), 289 IOMUX_PADS(PAD_KEY_COL4__USB_OTG_OC | DIO_PAD_CFG), 290 /* OTG PWR */ 291 IOMUX_PADS(PAD_EIM_D22__GPIO3_IO22 | DIO_PAD_CFG), 292 }; 293 294 int board_ehci_hcd_init(int port) 295 { 296 struct ventana_board_info *info = &ventana_info; 297 298 SETUP_IOMUX_PADS(usb_pads); 299 300 /* Reset USB HUB (present on GW54xx/GW53xx) */ 301 switch (info->model[3]) { 302 case '3': /* GW53xx */ 303 case '5': /* GW552x */ 304 SETUP_IOMUX_PAD(PAD_GPIO_9__GPIO1_IO09 | DIO_PAD_CFG); 305 gpio_direction_output(IMX_GPIO_NR(1, 9), 0); 306 mdelay(2); 307 gpio_set_value(IMX_GPIO_NR(1, 9), 1); 308 break; 309 case '4': /* GW54xx */ 310 SETUP_IOMUX_PAD(PAD_SD1_DAT0__GPIO1_IO16 | DIO_PAD_CFG); 311 gpio_direction_output(IMX_GPIO_NR(1, 16), 0); 312 mdelay(2); 313 gpio_set_value(IMX_GPIO_NR(1, 16), 1); 314 break; 315 } 316 317 return 0; 318 } 319 320 int board_ehci_power(int port, int on) 321 { 322 if (port) 323 return 0; 324 gpio_set_value(GP_USB_OTG_PWR, on); 325 return 0; 326 } 327 #endif /* CONFIG_USB_EHCI_MX6 */ 328 329 #ifdef CONFIG_FSL_ESDHC 330 struct fsl_esdhc_cfg usdhc_cfg = { USDHC3_BASE_ADDR }; 331 332 int board_mmc_getcd(struct mmc *mmc) 333 { 334 /* Card Detect */ 335 gpio_direction_input(GP_SD3_CD); 336 return !gpio_get_value(GP_SD3_CD); 337 } 338 339 int board_mmc_init(bd_t *bis) 340 { 341 /* Only one USDHC controller on Ventana */ 342 SETUP_IOMUX_PADS(usdhc3_pads); 343 usdhc_cfg.sdhc_clk = mxc_get_clock(MXC_ESDHC3_CLK); 344 usdhc_cfg.max_bus_width = 4; 345 346 return fsl_esdhc_initialize(bis, &usdhc_cfg); 347 } 348 #endif /* CONFIG_FSL_ESDHC */ 349 350 #ifdef CONFIG_MXC_SPI 351 iomux_v3_cfg_t const ecspi1_pads[] = { 352 /* SS1 */ 353 IOMUX_PADS(PAD_EIM_D19__GPIO3_IO19 | MUX_PAD_CTRL(SPI_PAD_CTRL)), 354 IOMUX_PADS(PAD_EIM_D17__ECSPI1_MISO | MUX_PAD_CTRL(SPI_PAD_CTRL)), 355 IOMUX_PADS(PAD_EIM_D18__ECSPI1_MOSI | MUX_PAD_CTRL(SPI_PAD_CTRL)), 356 IOMUX_PADS(PAD_EIM_D16__ECSPI1_SCLK | MUX_PAD_CTRL(SPI_PAD_CTRL)), 357 }; 358 359 static void setup_spi(void) 360 { 361 gpio_direction_output(CONFIG_SF_DEFAULT_CS, 1); 362 SETUP_IOMUX_PADS(ecspi1_pads); 363 } 364 #endif 365 366 /* configure eth0 PHY board-specific LED behavior */ 367 int board_phy_config(struct phy_device *phydev) 368 { 369 unsigned short val; 370 371 /* Marvel 88E1510 */ 372 if (phydev->phy_id == 0x1410dd1) { 373 /* 374 * Page 3, Register 16: LED[2:0] Function Control Register 375 * LED[0] (SPD:Amber) R16_3.3:0 to 0111: on-GbE link 376 * LED[1] (LNK:Green) R16_3.7:4 to 0001: on-link, blink-activity 377 */ 378 phy_write(phydev, MDIO_DEVAD_NONE, 22, 3); 379 val = phy_read(phydev, MDIO_DEVAD_NONE, 16); 380 val &= 0xff00; 381 val |= 0x0017; 382 phy_write(phydev, MDIO_DEVAD_NONE, 16, val); 383 phy_write(phydev, MDIO_DEVAD_NONE, 22, 0); 384 } 385 386 if (phydev->drv->config) 387 phydev->drv->config(phydev); 388 389 return 0; 390 } 391 392 int board_eth_init(bd_t *bis) 393 { 394 setup_iomux_enet(); 395 396 #ifdef CONFIG_FEC_MXC 397 if (board_type != GW552x) 398 cpu_eth_init(bis); 399 #endif 400 401 #ifdef CONFIG_CI_UDC 402 /* For otg ethernet*/ 403 usb_eth_initialize(bis); 404 #endif 405 406 return 0; 407 } 408 409 #if defined(CONFIG_VIDEO_IPUV3) 410 411 static void enable_hdmi(struct display_info_t const *dev) 412 { 413 imx_enable_hdmi_phy(); 414 } 415 416 static int detect_i2c(struct display_info_t const *dev) 417 { 418 return i2c_set_bus_num(dev->bus) == 0 && 419 i2c_probe(dev->addr) == 0; 420 } 421 422 static void enable_lvds(struct display_info_t const *dev) 423 { 424 struct iomuxc *iomux = (struct iomuxc *) 425 IOMUXC_BASE_ADDR; 426 427 /* set CH0 data width to 24bit (IOMUXC_GPR2:5 0=18bit, 1=24bit) */ 428 u32 reg = readl(&iomux->gpr[2]); 429 reg |= IOMUXC_GPR2_DATA_WIDTH_CH0_24BIT; 430 writel(reg, &iomux->gpr[2]); 431 432 /* Enable Backlight */ 433 SETUP_IOMUX_PAD(PAD_SD1_CMD__GPIO1_IO18 | DIO_PAD_CFG); 434 gpio_direction_output(IMX_GPIO_NR(1, 18), 1); 435 } 436 437 struct display_info_t const displays[] = {{ 438 /* HDMI Output */ 439 .bus = -1, 440 .addr = 0, 441 .pixfmt = IPU_PIX_FMT_RGB24, 442 .detect = detect_hdmi, 443 .enable = enable_hdmi, 444 .mode = { 445 .name = "HDMI", 446 .refresh = 60, 447 .xres = 1024, 448 .yres = 768, 449 .pixclock = 15385, 450 .left_margin = 220, 451 .right_margin = 40, 452 .upper_margin = 21, 453 .lower_margin = 7, 454 .hsync_len = 60, 455 .vsync_len = 10, 456 .sync = FB_SYNC_EXT, 457 .vmode = FB_VMODE_NONINTERLACED 458 } }, { 459 /* Freescale MXC-LVDS1: HannStar HSD100PXN1-A00 w/ egalx_ts cont */ 460 .bus = 2, 461 .addr = 0x4, 462 .pixfmt = IPU_PIX_FMT_LVDS666, 463 .detect = detect_i2c, 464 .enable = enable_lvds, 465 .mode = { 466 .name = "Hannstar-XGA", 467 .refresh = 60, 468 .xres = 1024, 469 .yres = 768, 470 .pixclock = 15385, 471 .left_margin = 220, 472 .right_margin = 40, 473 .upper_margin = 21, 474 .lower_margin = 7, 475 .hsync_len = 60, 476 .vsync_len = 10, 477 .sync = FB_SYNC_EXT, 478 .vmode = FB_VMODE_NONINTERLACED 479 } } }; 480 size_t display_count = ARRAY_SIZE(displays); 481 482 static void setup_display(void) 483 { 484 struct mxc_ccm_reg *mxc_ccm = (struct mxc_ccm_reg *)CCM_BASE_ADDR; 485 struct iomuxc *iomux = (struct iomuxc *)IOMUXC_BASE_ADDR; 486 int reg; 487 488 enable_ipu_clock(); 489 imx_setup_hdmi(); 490 /* Turn on LDB0,IPU,IPU DI0 clocks */ 491 reg = __raw_readl(&mxc_ccm->CCGR3); 492 reg |= MXC_CCM_CCGR3_LDB_DI0_MASK; 493 writel(reg, &mxc_ccm->CCGR3); 494 495 /* set LDB0, LDB1 clk select to 011/011 */ 496 reg = readl(&mxc_ccm->cs2cdr); 497 reg &= ~(MXC_CCM_CS2CDR_LDB_DI0_CLK_SEL_MASK 498 |MXC_CCM_CS2CDR_LDB_DI1_CLK_SEL_MASK); 499 reg |= (3<<MXC_CCM_CS2CDR_LDB_DI0_CLK_SEL_OFFSET) 500 |(3<<MXC_CCM_CS2CDR_LDB_DI1_CLK_SEL_OFFSET); 501 writel(reg, &mxc_ccm->cs2cdr); 502 503 reg = readl(&mxc_ccm->cscmr2); 504 reg |= MXC_CCM_CSCMR2_LDB_DI0_IPU_DIV; 505 writel(reg, &mxc_ccm->cscmr2); 506 507 reg = readl(&mxc_ccm->chsccdr); 508 reg |= (CHSCCDR_CLK_SEL_LDB_DI0 509 <<MXC_CCM_CHSCCDR_IPU1_DI0_CLK_SEL_OFFSET); 510 writel(reg, &mxc_ccm->chsccdr); 511 512 reg = IOMUXC_GPR2_BGREF_RRMODE_EXTERNAL_RES 513 |IOMUXC_GPR2_DI1_VS_POLARITY_ACTIVE_HIGH 514 |IOMUXC_GPR2_DI0_VS_POLARITY_ACTIVE_LOW 515 |IOMUXC_GPR2_BIT_MAPPING_CH1_SPWG 516 |IOMUXC_GPR2_DATA_WIDTH_CH1_18BIT 517 |IOMUXC_GPR2_BIT_MAPPING_CH0_SPWG 518 |IOMUXC_GPR2_DATA_WIDTH_CH0_18BIT 519 |IOMUXC_GPR2_LVDS_CH1_MODE_DISABLED 520 |IOMUXC_GPR2_LVDS_CH0_MODE_ENABLED_DI0; 521 writel(reg, &iomux->gpr[2]); 522 523 reg = readl(&iomux->gpr[3]); 524 reg = (reg & ~IOMUXC_GPR3_LVDS0_MUX_CTL_MASK) 525 | (IOMUXC_GPR3_MUX_SRC_IPU1_DI0 526 <<IOMUXC_GPR3_LVDS0_MUX_CTL_OFFSET); 527 writel(reg, &iomux->gpr[3]); 528 529 /* Backlight CABEN on LVDS connector */ 530 SETUP_IOMUX_PAD(PAD_SD2_CLK__GPIO1_IO10 | DIO_PAD_CFG); 531 gpio_direction_output(IMX_GPIO_NR(1, 10), 0); 532 } 533 #endif /* CONFIG_VIDEO_IPUV3 */ 534 535 /* 536 * Baseboard specific GPIO 537 */ 538 539 /* common to add baseboards */ 540 static iomux_v3_cfg_t const gw_gpio_pads[] = { 541 /* MSATA_EN */ 542 IOMUX_PADS(PAD_SD4_DAT0__GPIO2_IO08 | DIO_PAD_CFG), 543 /* RS232_EN# */ 544 IOMUX_PADS(PAD_SD4_DAT3__GPIO2_IO11 | DIO_PAD_CFG), 545 }; 546 547 /* prototype */ 548 static iomux_v3_cfg_t const gwproto_gpio_pads[] = { 549 /* PANLEDG# */ 550 IOMUX_PADS(PAD_KEY_COL0__GPIO4_IO06 | DIO_PAD_CFG), 551 /* PANLEDR# */ 552 IOMUX_PADS(PAD_KEY_ROW0__GPIO4_IO07 | DIO_PAD_CFG), 553 /* LOCLED# */ 554 IOMUX_PADS(PAD_KEY_ROW4__GPIO4_IO15 | DIO_PAD_CFG), 555 /* RS485_EN */ 556 IOMUX_PADS(PAD_SD3_DAT4__GPIO7_IO01 | DIO_PAD_CFG), 557 /* IOEXP_PWREN# */ 558 IOMUX_PADS(PAD_EIM_A19__GPIO2_IO19 | DIO_PAD_CFG), 559 /* IOEXP_IRQ# */ 560 IOMUX_PADS(PAD_EIM_A20__GPIO2_IO18 | MUX_PAD_CTRL(IRQ_PAD_CTRL)), 561 /* VID_EN */ 562 IOMUX_PADS(PAD_EIM_D31__GPIO3_IO31 | DIO_PAD_CFG), 563 /* DIOI2C_DIS# */ 564 IOMUX_PADS(PAD_GPIO_19__GPIO4_IO05 | DIO_PAD_CFG), 565 /* PCICK_SSON */ 566 IOMUX_PADS(PAD_SD1_CLK__GPIO1_IO20 | DIO_PAD_CFG), 567 /* PCI_RST# */ 568 IOMUX_PADS(PAD_ENET_TXD1__GPIO1_IO29 | DIO_PAD_CFG), 569 }; 570 571 static iomux_v3_cfg_t const gw51xx_gpio_pads[] = { 572 /* PANLEDG# */ 573 IOMUX_PADS(PAD_KEY_COL0__GPIO4_IO06 | DIO_PAD_CFG), 574 /* PANLEDR# */ 575 IOMUX_PADS(PAD_KEY_ROW0__GPIO4_IO07 | DIO_PAD_CFG), 576 /* IOEXP_PWREN# */ 577 IOMUX_PADS(PAD_EIM_A19__GPIO2_IO19 | DIO_PAD_CFG), 578 /* IOEXP_IRQ# */ 579 IOMUX_PADS(PAD_EIM_A20__GPIO2_IO18 | MUX_PAD_CTRL(IRQ_PAD_CTRL)), 580 581 /* GPS_SHDN */ 582 IOMUX_PADS(PAD_GPIO_2__GPIO1_IO02 | DIO_PAD_CFG), 583 /* VID_PWR */ 584 IOMUX_PADS(PAD_CSI0_DATA_EN__GPIO5_IO20 | DIO_PAD_CFG), 585 /* PCI_RST# */ 586 IOMUX_PADS(PAD_GPIO_0__GPIO1_IO00 | DIO_PAD_CFG), 587 /* PCIESKT_WDIS# */ 588 IOMUX_PADS(PAD_GPIO_17__GPIO7_IO12 | DIO_PAD_CFG), 589 }; 590 591 static iomux_v3_cfg_t const gw52xx_gpio_pads[] = { 592 /* PANLEDG# */ 593 IOMUX_PADS(PAD_KEY_COL0__GPIO4_IO06 | DIO_PAD_CFG), 594 /* PANLEDR# */ 595 IOMUX_PADS(PAD_KEY_ROW0__GPIO4_IO07 | DIO_PAD_CFG), 596 /* IOEXP_PWREN# */ 597 IOMUX_PADS(PAD_EIM_A19__GPIO2_IO19 | DIO_PAD_CFG), 598 /* IOEXP_IRQ# */ 599 IOMUX_PADS(PAD_EIM_A20__GPIO2_IO18 | MUX_PAD_CTRL(IRQ_PAD_CTRL)), 600 601 /* MX6_LOCLED# */ 602 IOMUX_PADS(PAD_KEY_ROW4__GPIO4_IO15 | DIO_PAD_CFG), 603 /* GPS_SHDN */ 604 IOMUX_PADS(PAD_ENET_RXD0__GPIO1_IO27 | DIO_PAD_CFG), 605 /* USBOTG_SEL */ 606 IOMUX_PADS(PAD_GPIO_2__GPIO1_IO02 | DIO_PAD_CFG), 607 /* VID_PWR */ 608 IOMUX_PADS(PAD_EIM_D31__GPIO3_IO31 | DIO_PAD_CFG), 609 /* PCI_RST# */ 610 IOMUX_PADS(PAD_ENET_TXD1__GPIO1_IO29 | DIO_PAD_CFG), 611 /* PCIESKT_WDIS# */ 612 IOMUX_PADS(PAD_GPIO_17__GPIO7_IO12 | DIO_PAD_CFG), 613 }; 614 615 static iomux_v3_cfg_t const gw53xx_gpio_pads[] = { 616 /* PANLEDG# */ 617 IOMUX_PADS(PAD_KEY_COL0__GPIO4_IO06 | DIO_PAD_CFG), 618 /* PANLEDR# */ 619 IOMUX_PADS(PAD_KEY_ROW0__GPIO4_IO07 | DIO_PAD_CFG), 620 /* MX6_LOCLED# */ 621 IOMUX_PADS(PAD_KEY_ROW4__GPIO4_IO15 | DIO_PAD_CFG), 622 /* IOEXP_PWREN# */ 623 IOMUX_PADS(PAD_EIM_A19__GPIO2_IO19 | DIO_PAD_CFG), 624 /* IOEXP_IRQ# */ 625 IOMUX_PADS(PAD_EIM_A20__GPIO2_IO18 | MUX_PAD_CTRL(IRQ_PAD_CTRL)), 626 /* DIOI2C_DIS# */ 627 IOMUX_PADS(PAD_GPIO_19__GPIO4_IO05 | DIO_PAD_CFG), 628 /* GPS_SHDN */ 629 IOMUX_PADS(PAD_ENET_RXD0__GPIO1_IO27 | DIO_PAD_CFG), 630 /* VID_EN */ 631 IOMUX_PADS(PAD_EIM_D31__GPIO3_IO31 | DIO_PAD_CFG), 632 /* PCI_RST# */ 633 IOMUX_PADS(PAD_ENET_TXD1__GPIO1_IO29 | DIO_PAD_CFG), 634 /* PCIESKT_WDIS# */ 635 IOMUX_PADS(PAD_GPIO_17__GPIO7_IO12 | DIO_PAD_CFG), 636 }; 637 638 static iomux_v3_cfg_t const gw54xx_gpio_pads[] = { 639 /* PANLEDG# */ 640 IOMUX_PADS(PAD_KEY_COL0__GPIO4_IO06 | DIO_PAD_CFG), 641 /* PANLEDR# */ 642 IOMUX_PADS(PAD_KEY_COL2__GPIO4_IO10 | DIO_PAD_CFG), 643 /* MX6_LOCLED# */ 644 IOMUX_PADS(PAD_KEY_ROW4__GPIO4_IO15 | DIO_PAD_CFG), 645 /* MIPI_DIO */ 646 IOMUX_PADS(PAD_SD1_DAT3__GPIO1_IO21 | DIO_PAD_CFG), 647 /* RS485_EN */ 648 IOMUX_PADS(PAD_EIM_D24__GPIO3_IO24 | DIO_PAD_CFG), 649 /* IOEXP_PWREN# */ 650 IOMUX_PADS(PAD_KEY_ROW0__GPIO4_IO07 | DIO_PAD_CFG), 651 /* IOEXP_IRQ# */ 652 IOMUX_PADS(PAD_KEY_ROW1__GPIO4_IO09 | MUX_PAD_CTRL(IRQ_PAD_CTRL)), 653 /* DIOI2C_DIS# */ 654 IOMUX_PADS(PAD_GPIO_19__GPIO4_IO05 | DIO_PAD_CFG), 655 /* PCICK_SSON */ 656 IOMUX_PADS(PAD_SD1_CLK__GPIO1_IO20 | DIO_PAD_CFG), 657 /* PCI_RST# */ 658 IOMUX_PADS(PAD_ENET_TXD1__GPIO1_IO29 | DIO_PAD_CFG), 659 /* VID_EN */ 660 IOMUX_PADS(PAD_EIM_D31__GPIO3_IO31 | DIO_PAD_CFG), 661 /* PCIESKT_WDIS# */ 662 IOMUX_PADS(PAD_DISP0_DAT23__GPIO5_IO17 | DIO_PAD_CFG), 663 }; 664 665 static iomux_v3_cfg_t const gw552x_gpio_pads[] = { 666 /* PANLEDG# */ 667 IOMUX_PADS(PAD_KEY_COL0__GPIO4_IO06 | DIO_PAD_CFG), 668 /* PANLEDR# */ 669 IOMUX_PADS(PAD_KEY_ROW0__GPIO4_IO07 | DIO_PAD_CFG), 670 /* MX6_LOCLED# */ 671 IOMUX_PADS(PAD_KEY_ROW4__GPIO4_IO15 | DIO_PAD_CFG), 672 /* PCI_RST# */ 673 IOMUX_PADS(PAD_ENET_TXD1__GPIO1_IO29 | DIO_PAD_CFG), 674 /* MX6_DIO[4:9] */ 675 IOMUX_PADS(PAD_CSI0_PIXCLK__GPIO5_IO18 | DIO_PAD_CFG), 676 IOMUX_PADS(PAD_CSI0_DATA_EN__GPIO5_IO20 | DIO_PAD_CFG), 677 IOMUX_PADS(PAD_CSI0_VSYNC__GPIO5_IO21 | DIO_PAD_CFG), 678 IOMUX_PADS(PAD_CSI0_DAT4__GPIO5_IO22 | DIO_PAD_CFG), 679 IOMUX_PADS(PAD_CSI0_DAT5__GPIO5_IO23 | DIO_PAD_CFG), 680 IOMUX_PADS(PAD_CSI0_DAT7__GPIO5_IO25 | DIO_PAD_CFG), 681 /* PCIEGBE1_OFF# */ 682 IOMUX_PADS(PAD_GPIO_1__GPIO1_IO01 | DIO_PAD_CFG), 683 /* PCIEGBE2_OFF# */ 684 IOMUX_PADS(PAD_GPIO_2__GPIO1_IO02 | DIO_PAD_CFG), 685 /* PCIESKT_WDIS# */ 686 IOMUX_PADS(PAD_GPIO_17__GPIO7_IO12 | DIO_PAD_CFG), 687 }; 688 689 /* 690 * each baseboard has 4 user configurable Digital IO lines which can 691 * be pinmuxed as a GPIO or in some cases a PWM 692 */ 693 struct dio_cfg { 694 iomux_v3_cfg_t gpio_padmux[2]; 695 unsigned gpio_param; 696 iomux_v3_cfg_t pwm_padmux[2]; 697 unsigned pwm_param; 698 }; 699 700 struct ventana { 701 /* pinmux */ 702 iomux_v3_cfg_t const *gpio_pads; 703 int num_pads; 704 /* DIO pinmux/val */ 705 struct dio_cfg dio_cfg[4]; 706 /* various gpios (0 if non-existent) */ 707 int leds[3]; 708 int pcie_rst; 709 int mezz_pwren; 710 int mezz_irq; 711 int rs485en; 712 int gps_shdn; 713 int vidin_en; 714 int dioi2c_en; 715 int pcie_sson; 716 int usb_sel; 717 int wdis; 718 }; 719 720 struct ventana gpio_cfg[] = { 721 /* GW5400proto */ 722 { 723 .gpio_pads = gw54xx_gpio_pads, 724 .num_pads = ARRAY_SIZE(gw54xx_gpio_pads)/2, 725 .dio_cfg = { 726 { 727 { IOMUX_PADS(PAD_GPIO_9__GPIO1_IO09) }, 728 IMX_GPIO_NR(1, 9), 729 { IOMUX_PADS(PAD_GPIO_9__PWM1_OUT) }, 730 1 731 }, 732 { 733 { IOMUX_PADS(PAD_SD1_DAT2__GPIO1_IO19) }, 734 IMX_GPIO_NR(1, 19), 735 { IOMUX_PADS(PAD_SD1_DAT2__PWM2_OUT) }, 736 2 737 }, 738 { 739 { IOMUX_PADS(PAD_SD4_DAT1__GPIO2_IO09) }, 740 IMX_GPIO_NR(2, 9), 741 { IOMUX_PADS(PAD_SD4_DAT1__PWM3_OUT) }, 742 3 743 }, 744 { 745 { IOMUX_PADS(PAD_SD4_DAT2__GPIO2_IO10) }, 746 IMX_GPIO_NR(2, 10), 747 { IOMUX_PADS(PAD_SD4_DAT2__PWM4_OUT) }, 748 4 749 }, 750 }, 751 .leds = { 752 IMX_GPIO_NR(4, 6), 753 IMX_GPIO_NR(4, 10), 754 IMX_GPIO_NR(4, 15), 755 }, 756 .pcie_rst = IMX_GPIO_NR(1, 29), 757 .mezz_pwren = IMX_GPIO_NR(4, 7), 758 .mezz_irq = IMX_GPIO_NR(4, 9), 759 .rs485en = IMX_GPIO_NR(3, 24), 760 .dioi2c_en = IMX_GPIO_NR(4, 5), 761 .pcie_sson = IMX_GPIO_NR(1, 20), 762 }, 763 764 /* GW51xx */ 765 { 766 .gpio_pads = gw51xx_gpio_pads, 767 .num_pads = ARRAY_SIZE(gw51xx_gpio_pads)/2, 768 .dio_cfg = { 769 { 770 { IOMUX_PADS(PAD_SD1_DAT0__GPIO1_IO16) }, 771 IMX_GPIO_NR(1, 16), 772 { 0, 0 }, 773 0 774 }, 775 { 776 { IOMUX_PADS(PAD_SD1_DAT2__GPIO1_IO19) }, 777 IMX_GPIO_NR(1, 19), 778 { IOMUX_PADS(PAD_SD1_DAT2__PWM2_OUT) }, 779 2 780 }, 781 { 782 { IOMUX_PADS(PAD_SD1_DAT1__GPIO1_IO17) }, 783 IMX_GPIO_NR(1, 17), 784 { IOMUX_PADS(PAD_SD1_DAT1__PWM3_OUT) }, 785 3 786 }, 787 { 788 { IOMUX_PADS(PAD_SD1_CMD__GPIO1_IO18) }, 789 IMX_GPIO_NR(1, 18), 790 { IOMUX_PADS(PAD_SD1_CMD__PWM4_OUT) }, 791 4 792 }, 793 }, 794 .leds = { 795 IMX_GPIO_NR(4, 6), 796 IMX_GPIO_NR(4, 10), 797 }, 798 .pcie_rst = IMX_GPIO_NR(1, 0), 799 .mezz_pwren = IMX_GPIO_NR(2, 19), 800 .mezz_irq = IMX_GPIO_NR(2, 18), 801 .gps_shdn = IMX_GPIO_NR(1, 2), 802 .vidin_en = IMX_GPIO_NR(5, 20), 803 .wdis = IMX_GPIO_NR(7, 12), 804 }, 805 806 /* GW52xx */ 807 { 808 .gpio_pads = gw52xx_gpio_pads, 809 .num_pads = ARRAY_SIZE(gw52xx_gpio_pads)/2, 810 .dio_cfg = { 811 { 812 { IOMUX_PADS(PAD_SD1_DAT0__GPIO1_IO16) }, 813 IMX_GPIO_NR(1, 16), 814 { 0, 0 }, 815 0 816 }, 817 { 818 { IOMUX_PADS(PAD_SD1_DAT2__GPIO1_IO19) }, 819 IMX_GPIO_NR(1, 19), 820 { IOMUX_PADS(PAD_SD1_DAT2__PWM2_OUT) }, 821 2 822 }, 823 { 824 { IOMUX_PADS(PAD_SD1_DAT1__GPIO1_IO17) }, 825 IMX_GPIO_NR(1, 17), 826 { IOMUX_PADS(PAD_SD1_DAT1__PWM3_OUT) }, 827 3 828 }, 829 { 830 { IOMUX_PADS(PAD_SD1_CLK__GPIO1_IO20) }, 831 IMX_GPIO_NR(1, 20), 832 { 0, 0 }, 833 0 834 }, 835 }, 836 .leds = { 837 IMX_GPIO_NR(4, 6), 838 IMX_GPIO_NR(4, 7), 839 IMX_GPIO_NR(4, 15), 840 }, 841 .pcie_rst = IMX_GPIO_NR(1, 29), 842 .mezz_pwren = IMX_GPIO_NR(2, 19), 843 .mezz_irq = IMX_GPIO_NR(2, 18), 844 .gps_shdn = IMX_GPIO_NR(1, 27), 845 .vidin_en = IMX_GPIO_NR(3, 31), 846 .usb_sel = IMX_GPIO_NR(1, 2), 847 .wdis = IMX_GPIO_NR(7, 12), 848 }, 849 850 /* GW53xx */ 851 { 852 .gpio_pads = gw53xx_gpio_pads, 853 .num_pads = ARRAY_SIZE(gw53xx_gpio_pads)/2, 854 .dio_cfg = { 855 { 856 { IOMUX_PADS(PAD_SD1_DAT0__GPIO1_IO16) }, 857 IMX_GPIO_NR(1, 16), 858 { 0, 0 }, 859 0 860 }, 861 { 862 { IOMUX_PADS(PAD_SD1_DAT2__GPIO1_IO19) }, 863 IMX_GPIO_NR(1, 19), 864 { IOMUX_PADS(PAD_SD1_DAT2__PWM2_OUT) }, 865 2 866 }, 867 { 868 { IOMUX_PADS(PAD_SD1_DAT1__GPIO1_IO17) }, 869 IMX_GPIO_NR(1, 17), 870 { IOMUX_PADS(PAD_SD1_DAT1__PWM3_OUT) }, 871 3 872 }, 873 { 874 {IOMUX_PADS(PAD_SD1_CLK__GPIO1_IO20) }, 875 IMX_GPIO_NR(1, 20), 876 { 0, 0 }, 877 0 878 }, 879 }, 880 .leds = { 881 IMX_GPIO_NR(4, 6), 882 IMX_GPIO_NR(4, 7), 883 IMX_GPIO_NR(4, 15), 884 }, 885 .pcie_rst = IMX_GPIO_NR(1, 29), 886 .mezz_pwren = IMX_GPIO_NR(2, 19), 887 .mezz_irq = IMX_GPIO_NR(2, 18), 888 .gps_shdn = IMX_GPIO_NR(1, 27), 889 .vidin_en = IMX_GPIO_NR(3, 31), 890 .wdis = IMX_GPIO_NR(7, 12), 891 }, 892 893 /* GW54xx */ 894 { 895 .gpio_pads = gw54xx_gpio_pads, 896 .num_pads = ARRAY_SIZE(gw54xx_gpio_pads)/2, 897 .dio_cfg = { 898 { 899 { IOMUX_PADS(PAD_GPIO_9__GPIO1_IO09) }, 900 IMX_GPIO_NR(1, 9), 901 { IOMUX_PADS(PAD_GPIO_9__PWM1_OUT) }, 902 1 903 }, 904 { 905 { IOMUX_PADS(PAD_SD1_DAT2__GPIO1_IO19) }, 906 IMX_GPIO_NR(1, 19), 907 { IOMUX_PADS(PAD_SD1_DAT2__PWM2_OUT) }, 908 2 909 }, 910 { 911 { IOMUX_PADS(PAD_SD4_DAT1__GPIO2_IO09) }, 912 IMX_GPIO_NR(2, 9), 913 { IOMUX_PADS(PAD_SD4_DAT1__PWM3_OUT) }, 914 3 915 }, 916 { 917 { IOMUX_PADS(PAD_SD4_DAT2__GPIO2_IO10) }, 918 IMX_GPIO_NR(2, 10), 919 { IOMUX_PADS(PAD_SD4_DAT2__PWM4_OUT) }, 920 4 921 }, 922 }, 923 .leds = { 924 IMX_GPIO_NR(4, 6), 925 IMX_GPIO_NR(4, 7), 926 IMX_GPIO_NR(4, 15), 927 }, 928 .pcie_rst = IMX_GPIO_NR(1, 29), 929 .mezz_pwren = IMX_GPIO_NR(2, 19), 930 .mezz_irq = IMX_GPIO_NR(2, 18), 931 .rs485en = IMX_GPIO_NR(7, 1), 932 .vidin_en = IMX_GPIO_NR(3, 31), 933 .dioi2c_en = IMX_GPIO_NR(4, 5), 934 .pcie_sson = IMX_GPIO_NR(1, 20), 935 .wdis = IMX_GPIO_NR(5, 17), 936 }, 937 938 /* GW552x */ 939 { 940 .gpio_pads = gw552x_gpio_pads, 941 .num_pads = ARRAY_SIZE(gw552x_gpio_pads)/2, 942 .dio_cfg = { 943 { 944 { IOMUX_PADS(PAD_SD1_DAT0__GPIO1_IO16) }, 945 IMX_GPIO_NR(1, 16), 946 { 0, 0 }, 947 0 948 }, 949 { 950 { IOMUX_PADS(PAD_SD1_DAT2__GPIO1_IO19) }, 951 IMX_GPIO_NR(1, 19), 952 { IOMUX_PADS(PAD_SD1_DAT2__PWM2_OUT) }, 953 2 954 }, 955 { 956 { IOMUX_PADS(PAD_SD1_DAT1__GPIO1_IO17) }, 957 IMX_GPIO_NR(1, 17), 958 { IOMUX_PADS(PAD_SD1_DAT1__PWM3_OUT) }, 959 3 960 }, 961 { 962 { IOMUX_PADS(PAD_SD1_CLK__GPIO1_IO20) }, 963 IMX_GPIO_NR(2, 10), 964 { 0, 0 }, 965 0 966 }, 967 }, 968 .leds = { 969 IMX_GPIO_NR(4, 6), 970 IMX_GPIO_NR(4, 7), 971 IMX_GPIO_NR(4, 15), 972 }, 973 .pcie_rst = IMX_GPIO_NR(1, 29), 974 }, 975 }; 976 977 /* setup board specific PMIC */ 978 int power_init_board(void) 979 { 980 struct pmic *p; 981 u32 reg; 982 983 /* configure PFUZE100 PMIC */ 984 if (board_type == GW54xx || board_type == GW54proto) { 985 power_pfuze100_init(CONFIG_I2C_PMIC); 986 p = pmic_get("PFUZE100"); 987 if (p && !pmic_probe(p)) { 988 pmic_reg_read(p, PFUZE100_DEVICEID, ®); 989 printf("PMIC: PFUZE100 ID=0x%02x\n", reg); 990 991 /* Set VGEN1 to 1.5V and enable */ 992 pmic_reg_read(p, PFUZE100_VGEN1VOL, ®); 993 reg &= ~(LDO_VOL_MASK); 994 reg |= (LDOA_1_50V | LDO_EN); 995 pmic_reg_write(p, PFUZE100_VGEN1VOL, reg); 996 997 /* Set SWBST to 5.0V and enable */ 998 pmic_reg_read(p, PFUZE100_SWBSTCON1, ®); 999 reg &= ~(SWBST_MODE_MASK | SWBST_VOL_MASK); 1000 reg |= (SWBST_5_00V | SWBST_MODE_AUTO); 1001 pmic_reg_write(p, PFUZE100_SWBSTCON1, reg); 1002 } 1003 } 1004 1005 /* configure LTC3676 PMIC */ 1006 else { 1007 power_ltc3676_init(CONFIG_I2C_PMIC); 1008 p = pmic_get("LTC3676_PMIC"); 1009 if (p && !pmic_probe(p)) { 1010 puts("PMIC: LTC3676\n"); 1011 /* set board-specific scalar to 1225mV for IMX6Q@1GHz */ 1012 if (is_cpu_type(MXC_CPU_MX6Q)) { 1013 /* mask PGOOD during SW1 transition */ 1014 reg = 0x1d | LTC3676_PGOOD_MASK; 1015 pmic_reg_write(p, LTC3676_DVB1B, reg); 1016 /* set SW1 (VDD_SOC) to 1259mV */ 1017 reg = 0x1d; 1018 pmic_reg_write(p, LTC3676_DVB1A, reg); 1019 1020 /* mask PGOOD during SW3 transition */ 1021 reg = 0x1d | LTC3676_PGOOD_MASK; 1022 pmic_reg_write(p, LTC3676_DVB3B, reg); 1023 /*set SW3 (VDD_ARM) to 1259mV */ 1024 reg = 0x1d; 1025 pmic_reg_write(p, LTC3676_DVB3A, reg); 1026 } 1027 } 1028 } 1029 1030 return 0; 1031 } 1032 1033 /* setup GPIO pinmux and default configuration per baseboard */ 1034 static void setup_board_gpio(int board) 1035 { 1036 struct ventana_board_info *info = &ventana_info; 1037 const char *s; 1038 char arg[10]; 1039 size_t len; 1040 int i; 1041 int quiet = simple_strtol(getenv("quiet"), NULL, 10); 1042 1043 if (board >= GW_UNKNOWN) 1044 return; 1045 1046 /* RS232_EN# */ 1047 gpio_direction_output(GP_RS232_EN, (hwconfig("rs232")) ? 0 : 1); 1048 1049 /* MSATA Enable */ 1050 if (is_cpu_type(MXC_CPU_MX6Q) && 1051 test_bit(EECONFIG_SATA, info->config)) { 1052 gpio_direction_output(GP_MSATA_SEL, 1053 (hwconfig("msata")) ? 1 : 0); 1054 } else { 1055 gpio_direction_output(GP_MSATA_SEL, 0); 1056 } 1057 1058 #if !defined(CONFIG_CMD_PCI) 1059 /* assert PCI_RST# (released by OS when clock is valid) */ 1060 gpio_direction_output(gpio_cfg[board].pcie_rst, 0); 1061 #endif 1062 1063 /* turn off (active-high) user LED's */ 1064 for (i = 0; i < ARRAY_SIZE(gpio_cfg[board].leds); i++) { 1065 if (gpio_cfg[board].leds[i]) 1066 gpio_direction_output(gpio_cfg[board].leds[i], 1); 1067 } 1068 1069 /* Expansion Mezzanine IO */ 1070 if (gpio_cfg[board].mezz_pwren) 1071 gpio_direction_output(gpio_cfg[board].mezz_pwren, 0); 1072 if (gpio_cfg[board].mezz_irq) 1073 gpio_direction_input(gpio_cfg[board].mezz_irq); 1074 1075 /* RS485 Transmit Enable */ 1076 if (gpio_cfg[board].rs485en) 1077 gpio_direction_output(gpio_cfg[board].rs485en, 0); 1078 1079 /* GPS_SHDN */ 1080 if (gpio_cfg[board].gps_shdn) 1081 gpio_direction_output(gpio_cfg[board].gps_shdn, 1); 1082 1083 /* Analog video codec power enable */ 1084 if (gpio_cfg[board].vidin_en) 1085 gpio_direction_output(gpio_cfg[board].vidin_en, 1); 1086 1087 /* DIOI2C_DIS# */ 1088 if (gpio_cfg[board].dioi2c_en) 1089 gpio_direction_output(gpio_cfg[board].dioi2c_en, 0); 1090 1091 /* PCICK_SSON: disable spread-spectrum clock */ 1092 if (gpio_cfg[board].pcie_sson) 1093 gpio_direction_output(gpio_cfg[board].pcie_sson, 0); 1094 1095 /* USBOTG Select (PCISKT or FrontPanel) */ 1096 if (gpio_cfg[board].usb_sel) 1097 gpio_direction_output(gpio_cfg[board].usb_sel, 0); 1098 1099 /* PCISKT_WDIS# (Wireless disable GPIO to miniPCIe sockets) */ 1100 if (gpio_cfg[board].wdis) 1101 gpio_direction_output(gpio_cfg[board].wdis, 1); 1102 1103 /* 1104 * Configure DIO pinmux/padctl registers 1105 * see IMX6DQRM/IMX6SDLRM IOMUXC_SW_PAD_CTL_PAD_* register definitions 1106 */ 1107 for (i = 0; i < 4; i++) { 1108 struct dio_cfg *cfg = &gpio_cfg[board].dio_cfg[i]; 1109 iomux_v3_cfg_t ctrl = DIO_PAD_CFG; 1110 unsigned cputype = is_cpu_type(MXC_CPU_MX6Q) ? 0 : 1; 1111 1112 sprintf(arg, "dio%d", i); 1113 if (!hwconfig(arg)) 1114 continue; 1115 s = hwconfig_subarg(arg, "padctrl", &len); 1116 if (s) { 1117 ctrl = MUX_PAD_CTRL(simple_strtoul(s, NULL, 16) 1118 & 0x1ffff) | MUX_MODE_SION; 1119 } 1120 if (hwconfig_subarg_cmp(arg, "mode", "gpio")) { 1121 if (!quiet) { 1122 printf("DIO%d: GPIO%d_IO%02d (gpio-%d)\n", i, 1123 (cfg->gpio_param/32)+1, 1124 cfg->gpio_param%32, 1125 cfg->gpio_param); 1126 } 1127 imx_iomux_v3_setup_pad(cfg->gpio_padmux[cputype] | 1128 ctrl); 1129 gpio_direction_input(cfg->gpio_param); 1130 } else if (hwconfig_subarg_cmp("dio2", "mode", "pwm") && 1131 cfg->pwm_padmux) { 1132 if (!quiet) 1133 printf("DIO%d: pwm%d\n", i, cfg->pwm_param); 1134 imx_iomux_v3_setup_pad(cfg->pwm_padmux[cputype] | 1135 MUX_PAD_CTRL(ctrl)); 1136 } 1137 } 1138 1139 if (!quiet) { 1140 if (is_cpu_type(MXC_CPU_MX6Q) && 1141 (test_bit(EECONFIG_SATA, info->config))) { 1142 printf("MSATA: %s\n", (hwconfig("msata") ? 1143 "enabled" : "disabled")); 1144 } 1145 printf("RS232: %s\n", (hwconfig("rs232")) ? 1146 "enabled" : "disabled"); 1147 } 1148 } 1149 1150 #if defined(CONFIG_CMD_PCI) 1151 int imx6_pcie_toggle_reset(void) 1152 { 1153 if (board_type < GW_UNKNOWN) { 1154 uint pin = gpio_cfg[board_type].pcie_rst; 1155 gpio_direction_output(pin, 0); 1156 mdelay(50); 1157 gpio_direction_output(pin, 1); 1158 } 1159 return 0; 1160 } 1161 1162 /* 1163 * Most Ventana boards have a PLX PEX860x PCIe switch onboard and use its 1164 * GPIO's as PERST# signals for its downstream ports - configure the GPIO's 1165 * properly and assert reset for 100ms. 1166 */ 1167 void board_pci_fixup_dev(struct pci_controller *hose, pci_dev_t dev, 1168 unsigned short vendor, unsigned short device, 1169 unsigned short class) 1170 { 1171 u32 dw; 1172 1173 debug("%s: %02d:%02d.%02d: %04x:%04x\n", __func__, 1174 PCI_BUS(dev), PCI_DEV(dev), PCI_FUNC(dev), vendor, device); 1175 if (vendor == PCI_VENDOR_ID_PLX && 1176 (device & 0xfff0) == 0x8600 && 1177 PCI_DEV(dev) == 0 && PCI_FUNC(dev) == 0) { 1178 debug("configuring PLX 860X downstream PERST#\n"); 1179 pci_hose_read_config_dword(hose, dev, 0x62c, &dw); 1180 dw |= 0xaaa8; /* GPIO1-7 outputs */ 1181 pci_hose_write_config_dword(hose, dev, 0x62c, dw); 1182 1183 pci_hose_read_config_dword(hose, dev, 0x644, &dw); 1184 dw |= 0xfe; /* GPIO1-7 output high */ 1185 pci_hose_write_config_dword(hose, dev, 0x644, dw); 1186 1187 mdelay(100); 1188 } 1189 } 1190 #endif /* CONFIG_CMD_PCI */ 1191 1192 #ifdef CONFIG_SERIAL_TAG 1193 /* 1194 * called when setting up ATAGS before booting kernel 1195 * populate serialnum from the following (in order of priority): 1196 * serial# env var 1197 * eeprom 1198 */ 1199 void get_board_serial(struct tag_serialnr *serialnr) 1200 { 1201 char *serial = getenv("serial#"); 1202 1203 if (serial) { 1204 serialnr->high = 0; 1205 serialnr->low = simple_strtoul(serial, NULL, 10); 1206 } else if (ventana_info.model[0]) { 1207 serialnr->high = 0; 1208 serialnr->low = ventana_info.serial; 1209 } else { 1210 serialnr->high = 0; 1211 serialnr->low = 0; 1212 } 1213 } 1214 #endif 1215 1216 /* 1217 * Board Support 1218 */ 1219 1220 /* called from SPL board_init_f() */ 1221 int board_early_init_f(void) 1222 { 1223 setup_iomux_uart(); 1224 gpio_direction_output(GP_USB_OTG_PWR, 0); /* OTG power off */ 1225 1226 #if defined(CONFIG_VIDEO_IPUV3) 1227 setup_display(); 1228 #endif 1229 return 0; 1230 } 1231 1232 int dram_init(void) 1233 { 1234 gd->ram_size = imx_ddr_size(); 1235 return 0; 1236 } 1237 1238 int board_init(void) 1239 { 1240 struct iomuxc *const iomuxc_regs = (struct iomuxc *)IOMUXC_BASE_ADDR; 1241 1242 clrsetbits_le32(&iomuxc_regs->gpr[1], 1243 IOMUXC_GPR1_OTG_ID_MASK, 1244 IOMUXC_GPR1_OTG_ID_GPIO1); 1245 1246 /* address of linux boot parameters */ 1247 gd->bd->bi_boot_params = PHYS_SDRAM + 0x100; 1248 1249 #ifdef CONFIG_CMD_NAND 1250 setup_gpmi_nand(); 1251 #endif 1252 #ifdef CONFIG_MXC_SPI 1253 setup_spi(); 1254 #endif 1255 if (is_cpu_type(MXC_CPU_MX6Q)) { 1256 setup_i2c(0, CONFIG_SYS_I2C_SPEED, 0x7f, &mx6q_i2c_pad_info0); 1257 setup_i2c(1, CONFIG_SYS_I2C_SPEED, 0x7f, &mx6q_i2c_pad_info1); 1258 setup_i2c(2, CONFIG_SYS_I2C_SPEED, 0x7f, &mx6q_i2c_pad_info2); 1259 } else { 1260 setup_i2c(0, CONFIG_SYS_I2C_SPEED, 0x7f, &mx6dl_i2c_pad_info0); 1261 setup_i2c(1, CONFIG_SYS_I2C_SPEED, 0x7f, &mx6dl_i2c_pad_info1); 1262 setup_i2c(2, CONFIG_SYS_I2C_SPEED, 0x7f, &mx6dl_i2c_pad_info2); 1263 } 1264 1265 #ifdef CONFIG_CMD_SATA 1266 setup_sata(); 1267 #endif 1268 /* read Gateworks EEPROM into global struct (used later) */ 1269 board_type = read_eeprom(CONFIG_I2C_GSC, &ventana_info); 1270 1271 /* board-specifc GPIO iomux */ 1272 SETUP_IOMUX_PADS(gw_gpio_pads); 1273 if (board_type < GW_UNKNOWN) { 1274 iomux_v3_cfg_t const *p = gpio_cfg[board_type].gpio_pads; 1275 int count = gpio_cfg[board_type].num_pads; 1276 1277 imx_iomux_v3_setup_multiple_pads(p, count); 1278 } 1279 1280 return 0; 1281 } 1282 1283 #if defined(CONFIG_DISPLAY_BOARDINFO_LATE) 1284 /* 1285 * called during late init (after relocation and after board_init()) 1286 * by virtue of CONFIG_DISPLAY_BOARDINFO_LATE as we needed i2c initialized and 1287 * EEPROM read. 1288 */ 1289 int checkboard(void) 1290 { 1291 struct ventana_board_info *info = &ventana_info; 1292 unsigned char buf[4]; 1293 const char *p; 1294 int quiet; /* Quiet or minimal output mode */ 1295 1296 quiet = 0; 1297 p = getenv("quiet"); 1298 if (p) 1299 quiet = simple_strtol(p, NULL, 10); 1300 else 1301 setenv("quiet", "0"); 1302 1303 puts("\nGateworks Corporation Copyright 2014\n"); 1304 if (info->model[0]) { 1305 printf("Model: %s\n", info->model); 1306 printf("MFGDate: %02x-%02x-%02x%02x\n", 1307 info->mfgdate[0], info->mfgdate[1], 1308 info->mfgdate[2], info->mfgdate[3]); 1309 printf("Serial:%d\n", info->serial); 1310 } else { 1311 puts("Invalid EEPROM - board will not function fully\n"); 1312 } 1313 if (quiet) 1314 return 0; 1315 1316 /* Display GSC firmware revision/CRC/status */ 1317 i2c_set_bus_num(CONFIG_I2C_GSC); 1318 if (!gsc_i2c_read(GSC_SC_ADDR, GSC_SC_FWVER, 1, buf, 1)) { 1319 printf("GSC: v%d", buf[0]); 1320 if (!gsc_i2c_read(GSC_SC_ADDR, GSC_SC_STATUS, 1, buf, 4)) { 1321 printf(" 0x%04x", buf[2] | buf[3]<<8); /* CRC */ 1322 printf(" 0x%02x", buf[0]); /* irq status */ 1323 } 1324 puts("\n"); 1325 } 1326 /* Display RTC */ 1327 if (!gsc_i2c_read(GSC_RTC_ADDR, 0x00, 1, buf, 4)) { 1328 printf("RTC: %d\n", 1329 buf[0] | buf[1]<<8 | buf[2]<<16 | buf[3]<<24); 1330 } 1331 1332 return 0; 1333 } 1334 #endif 1335 1336 #ifdef CONFIG_CMD_BMODE 1337 /* 1338 * BOOT_CFG1, BOOT_CFG2, BOOT_CFG3, BOOT_CFG4 1339 * see Table 8-11 and Table 5-9 1340 * BOOT_CFG1[7] = 1 (boot from NAND) 1341 * BOOT_CFG1[5] = 0 - raw NAND 1342 * BOOT_CFG1[4] = 0 - default pad settings 1343 * BOOT_CFG1[3:2] = 00 - devices = 1 1344 * BOOT_CFG1[1:0] = 00 - Row Address Cycles = 3 1345 * BOOT_CFG2[4:3] = 00 - Boot Search Count = 2 1346 * BOOT_CFG2[2:1] = 01 - Pages In Block = 64 1347 * BOOT_CFG2[0] = 0 - Reset time 12ms 1348 */ 1349 static const struct boot_mode board_boot_modes[] = { 1350 /* NAND: 64pages per block, 3 row addr cycles, 2 copies of FCB/DBBT */ 1351 { "nand", MAKE_CFGVAL(0x80, 0x02, 0x00, 0x00) }, 1352 { NULL, 0 }, 1353 }; 1354 #endif 1355 1356 /* late init */ 1357 int misc_init_r(void) 1358 { 1359 struct ventana_board_info *info = &ventana_info; 1360 unsigned char reg; 1361 1362 /* set env vars based on EEPROM data */ 1363 if (ventana_info.model[0]) { 1364 char str[16], fdt[36]; 1365 char *p; 1366 const char *cputype = ""; 1367 int i; 1368 1369 /* 1370 * FDT name will be prefixed with CPU type. Three versions 1371 * will be created each increasingly generic and bootloader 1372 * env scripts will try loading each from most specific to 1373 * least. 1374 */ 1375 if (is_cpu_type(MXC_CPU_MX6Q) || 1376 is_cpu_type(MXC_CPU_MX6D)) 1377 cputype = "imx6q"; 1378 else if (is_cpu_type(MXC_CPU_MX6DL) || 1379 is_cpu_type(MXC_CPU_MX6SOLO)) 1380 cputype = "imx6dl"; 1381 setenv("soctype", cputype); 1382 if (8 << (ventana_info.nand_flash_size-1) >= 2048) 1383 setenv("flash_layout", "large"); 1384 else 1385 setenv("flash_layout", "normal"); 1386 memset(str, 0, sizeof(str)); 1387 for (i = 0; i < (sizeof(str)-1) && info->model[i]; i++) 1388 str[i] = tolower(info->model[i]); 1389 if (!getenv("model")) 1390 setenv("model", str); 1391 if (!getenv("fdt_file")) { 1392 sprintf(fdt, "%s-%s.dtb", cputype, str); 1393 setenv("fdt_file", fdt); 1394 } 1395 p = strchr(str, '-'); 1396 if (p) { 1397 *p++ = 0; 1398 1399 setenv("model_base", str); 1400 if (!getenv("fdt_file1")) { 1401 sprintf(fdt, "%s-%s.dtb", cputype, str); 1402 setenv("fdt_file1", fdt); 1403 } 1404 if (board_type != GW552x) 1405 str[4] = 'x'; 1406 str[5] = 'x'; 1407 str[6] = 0; 1408 if (!getenv("fdt_file2")) { 1409 sprintf(fdt, "%s-%s.dtb", cputype, str); 1410 setenv("fdt_file2", fdt); 1411 } 1412 } 1413 1414 /* initialize env from EEPROM */ 1415 if (test_bit(EECONFIG_ETH0, info->config) && 1416 !getenv("ethaddr")) { 1417 eth_setenv_enetaddr("ethaddr", info->mac0); 1418 } 1419 if (test_bit(EECONFIG_ETH1, info->config) && 1420 !getenv("eth1addr")) { 1421 eth_setenv_enetaddr("eth1addr", info->mac1); 1422 } 1423 1424 /* board serial-number */ 1425 sprintf(str, "%6d", info->serial); 1426 setenv("serial#", str); 1427 } 1428 1429 1430 /* setup baseboard specific GPIO pinmux and config */ 1431 setup_board_gpio(board_type); 1432 1433 #ifdef CONFIG_CMD_BMODE 1434 add_board_boot_modes(board_boot_modes); 1435 #endif 1436 1437 /* 1438 * The Gateworks System Controller implements a boot 1439 * watchdog (always enabled) as a workaround for IMX6 boot related 1440 * errata such as: 1441 * ERR005768 - no fix scheduled 1442 * ERR006282 - fixed in silicon r1.2 1443 * ERR007117 - fixed in silicon r1.3 1444 * ERR007220 - fixed in silicon r1.3 1445 * ERR007926 - no fix scheduled 1446 * see http://cache.freescale.com/files/32bit/doc/errata/IMX6DQCE.pdf 1447 * 1448 * Disable the boot watchdog and display/clear the timeout flag if set 1449 */ 1450 i2c_set_bus_num(CONFIG_I2C_GSC); 1451 if (!gsc_i2c_read(GSC_SC_ADDR, GSC_SC_CTRL1, 1, ®, 1)) { 1452 reg |= (1 << GSC_SC_CTRL1_WDDIS); 1453 if (gsc_i2c_write(GSC_SC_ADDR, GSC_SC_CTRL1, 1, ®, 1)) 1454 puts("Error: could not disable GSC Watchdog\n"); 1455 } else { 1456 puts("Error: could not disable GSC Watchdog\n"); 1457 } 1458 if (!gsc_i2c_read(GSC_SC_ADDR, GSC_SC_STATUS, 1, ®, 1)) { 1459 if (reg & (1 << GSC_SC_IRQ_WATCHDOG)) { /* watchdog timeout */ 1460 puts("GSC boot watchdog timeout detected\n"); 1461 reg &= ~(1 << GSC_SC_IRQ_WATCHDOG); /* clear flag */ 1462 gsc_i2c_write(GSC_SC_ADDR, GSC_SC_STATUS, 1, ®, 1); 1463 } 1464 } 1465 1466 return 0; 1467 } 1468 1469 #if defined(CONFIG_OF_LIBFDT) && defined(CONFIG_OF_BOARD_SETUP) 1470 1471 /* 1472 * called prior to booting kernel or by 'fdt boardsetup' command 1473 * 1474 * unless 'fdt_noauto' env var is set we will update the following in the DTB: 1475 * - mtd partitions based on mtdparts/mtdids env 1476 * - system-serial (board serial num from EEPROM) 1477 * - board (full model from EEPROM) 1478 * - peripherals removed from DTB if not loaded on board (per EEPROM config) 1479 */ 1480 void ft_board_setup(void *blob, bd_t *bd) 1481 { 1482 struct ventana_board_info *info = &ventana_info; 1483 struct ventana_eeprom_config *cfg; 1484 struct node_info nodes[] = { 1485 { "sst,w25q256", MTD_DEV_TYPE_NOR, }, /* SPI flash */ 1486 { "fsl,imx6q-gpmi-nand", MTD_DEV_TYPE_NAND, }, /* NAND flash */ 1487 }; 1488 const char *model = getenv("model"); 1489 1490 if (getenv("fdt_noauto")) { 1491 puts(" Skiping ft_board_setup (fdt_noauto defined)\n"); 1492 return; 1493 } 1494 1495 /* Update partition nodes using info from mtdparts env var */ 1496 puts(" Updating MTD partitions...\n"); 1497 fdt_fixup_mtdparts(blob, nodes, ARRAY_SIZE(nodes)); 1498 1499 if (!model) { 1500 puts("invalid board info: Leaving FDT fully enabled\n"); 1501 return; 1502 } 1503 printf(" Adjusting FDT per EEPROM for %s...\n", model); 1504 1505 /* board serial number */ 1506 fdt_setprop(blob, 0, "system-serial", getenv("serial#"), 1507 strlen(getenv("serial#")) + 1); 1508 1509 /* board (model contains model from device-tree) */ 1510 fdt_setprop(blob, 0, "board", info->model, 1511 strlen((const char *)info->model) + 1); 1512 1513 /* 1514 * Peripheral Config: 1515 * remove nodes by alias path if EEPROM config tells us the 1516 * peripheral is not loaded on the board. 1517 */ 1518 if (getenv("fdt_noconfig")) { 1519 puts(" Skiping periperhal config (fdt_noconfig defined)\n"); 1520 return; 1521 } 1522 cfg = econfig; 1523 while (cfg->name) { 1524 if (!test_bit(cfg->bit, info->config)) { 1525 fdt_del_node_and_alias(blob, cfg->dtalias ? 1526 cfg->dtalias : cfg->name); 1527 } 1528 cfg++; 1529 } 1530 } 1531 #endif /* defined(CONFIG_OF_FLAT_TREE) && defined(CONFIG_OF_BOARD_SETUP) */ 1532 1533