1 /* 2 * Copyright (C) 2013 Gateworks Corporation 3 * 4 * Author: Tim Harvey <tharvey@gateworks.com> 5 * 6 * SPDX-License-Identifier: GPL-2.0+ 7 */ 8 9 #include <common.h> 10 #include <asm/arch/clock.h> 11 #include <asm/arch/crm_regs.h> 12 #include <asm/arch/iomux.h> 13 #include <asm/arch/mx6-pins.h> 14 #include <asm/arch/mxc_hdmi.h> 15 #include <asm/arch/sys_proto.h> 16 #include <asm/gpio.h> 17 #include <asm/imx-common/boot_mode.h> 18 #include <asm/imx-common/sata.h> 19 #include <asm/imx-common/spi.h> 20 #include <asm/imx-common/video.h> 21 #include <asm/io.h> 22 #include <dm.h> 23 #include <dm/platform_data/serial_mxc.h> 24 #include <i2c.h> 25 #include <fdt_support.h> 26 #include <fsl_esdhc.h> 27 #include <jffs2/load_kernel.h> 28 #include <linux/ctype.h> 29 #include <miiphy.h> 30 #include <mtd_node.h> 31 #include <netdev.h> 32 #include <pci.h> 33 #include <power/pmic.h> 34 #include <power/ltc3676_pmic.h> 35 #include <power/pfuze100_pmic.h> 36 #include <fdt_support.h> 37 #include <jffs2/load_kernel.h> 38 #include <spi_flash.h> 39 40 #include "gsc.h" 41 #include "common.h" 42 43 DECLARE_GLOBAL_DATA_PTR; 44 45 46 /* 47 * EEPROM board info struct populated by read_eeprom so that we only have to 48 * read it once. 49 */ 50 struct ventana_board_info ventana_info; 51 52 static int board_type; 53 54 /* MMC */ 55 static iomux_v3_cfg_t const usdhc3_pads[] = { 56 IOMUX_PADS(PAD_SD3_CLK__SD3_CLK | MUX_PAD_CTRL(USDHC_PAD_CTRL)), 57 IOMUX_PADS(PAD_SD3_CMD__SD3_CMD | MUX_PAD_CTRL(USDHC_PAD_CTRL)), 58 IOMUX_PADS(PAD_SD3_DAT0__SD3_DATA0 | MUX_PAD_CTRL(USDHC_PAD_CTRL)), 59 IOMUX_PADS(PAD_SD3_DAT1__SD3_DATA1 | MUX_PAD_CTRL(USDHC_PAD_CTRL)), 60 IOMUX_PADS(PAD_SD3_DAT2__SD3_DATA2 | MUX_PAD_CTRL(USDHC_PAD_CTRL)), 61 IOMUX_PADS(PAD_SD3_DAT3__SD3_DATA3 | MUX_PAD_CTRL(USDHC_PAD_CTRL)), 62 /* CD */ 63 IOMUX_PADS(PAD_SD3_DAT5__GPIO7_IO00 | MUX_PAD_CTRL(IRQ_PAD_CTRL)), 64 }; 65 66 /* ENET */ 67 static iomux_v3_cfg_t const enet_pads[] = { 68 IOMUX_PADS(PAD_ENET_MDIO__ENET_MDIO | MUX_PAD_CTRL(ENET_PAD_CTRL)), 69 IOMUX_PADS(PAD_ENET_MDC__ENET_MDC | MUX_PAD_CTRL(ENET_PAD_CTRL)), 70 IOMUX_PADS(PAD_RGMII_TXC__RGMII_TXC | MUX_PAD_CTRL(ENET_PAD_CTRL)), 71 IOMUX_PADS(PAD_RGMII_TD0__RGMII_TD0 | MUX_PAD_CTRL(ENET_PAD_CTRL)), 72 IOMUX_PADS(PAD_RGMII_TD1__RGMII_TD1 | MUX_PAD_CTRL(ENET_PAD_CTRL)), 73 IOMUX_PADS(PAD_RGMII_TD2__RGMII_TD2 | MUX_PAD_CTRL(ENET_PAD_CTRL)), 74 IOMUX_PADS(PAD_RGMII_TD3__RGMII_TD3 | MUX_PAD_CTRL(ENET_PAD_CTRL)), 75 IOMUX_PADS(PAD_RGMII_TX_CTL__RGMII_TX_CTL | 76 MUX_PAD_CTRL(ENET_PAD_CTRL)), 77 IOMUX_PADS(PAD_ENET_REF_CLK__ENET_TX_CLK | 78 MUX_PAD_CTRL(ENET_PAD_CTRL)), 79 IOMUX_PADS(PAD_RGMII_RXC__RGMII_RXC | MUX_PAD_CTRL(ENET_PAD_CTRL)), 80 IOMUX_PADS(PAD_RGMII_RD0__RGMII_RD0 | MUX_PAD_CTRL(ENET_PAD_CTRL)), 81 IOMUX_PADS(PAD_RGMII_RD1__RGMII_RD1 | MUX_PAD_CTRL(ENET_PAD_CTRL)), 82 IOMUX_PADS(PAD_RGMII_RD2__RGMII_RD2 | MUX_PAD_CTRL(ENET_PAD_CTRL)), 83 IOMUX_PADS(PAD_RGMII_RD3__RGMII_RD3 | MUX_PAD_CTRL(ENET_PAD_CTRL)), 84 IOMUX_PADS(PAD_RGMII_RX_CTL__RGMII_RX_CTL | 85 MUX_PAD_CTRL(ENET_PAD_CTRL)), 86 /* PHY nRST */ 87 IOMUX_PADS(PAD_ENET_TXD0__GPIO1_IO30 | DIO_PAD_CFG), 88 }; 89 90 /* NAND */ 91 static iomux_v3_cfg_t const nfc_pads[] = { 92 IOMUX_PADS(PAD_NANDF_CLE__NAND_CLE | MUX_PAD_CTRL(NO_PAD_CTRL)), 93 IOMUX_PADS(PAD_NANDF_ALE__NAND_ALE | MUX_PAD_CTRL(NO_PAD_CTRL)), 94 IOMUX_PADS(PAD_NANDF_WP_B__NAND_WP_B | MUX_PAD_CTRL(NO_PAD_CTRL)), 95 IOMUX_PADS(PAD_NANDF_RB0__NAND_READY_B | MUX_PAD_CTRL(NO_PAD_CTRL)), 96 IOMUX_PADS(PAD_NANDF_CS0__NAND_CE0_B | MUX_PAD_CTRL(NO_PAD_CTRL)), 97 IOMUX_PADS(PAD_SD4_CMD__NAND_RE_B | MUX_PAD_CTRL(NO_PAD_CTRL)), 98 IOMUX_PADS(PAD_SD4_CLK__NAND_WE_B | MUX_PAD_CTRL(NO_PAD_CTRL)), 99 IOMUX_PADS(PAD_NANDF_D0__NAND_DATA00 | MUX_PAD_CTRL(NO_PAD_CTRL)), 100 IOMUX_PADS(PAD_NANDF_D1__NAND_DATA01 | MUX_PAD_CTRL(NO_PAD_CTRL)), 101 IOMUX_PADS(PAD_NANDF_D2__NAND_DATA02 | MUX_PAD_CTRL(NO_PAD_CTRL)), 102 IOMUX_PADS(PAD_NANDF_D3__NAND_DATA03 | MUX_PAD_CTRL(NO_PAD_CTRL)), 103 IOMUX_PADS(PAD_NANDF_D4__NAND_DATA04 | MUX_PAD_CTRL(NO_PAD_CTRL)), 104 IOMUX_PADS(PAD_NANDF_D5__NAND_DATA05 | MUX_PAD_CTRL(NO_PAD_CTRL)), 105 IOMUX_PADS(PAD_NANDF_D6__NAND_DATA06 | MUX_PAD_CTRL(NO_PAD_CTRL)), 106 IOMUX_PADS(PAD_NANDF_D7__NAND_DATA07 | MUX_PAD_CTRL(NO_PAD_CTRL)), 107 }; 108 109 #ifdef CONFIG_CMD_NAND 110 static void setup_gpmi_nand(void) 111 { 112 struct mxc_ccm_reg *mxc_ccm = (struct mxc_ccm_reg *)CCM_BASE_ADDR; 113 114 /* config gpmi nand iomux */ 115 SETUP_IOMUX_PADS(nfc_pads); 116 117 /* config gpmi and bch clock to 100 MHz */ 118 clrsetbits_le32(&mxc_ccm->cs2cdr, 119 MXC_CCM_CS2CDR_ENFC_CLK_PODF_MASK | 120 MXC_CCM_CS2CDR_ENFC_CLK_PRED_MASK | 121 MXC_CCM_CS2CDR_ENFC_CLK_SEL_MASK, 122 MXC_CCM_CS2CDR_ENFC_CLK_PODF(0) | 123 MXC_CCM_CS2CDR_ENFC_CLK_PRED(3) | 124 MXC_CCM_CS2CDR_ENFC_CLK_SEL(3)); 125 126 /* enable gpmi and bch clock gating */ 127 setbits_le32(&mxc_ccm->CCGR4, 128 MXC_CCM_CCGR4_RAWNAND_U_BCH_INPUT_APB_MASK | 129 MXC_CCM_CCGR4_RAWNAND_U_GPMI_BCH_INPUT_BCH_MASK | 130 MXC_CCM_CCGR4_RAWNAND_U_GPMI_BCH_INPUT_GPMI_IO_MASK | 131 MXC_CCM_CCGR4_RAWNAND_U_GPMI_INPUT_APB_MASK | 132 MXC_CCM_CCGR4_PL301_MX6QPER1_BCH_OFFSET); 133 134 /* enable apbh clock gating */ 135 setbits_le32(&mxc_ccm->CCGR0, MXC_CCM_CCGR0_APBHDMA_MASK); 136 } 137 #endif 138 139 static void setup_iomux_enet(int gpio) 140 { 141 SETUP_IOMUX_PADS(enet_pads); 142 143 /* toggle PHY_RST# */ 144 gpio_request(gpio, "phy_rst#"); 145 gpio_direction_output(gpio, 0); 146 mdelay(2); 147 gpio_set_value(gpio, 1); 148 } 149 150 #ifdef CONFIG_USB_EHCI_MX6 151 static iomux_v3_cfg_t const usb_pads[] = { 152 IOMUX_PADS(PAD_GPIO_1__USB_OTG_ID | DIO_PAD_CFG), 153 IOMUX_PADS(PAD_KEY_COL4__USB_OTG_OC | DIO_PAD_CFG), 154 /* OTG PWR */ 155 IOMUX_PADS(PAD_EIM_D22__GPIO3_IO22 | DIO_PAD_CFG), 156 }; 157 158 int board_ehci_hcd_init(int port) 159 { 160 struct ventana_board_info *info = &ventana_info; 161 int gpio; 162 163 SETUP_IOMUX_PADS(usb_pads); 164 165 /* Reset USB HUB (present on GW54xx/GW53xx) */ 166 switch (info->model[3]) { 167 case '3': /* GW53xx */ 168 case '5': /* GW552x */ 169 SETUP_IOMUX_PAD(PAD_GPIO_9__GPIO1_IO09 | DIO_PAD_CFG); 170 gpio = (IMX_GPIO_NR(1, 9)); 171 break; 172 case '4': /* GW54xx */ 173 SETUP_IOMUX_PAD(PAD_SD1_DAT0__GPIO1_IO16 | DIO_PAD_CFG); 174 gpio = (IMX_GPIO_NR(1, 16)); 175 break; 176 default: 177 return 0; 178 } 179 180 /* request and toggle hub rst */ 181 gpio_request(gpio, "usb_hub_rst#"); 182 gpio_direction_output(gpio, 0); 183 mdelay(2); 184 gpio_set_value(gpio, 1); 185 186 return 0; 187 } 188 189 int board_ehci_power(int port, int on) 190 { 191 if (port) 192 return 0; 193 gpio_set_value(GP_USB_OTG_PWR, on); 194 return 0; 195 } 196 #endif /* CONFIG_USB_EHCI_MX6 */ 197 198 #ifdef CONFIG_FSL_ESDHC 199 static struct fsl_esdhc_cfg usdhc_cfg = { USDHC3_BASE_ADDR }; 200 201 int board_mmc_getcd(struct mmc *mmc) 202 { 203 /* Card Detect */ 204 gpio_request(GP_SD3_CD, "sd_cd"); 205 gpio_direction_input(GP_SD3_CD); 206 return !gpio_get_value(GP_SD3_CD); 207 } 208 209 int board_mmc_init(bd_t *bis) 210 { 211 /* Only one USDHC controller on Ventana */ 212 SETUP_IOMUX_PADS(usdhc3_pads); 213 usdhc_cfg.sdhc_clk = mxc_get_clock(MXC_ESDHC3_CLK); 214 usdhc_cfg.max_bus_width = 4; 215 216 return fsl_esdhc_initialize(bis, &usdhc_cfg); 217 } 218 #endif /* CONFIG_FSL_ESDHC */ 219 220 #ifdef CONFIG_MXC_SPI 221 iomux_v3_cfg_t const ecspi1_pads[] = { 222 /* SS1 */ 223 IOMUX_PADS(PAD_EIM_D19__GPIO3_IO19 | MUX_PAD_CTRL(SPI_PAD_CTRL)), 224 IOMUX_PADS(PAD_EIM_D17__ECSPI1_MISO | MUX_PAD_CTRL(SPI_PAD_CTRL)), 225 IOMUX_PADS(PAD_EIM_D18__ECSPI1_MOSI | MUX_PAD_CTRL(SPI_PAD_CTRL)), 226 IOMUX_PADS(PAD_EIM_D16__ECSPI1_SCLK | MUX_PAD_CTRL(SPI_PAD_CTRL)), 227 }; 228 229 int board_spi_cs_gpio(unsigned bus, unsigned cs) 230 { 231 return (bus == 0 && cs == 0) ? (IMX_GPIO_NR(3, 19)) : -1; 232 } 233 234 static void setup_spi(void) 235 { 236 gpio_request(IMX_GPIO_NR(3, 19), "spi_cs"); 237 gpio_direction_output(IMX_GPIO_NR(3, 19), 1); 238 SETUP_IOMUX_PADS(ecspi1_pads); 239 } 240 #endif 241 242 /* configure eth0 PHY board-specific LED behavior */ 243 int board_phy_config(struct phy_device *phydev) 244 { 245 unsigned short val; 246 247 /* Marvel 88E1510 */ 248 if (phydev->phy_id == 0x1410dd1) { 249 /* 250 * Page 3, Register 16: LED[2:0] Function Control Register 251 * LED[0] (SPD:Amber) R16_3.3:0 to 0111: on-GbE link 252 * LED[1] (LNK:Green) R16_3.7:4 to 0001: on-link, blink-activity 253 */ 254 phy_write(phydev, MDIO_DEVAD_NONE, 22, 3); 255 val = phy_read(phydev, MDIO_DEVAD_NONE, 16); 256 val &= 0xff00; 257 val |= 0x0017; 258 phy_write(phydev, MDIO_DEVAD_NONE, 16, val); 259 phy_write(phydev, MDIO_DEVAD_NONE, 22, 0); 260 } 261 262 if (phydev->drv->config) 263 phydev->drv->config(phydev); 264 265 return 0; 266 } 267 268 int board_eth_init(bd_t *bis) 269 { 270 #ifdef CONFIG_FEC_MXC 271 if (board_type != GW551x && board_type != GW552x) { 272 setup_iomux_enet(GP_PHY_RST); 273 cpu_eth_init(bis); 274 } 275 #endif 276 277 #ifdef CONFIG_E1000 278 e1000_initialize(bis); 279 #endif 280 281 #ifdef CONFIG_CI_UDC 282 /* For otg ethernet*/ 283 usb_eth_initialize(bis); 284 #endif 285 286 /* default to the first detected enet dev */ 287 if (!getenv("ethprime")) { 288 struct eth_device *dev = eth_get_dev_by_index(0); 289 if (dev) { 290 setenv("ethprime", dev->name); 291 printf("set ethprime to %s\n", getenv("ethprime")); 292 } 293 } 294 295 return 0; 296 } 297 298 #if defined(CONFIG_VIDEO_IPUV3) 299 300 static void enable_hdmi(struct display_info_t const *dev) 301 { 302 imx_enable_hdmi_phy(); 303 } 304 305 static int detect_i2c(struct display_info_t const *dev) 306 { 307 return i2c_set_bus_num(dev->bus) == 0 && 308 i2c_probe(dev->addr) == 0; 309 } 310 311 static void enable_lvds(struct display_info_t const *dev) 312 { 313 struct iomuxc *iomux = (struct iomuxc *) 314 IOMUXC_BASE_ADDR; 315 316 /* set CH0 data width to 24bit (IOMUXC_GPR2:5 0=18bit, 1=24bit) */ 317 u32 reg = readl(&iomux->gpr[2]); 318 reg |= IOMUXC_GPR2_DATA_WIDTH_CH0_24BIT; 319 writel(reg, &iomux->gpr[2]); 320 321 /* Enable Backlight */ 322 gpio_request(IMX_GPIO_NR(1, 18), "bklt_en"); 323 SETUP_IOMUX_PAD(PAD_SD1_CMD__GPIO1_IO18 | DIO_PAD_CFG); 324 gpio_direction_output(IMX_GPIO_NR(1, 18), 1); 325 } 326 327 struct display_info_t const displays[] = {{ 328 /* HDMI Output */ 329 .bus = -1, 330 .addr = 0, 331 .pixfmt = IPU_PIX_FMT_RGB24, 332 .detect = detect_hdmi, 333 .enable = enable_hdmi, 334 .mode = { 335 .name = "HDMI", 336 .refresh = 60, 337 .xres = 1024, 338 .yres = 768, 339 .pixclock = 15385, 340 .left_margin = 220, 341 .right_margin = 40, 342 .upper_margin = 21, 343 .lower_margin = 7, 344 .hsync_len = 60, 345 .vsync_len = 10, 346 .sync = FB_SYNC_EXT, 347 .vmode = FB_VMODE_NONINTERLACED 348 } }, { 349 /* Freescale MXC-LVDS1: HannStar HSD100PXN1-A00 w/ egalx_ts cont */ 350 .bus = 2, 351 .addr = 0x4, 352 .pixfmt = IPU_PIX_FMT_LVDS666, 353 .detect = detect_i2c, 354 .enable = enable_lvds, 355 .mode = { 356 .name = "Hannstar-XGA", 357 .refresh = 60, 358 .xres = 1024, 359 .yres = 768, 360 .pixclock = 15385, 361 .left_margin = 220, 362 .right_margin = 40, 363 .upper_margin = 21, 364 .lower_margin = 7, 365 .hsync_len = 60, 366 .vsync_len = 10, 367 .sync = FB_SYNC_EXT, 368 .vmode = FB_VMODE_NONINTERLACED 369 } }, { 370 /* DLC700JMG-T-4 */ 371 .bus = 0, 372 .addr = 0, 373 .detect = NULL, 374 .enable = enable_lvds, 375 .pixfmt = IPU_PIX_FMT_LVDS666, 376 .mode = { 377 .name = "DLC700JMGT4", 378 .refresh = 60, 379 .xres = 1024, /* 1024x600active pixels */ 380 .yres = 600, 381 .pixclock = 15385, /* 64MHz */ 382 .left_margin = 220, 383 .right_margin = 40, 384 .upper_margin = 21, 385 .lower_margin = 7, 386 .hsync_len = 60, 387 .vsync_len = 10, 388 .sync = FB_SYNC_EXT, 389 .vmode = FB_VMODE_NONINTERLACED 390 } }, { 391 /* DLC800FIG-T-3 */ 392 .bus = 0, 393 .addr = 0, 394 .detect = NULL, 395 .enable = enable_lvds, 396 .pixfmt = IPU_PIX_FMT_LVDS666, 397 .mode = { 398 .name = "DLC800FIGT3", 399 .refresh = 60, 400 .xres = 1024, /* 1024x768 active pixels */ 401 .yres = 768, 402 .pixclock = 15385, /* 64MHz */ 403 .left_margin = 220, 404 .right_margin = 40, 405 .upper_margin = 21, 406 .lower_margin = 7, 407 .hsync_len = 60, 408 .vsync_len = 10, 409 .sync = FB_SYNC_EXT, 410 .vmode = FB_VMODE_NONINTERLACED 411 } } }; 412 size_t display_count = ARRAY_SIZE(displays); 413 414 static void setup_display(void) 415 { 416 struct mxc_ccm_reg *mxc_ccm = (struct mxc_ccm_reg *)CCM_BASE_ADDR; 417 struct iomuxc *iomux = (struct iomuxc *)IOMUXC_BASE_ADDR; 418 int reg; 419 420 enable_ipu_clock(); 421 imx_setup_hdmi(); 422 /* Turn on LDB0,IPU,IPU DI0 clocks */ 423 reg = __raw_readl(&mxc_ccm->CCGR3); 424 reg |= MXC_CCM_CCGR3_LDB_DI0_MASK; 425 writel(reg, &mxc_ccm->CCGR3); 426 427 /* set LDB0, LDB1 clk select to 011/011 */ 428 reg = readl(&mxc_ccm->cs2cdr); 429 reg &= ~(MXC_CCM_CS2CDR_LDB_DI0_CLK_SEL_MASK 430 |MXC_CCM_CS2CDR_LDB_DI1_CLK_SEL_MASK); 431 reg |= (3<<MXC_CCM_CS2CDR_LDB_DI0_CLK_SEL_OFFSET) 432 |(3<<MXC_CCM_CS2CDR_LDB_DI1_CLK_SEL_OFFSET); 433 writel(reg, &mxc_ccm->cs2cdr); 434 435 reg = readl(&mxc_ccm->cscmr2); 436 reg |= MXC_CCM_CSCMR2_LDB_DI0_IPU_DIV; 437 writel(reg, &mxc_ccm->cscmr2); 438 439 reg = readl(&mxc_ccm->chsccdr); 440 reg |= (CHSCCDR_CLK_SEL_LDB_DI0 441 <<MXC_CCM_CHSCCDR_IPU1_DI0_CLK_SEL_OFFSET); 442 writel(reg, &mxc_ccm->chsccdr); 443 444 reg = IOMUXC_GPR2_BGREF_RRMODE_EXTERNAL_RES 445 |IOMUXC_GPR2_DI1_VS_POLARITY_ACTIVE_HIGH 446 |IOMUXC_GPR2_DI0_VS_POLARITY_ACTIVE_LOW 447 |IOMUXC_GPR2_BIT_MAPPING_CH1_SPWG 448 |IOMUXC_GPR2_DATA_WIDTH_CH1_18BIT 449 |IOMUXC_GPR2_BIT_MAPPING_CH0_SPWG 450 |IOMUXC_GPR2_DATA_WIDTH_CH0_18BIT 451 |IOMUXC_GPR2_LVDS_CH1_MODE_DISABLED 452 |IOMUXC_GPR2_LVDS_CH0_MODE_ENABLED_DI0; 453 writel(reg, &iomux->gpr[2]); 454 455 reg = readl(&iomux->gpr[3]); 456 reg = (reg & ~IOMUXC_GPR3_LVDS0_MUX_CTL_MASK) 457 | (IOMUXC_GPR3_MUX_SRC_IPU1_DI0 458 <<IOMUXC_GPR3_LVDS0_MUX_CTL_OFFSET); 459 writel(reg, &iomux->gpr[3]); 460 461 /* Backlight CABEN on LVDS connector */ 462 gpio_request(IMX_GPIO_NR(1, 10), "bklt_gpio"); 463 SETUP_IOMUX_PAD(PAD_SD2_CLK__GPIO1_IO10 | DIO_PAD_CFG); 464 gpio_direction_output(IMX_GPIO_NR(1, 10), 0); 465 } 466 #endif /* CONFIG_VIDEO_IPUV3 */ 467 468 /* setup board specific PMIC */ 469 int power_init_board(void) 470 { 471 setup_pmic(); 472 return 0; 473 } 474 475 #if defined(CONFIG_CMD_PCI) 476 int imx6_pcie_toggle_reset(void) 477 { 478 if (board_type < GW_UNKNOWN) { 479 uint pin = gpio_cfg[board_type].pcie_rst; 480 gpio_request(pin, "pci_rst#"); 481 gpio_direction_output(pin, 0); 482 mdelay(50); 483 gpio_direction_output(pin, 1); 484 } 485 return 0; 486 } 487 488 /* 489 * Most Ventana boards have a PLX PEX860x PCIe switch onboard and use its 490 * GPIO's as PERST# signals for its downstream ports - configure the GPIO's 491 * properly and assert reset for 100ms. 492 */ 493 void board_pci_fixup_dev(struct pci_controller *hose, pci_dev_t dev, 494 unsigned short vendor, unsigned short device, 495 unsigned short class) 496 { 497 u32 dw; 498 499 debug("%s: %02d:%02d.%02d: %04x:%04x\n", __func__, 500 PCI_BUS(dev), PCI_DEV(dev), PCI_FUNC(dev), vendor, device); 501 if (vendor == PCI_VENDOR_ID_PLX && 502 (device & 0xfff0) == 0x8600 && 503 PCI_DEV(dev) == 0 && PCI_FUNC(dev) == 0) { 504 debug("configuring PLX 860X downstream PERST#\n"); 505 pci_hose_read_config_dword(hose, dev, 0x62c, &dw); 506 dw |= 0xaaa8; /* GPIO1-7 outputs */ 507 pci_hose_write_config_dword(hose, dev, 0x62c, dw); 508 509 pci_hose_read_config_dword(hose, dev, 0x644, &dw); 510 dw |= 0xfe; /* GPIO1-7 output high */ 511 pci_hose_write_config_dword(hose, dev, 0x644, dw); 512 513 mdelay(100); 514 } 515 } 516 #endif /* CONFIG_CMD_PCI */ 517 518 #ifdef CONFIG_SERIAL_TAG 519 /* 520 * called when setting up ATAGS before booting kernel 521 * populate serialnum from the following (in order of priority): 522 * serial# env var 523 * eeprom 524 */ 525 void get_board_serial(struct tag_serialnr *serialnr) 526 { 527 char *serial = getenv("serial#"); 528 529 if (serial) { 530 serialnr->high = 0; 531 serialnr->low = simple_strtoul(serial, NULL, 10); 532 } else if (ventana_info.model[0]) { 533 serialnr->high = 0; 534 serialnr->low = ventana_info.serial; 535 } else { 536 serialnr->high = 0; 537 serialnr->low = 0; 538 } 539 } 540 #endif 541 542 /* 543 * Board Support 544 */ 545 546 int board_early_init_f(void) 547 { 548 setup_iomux_uart(); 549 550 #if defined(CONFIG_VIDEO_IPUV3) 551 setup_display(); 552 #endif 553 return 0; 554 } 555 556 int dram_init(void) 557 { 558 gd->ram_size = imx_ddr_size(); 559 return 0; 560 } 561 562 int board_init(void) 563 { 564 struct iomuxc *const iomuxc_regs = (struct iomuxc *)IOMUXC_BASE_ADDR; 565 566 clrsetbits_le32(&iomuxc_regs->gpr[1], 567 IOMUXC_GPR1_OTG_ID_MASK, 568 IOMUXC_GPR1_OTG_ID_GPIO1); 569 570 /* address of linux boot parameters */ 571 gd->bd->bi_boot_params = PHYS_SDRAM + 0x100; 572 573 #ifdef CONFIG_CMD_NAND 574 setup_gpmi_nand(); 575 #endif 576 #ifdef CONFIG_MXC_SPI 577 setup_spi(); 578 #endif 579 setup_ventana_i2c(); 580 581 #ifdef CONFIG_CMD_SATA 582 setup_sata(); 583 #endif 584 /* read Gateworks EEPROM into global struct (used later) */ 585 board_type = read_eeprom(CONFIG_I2C_GSC, &ventana_info); 586 587 setup_iomux_gpio(board_type, &ventana_info); 588 589 return 0; 590 } 591 592 #if defined(CONFIG_DISPLAY_BOARDINFO_LATE) 593 /* 594 * called during late init (after relocation and after board_init()) 595 * by virtue of CONFIG_DISPLAY_BOARDINFO_LATE as we needed i2c initialized and 596 * EEPROM read. 597 */ 598 int checkboard(void) 599 { 600 struct ventana_board_info *info = &ventana_info; 601 unsigned char buf[4]; 602 const char *p; 603 int quiet; /* Quiet or minimal output mode */ 604 605 quiet = 0; 606 p = getenv("quiet"); 607 if (p) 608 quiet = simple_strtol(p, NULL, 10); 609 else 610 setenv("quiet", "0"); 611 612 puts("\nGateworks Corporation Copyright 2014\n"); 613 if (info->model[0]) { 614 printf("Model: %s\n", info->model); 615 printf("MFGDate: %02x-%02x-%02x%02x\n", 616 info->mfgdate[0], info->mfgdate[1], 617 info->mfgdate[2], info->mfgdate[3]); 618 printf("Serial:%d\n", info->serial); 619 } else { 620 puts("Invalid EEPROM - board will not function fully\n"); 621 } 622 if (quiet) 623 return 0; 624 625 /* Display GSC firmware revision/CRC/status */ 626 gsc_info(0); 627 628 /* Display RTC */ 629 if (!gsc_i2c_read(GSC_RTC_ADDR, 0x00, 1, buf, 4)) { 630 printf("RTC: %d\n", 631 buf[0] | buf[1]<<8 | buf[2]<<16 | buf[3]<<24); 632 } 633 634 return 0; 635 } 636 #endif 637 638 #ifdef CONFIG_CMD_BMODE 639 /* 640 * BOOT_CFG1, BOOT_CFG2, BOOT_CFG3, BOOT_CFG4 641 * see Table 8-11 and Table 5-9 642 * BOOT_CFG1[7] = 1 (boot from NAND) 643 * BOOT_CFG1[5] = 0 - raw NAND 644 * BOOT_CFG1[4] = 0 - default pad settings 645 * BOOT_CFG1[3:2] = 00 - devices = 1 646 * BOOT_CFG1[1:0] = 00 - Row Address Cycles = 3 647 * BOOT_CFG2[4:3] = 00 - Boot Search Count = 2 648 * BOOT_CFG2[2:1] = 01 - Pages In Block = 64 649 * BOOT_CFG2[0] = 0 - Reset time 12ms 650 */ 651 static const struct boot_mode board_boot_modes[] = { 652 /* NAND: 64pages per block, 3 row addr cycles, 2 copies of FCB/DBBT */ 653 { "nand", MAKE_CFGVAL(0x80, 0x02, 0x00, 0x00) }, 654 { NULL, 0 }, 655 }; 656 #endif 657 658 /* late init */ 659 int misc_init_r(void) 660 { 661 struct ventana_board_info *info = &ventana_info; 662 663 /* set env vars based on EEPROM data */ 664 if (ventana_info.model[0]) { 665 char str[16], fdt[36]; 666 char *p; 667 const char *cputype = ""; 668 int i; 669 670 /* 671 * FDT name will be prefixed with CPU type. Three versions 672 * will be created each increasingly generic and bootloader 673 * env scripts will try loading each from most specific to 674 * least. 675 */ 676 if (is_cpu_type(MXC_CPU_MX6Q) || 677 is_cpu_type(MXC_CPU_MX6D)) 678 cputype = "imx6q"; 679 else if (is_cpu_type(MXC_CPU_MX6DL) || 680 is_cpu_type(MXC_CPU_MX6SOLO)) 681 cputype = "imx6dl"; 682 setenv("soctype", cputype); 683 if (8 << (ventana_info.nand_flash_size-1) >= 2048) 684 setenv("flash_layout", "large"); 685 else 686 setenv("flash_layout", "normal"); 687 memset(str, 0, sizeof(str)); 688 for (i = 0; i < (sizeof(str)-1) && info->model[i]; i++) 689 str[i] = tolower(info->model[i]); 690 if (!getenv("model")) 691 setenv("model", str); 692 if (!getenv("fdt_file")) { 693 sprintf(fdt, "%s-%s.dtb", cputype, str); 694 setenv("fdt_file", fdt); 695 } 696 p = strchr(str, '-'); 697 if (p) { 698 *p++ = 0; 699 700 setenv("model_base", str); 701 if (!getenv("fdt_file1")) { 702 sprintf(fdt, "%s-%s.dtb", cputype, str); 703 setenv("fdt_file1", fdt); 704 } 705 if (board_type != GW551x && board_type != GW552x) 706 str[4] = 'x'; 707 str[5] = 'x'; 708 str[6] = 0; 709 if (!getenv("fdt_file2")) { 710 sprintf(fdt, "%s-%s.dtb", cputype, str); 711 setenv("fdt_file2", fdt); 712 } 713 } 714 715 /* initialize env from EEPROM */ 716 if (test_bit(EECONFIG_ETH0, info->config) && 717 !getenv("ethaddr")) { 718 eth_setenv_enetaddr("ethaddr", info->mac0); 719 } 720 if (test_bit(EECONFIG_ETH1, info->config) && 721 !getenv("eth1addr")) { 722 eth_setenv_enetaddr("eth1addr", info->mac1); 723 } 724 725 /* board serial-number */ 726 sprintf(str, "%6d", info->serial); 727 setenv("serial#", str); 728 729 /* memory MB */ 730 sprintf(str, "%d", (int) (gd->ram_size >> 20)); 731 setenv("mem_mb", str); 732 } 733 734 735 /* setup baseboard specific GPIO based on board and env */ 736 setup_board_gpio(board_type, info); 737 738 #ifdef CONFIG_CMD_BMODE 739 add_board_boot_modes(board_boot_modes); 740 #endif 741 742 /* disable boot watchdog */ 743 gsc_boot_wd_disable(); 744 745 return 0; 746 } 747 748 #if defined(CONFIG_OF_LIBFDT) && defined(CONFIG_OF_BOARD_SETUP) 749 750 static int ft_sethdmiinfmt(void *blob, char *mode) 751 { 752 int off; 753 754 if (!mode) 755 return -EINVAL; 756 757 off = fdt_node_offset_by_compatible(blob, -1, "nxp,tda1997x"); 758 if (off < 0) 759 return off; 760 761 if (0 == strcasecmp(mode, "yuv422bt656")) { 762 u8 cfg[] = { 0x00, 0x00, 0x00, 0x82, 0x81, 0x00, 763 0x00, 0x00, 0x00 }; 764 mode = "422_ccir"; 765 fdt_setprop(blob, off, "vidout_fmt", mode, strlen(mode) + 1); 766 fdt_setprop_u32(blob, off, "vidout_trc", 1); 767 fdt_setprop_u32(blob, off, "vidout_blc", 1); 768 fdt_setprop(blob, off, "vidout_portcfg", cfg, sizeof(cfg)); 769 printf(" set HDMI input mode to %s\n", mode); 770 } else if (0 == strcasecmp(mode, "yuv422smp")) { 771 u8 cfg[] = { 0x00, 0x00, 0x00, 0x88, 0x87, 0x00, 772 0x82, 0x81, 0x00 }; 773 mode = "422_smp"; 774 fdt_setprop(blob, off, "vidout_fmt", mode, strlen(mode) + 1); 775 fdt_setprop_u32(blob, off, "vidout_trc", 0); 776 fdt_setprop_u32(blob, off, "vidout_blc", 0); 777 fdt_setprop(blob, off, "vidout_portcfg", cfg, sizeof(cfg)); 778 printf(" set HDMI input mode to %s\n", mode); 779 } else { 780 return -EINVAL; 781 } 782 783 return 0; 784 } 785 786 /* 787 * called prior to booting kernel or by 'fdt boardsetup' command 788 * 789 * unless 'fdt_noauto' env var is set we will update the following in the DTB: 790 * - mtd partitions based on mtdparts/mtdids env 791 * - system-serial (board serial num from EEPROM) 792 * - board (full model from EEPROM) 793 * - peripherals removed from DTB if not loaded on board (per EEPROM config) 794 */ 795 int ft_board_setup(void *blob, bd_t *bd) 796 { 797 struct ventana_board_info *info = &ventana_info; 798 struct ventana_eeprom_config *cfg; 799 struct node_info nodes[] = { 800 { "sst,w25q256", MTD_DEV_TYPE_NOR, }, /* SPI flash */ 801 { "fsl,imx6q-gpmi-nand", MTD_DEV_TYPE_NAND, }, /* NAND flash */ 802 }; 803 const char *model = getenv("model"); 804 const char *display = getenv("display"); 805 int i; 806 char rev = 0; 807 808 /* determine board revision */ 809 for (i = sizeof(ventana_info.model) - 1; i > 0; i--) { 810 if (ventana_info.model[i] >= 'A') { 811 rev = ventana_info.model[i]; 812 break; 813 } 814 } 815 816 if (getenv("fdt_noauto")) { 817 puts(" Skiping ft_board_setup (fdt_noauto defined)\n"); 818 return 0; 819 } 820 821 /* Update partition nodes using info from mtdparts env var */ 822 puts(" Updating MTD partitions...\n"); 823 fdt_fixup_mtdparts(blob, nodes, ARRAY_SIZE(nodes)); 824 825 /* Update display timings from display env var */ 826 if (display) { 827 if (fdt_fixup_display(blob, fdt_get_alias(blob, "lvds0"), 828 display) >= 0) 829 printf(" Set display timings for %s...\n", display); 830 } 831 832 if (!model) { 833 puts("invalid board info: Leaving FDT fully enabled\n"); 834 return 0; 835 } 836 printf(" Adjusting FDT per EEPROM for %s...\n", model); 837 838 /* board serial number */ 839 fdt_setprop(blob, 0, "system-serial", getenv("serial#"), 840 strlen(getenv("serial#")) + 1); 841 842 /* board (model contains model from device-tree) */ 843 fdt_setprop(blob, 0, "board", info->model, 844 strlen((const char *)info->model) + 1); 845 846 /* set desired digital video capture format */ 847 ft_sethdmiinfmt(blob, getenv("hdmiinfmt")); 848 849 /* 850 * disable serial2 node for GW54xx for compatibility with older 851 * 3.10.x kernel that improperly had this node enabled in the DT 852 */ 853 if (board_type == GW54xx) { 854 i = fdt_path_offset(blob, 855 "/soc/aips-bus@02100000/serial@021ec000"); 856 if (i) 857 fdt_del_node(blob, i); 858 } 859 860 /* 861 * disable wdog1/wdog2 nodes for GW51xx below revC to work around 862 * errata causing wdog timer to be unreliable. 863 */ 864 if (board_type == GW51xx && rev >= 'A' && rev < 'C') { 865 i = fdt_path_offset(blob, 866 "/soc/aips-bus@02000000/wdog@020bc000"); 867 if (i) 868 fdt_status_disabled(blob, i); 869 } 870 871 /* GW522x Uses GPIO3_IO23 instead of GPIO1_IO29 */ 872 else if (board_type == GW52xx && info->model[4] == '2') { 873 u32 handle = 0; 874 u32 *range = NULL; 875 876 i = fdt_node_offset_by_compatible(blob, -1, "fsl,imx6q-pcie"); 877 if (i) 878 range = (u32 *)fdt_getprop(blob, i, "reset-gpio", 879 NULL); 880 881 if (range) { 882 i = fdt_path_offset(blob, 883 "/soc/aips-bus@02000000/gpio@020a4000"); 884 if (i) 885 handle = fdt_get_phandle(blob, i); 886 if (handle) { 887 range[0] = cpu_to_fdt32(handle); 888 range[1] = cpu_to_fdt32(23); 889 } 890 } 891 } 892 893 /* 894 * isolate CSI0_DATA_EN for GW551x below revB to work around 895 * errata causing non functional digital video in (it is not hooked up) 896 */ 897 else if (board_type == GW551x && rev == 'A') { 898 u32 *range = NULL; 899 int len; 900 const u32 *handle = NULL; 901 902 i = fdt_node_offset_by_compatible(blob, -1, 903 "fsl,imx-tda1997x-video"); 904 if (i) 905 handle = fdt_getprop(blob, i, "pinctrl-0", NULL); 906 if (handle) 907 i = fdt_node_offset_by_phandle(blob, 908 fdt32_to_cpu(*handle)); 909 if (i) 910 range = (u32 *)fdt_getprop(blob, i, "fsl,pins", &len); 911 if (range) { 912 len /= sizeof(u32); 913 for (i = 0; i < len; i += 6) { 914 u32 mux_reg = fdt32_to_cpu(range[i+0]); 915 u32 conf_reg = fdt32_to_cpu(range[i+1]); 916 /* mux PAD_CSI0_DATA_EN to GPIO */ 917 if (is_cpu_type(MXC_CPU_MX6Q) && 918 mux_reg == 0x260 && conf_reg == 0x630) 919 range[i+3] = cpu_to_fdt32(0x5); 920 else if (!is_cpu_type(MXC_CPU_MX6Q) && 921 mux_reg == 0x08c && conf_reg == 0x3a0) 922 range[i+3] = cpu_to_fdt32(0x5); 923 } 924 fdt_setprop_inplace(blob, i, "fsl,pins", range, len); 925 } 926 927 /* set BT656 video format */ 928 ft_sethdmiinfmt(blob, "yuv422bt656"); 929 } 930 931 /* 932 * Peripheral Config: 933 * remove nodes by alias path if EEPROM config tells us the 934 * peripheral is not loaded on the board. 935 */ 936 if (getenv("fdt_noconfig")) { 937 puts(" Skiping periperhal config (fdt_noconfig defined)\n"); 938 return 0; 939 } 940 cfg = econfig; 941 while (cfg->name) { 942 if (!test_bit(cfg->bit, info->config)) { 943 fdt_del_node_and_alias(blob, cfg->dtalias ? 944 cfg->dtalias : cfg->name); 945 } 946 cfg++; 947 } 948 949 return 0; 950 } 951 #endif /* defined(CONFIG_OF_FLAT_TREE) && defined(CONFIG_OF_BOARD_SETUP) */ 952 953 static struct mxc_serial_platdata ventana_mxc_serial_plat = { 954 .reg = (struct mxc_uart *)UART2_BASE, 955 }; 956 957 U_BOOT_DEVICE(ventana_serial) = { 958 .name = "serial_mxc", 959 .platdata = &ventana_mxc_serial_plat, 960 }; 961