1 /* 2 * Copyright (C) 2013 Gateworks Corporation 3 * 4 * Author: Tim Harvey <tharvey@gateworks.com> 5 * 6 * SPDX-License-Identifier: GPL-2.0+ 7 */ 8 9 #include <common.h> 10 #include <asm/io.h> 11 #include <asm/arch/clock.h> 12 #include <asm/arch/imx-regs.h> 13 #include <asm/arch/iomux.h> 14 #include <asm/arch/mx6-pins.h> 15 #include <asm/arch/mxc_hdmi.h> 16 #include <asm/arch/crm_regs.h> 17 #include <asm/arch/sys_proto.h> 18 #include <asm/gpio.h> 19 #include <asm/imx-common/iomux-v3.h> 20 #include <asm/imx-common/mxc_i2c.h> 21 #include <asm/imx-common/boot_mode.h> 22 #include <asm/imx-common/sata.h> 23 #include <asm/imx-common/video.h> 24 #include <jffs2/load_kernel.h> 25 #include <hwconfig.h> 26 #include <i2c.h> 27 #include <linux/ctype.h> 28 #include <fdt_support.h> 29 #include <fsl_esdhc.h> 30 #include <miiphy.h> 31 #include <mmc.h> 32 #include <mtd_node.h> 33 #include <netdev.h> 34 #include <pci.h> 35 #include <power/pmic.h> 36 #include <power/ltc3676_pmic.h> 37 #include <power/pfuze100_pmic.h> 38 #include <fdt_support.h> 39 #include <jffs2/load_kernel.h> 40 #include <spi_flash.h> 41 42 #include "gsc.h" 43 #include "ventana_eeprom.h" 44 45 DECLARE_GLOBAL_DATA_PTR; 46 47 /* GPIO's common to all baseboards */ 48 #define GP_PHY_RST IMX_GPIO_NR(1, 30) 49 #define GP_USB_OTG_PWR IMX_GPIO_NR(3, 22) 50 #define GP_SD3_CD IMX_GPIO_NR(7, 0) 51 #define GP_RS232_EN IMX_GPIO_NR(2, 11) 52 #define GP_MSATA_SEL IMX_GPIO_NR(2, 8) 53 54 #define UART_PAD_CTRL (PAD_CTL_PKE | PAD_CTL_PUE | \ 55 PAD_CTL_PUS_100K_UP | PAD_CTL_SPEED_MED | \ 56 PAD_CTL_DSE_40ohm | PAD_CTL_SRE_FAST | PAD_CTL_HYS) 57 58 #define USDHC_PAD_CTRL (PAD_CTL_PKE | PAD_CTL_PUE | \ 59 PAD_CTL_PUS_47K_UP | PAD_CTL_SPEED_LOW | \ 60 PAD_CTL_DSE_80ohm | PAD_CTL_SRE_FAST | PAD_CTL_HYS) 61 62 #define ENET_PAD_CTRL (PAD_CTL_PKE | PAD_CTL_PUE | \ 63 PAD_CTL_PUS_100K_UP | PAD_CTL_SPEED_MED | \ 64 PAD_CTL_DSE_40ohm | PAD_CTL_HYS) 65 66 #define SPI_PAD_CTRL (PAD_CTL_HYS | \ 67 PAD_CTL_PUS_100K_DOWN | PAD_CTL_SPEED_MED | \ 68 PAD_CTL_DSE_40ohm | PAD_CTL_SRE_FAST) 69 70 #define DIO_PAD_CTRL (PAD_CTL_PKE | PAD_CTL_PUE | \ 71 PAD_CTL_PUS_100K_UP | PAD_CTL_SPEED_MED | \ 72 PAD_CTL_DSE_34ohm | PAD_CTL_HYS | PAD_CTL_SRE_FAST) 73 74 #define I2C_PAD_CTRL (PAD_CTL_PUS_100K_UP | \ 75 PAD_CTL_SPEED_MED | PAD_CTL_DSE_40ohm | PAD_CTL_HYS | \ 76 PAD_CTL_ODE | PAD_CTL_SRE_FAST) 77 78 #define IRQ_PAD_CTRL (PAD_CTL_PKE | PAD_CTL_PUE | \ 79 PAD_CTL_PUS_100K_UP | PAD_CTL_SPEED_MED | \ 80 PAD_CTL_DSE_34ohm | PAD_CTL_HYS | PAD_CTL_SRE_FAST) 81 82 #define DIO_PAD_CFG (MUX_PAD_CTRL(DIO_PAD_CTRL) | MUX_MODE_SION) 83 84 85 /* 86 * EEPROM board info struct populated by read_eeprom so that we only have to 87 * read it once. 88 */ 89 struct ventana_board_info ventana_info; 90 91 int board_type; 92 93 /* UART1: Function varies per baseboard */ 94 iomux_v3_cfg_t const uart1_pads[] = { 95 IOMUX_PADS(PAD_SD3_DAT6__UART1_RX_DATA | MUX_PAD_CTRL(UART_PAD_CTRL)), 96 IOMUX_PADS(PAD_SD3_DAT7__UART1_TX_DATA | MUX_PAD_CTRL(UART_PAD_CTRL)), 97 }; 98 99 /* UART2: Serial Console */ 100 iomux_v3_cfg_t const uart2_pads[] = { 101 IOMUX_PADS(PAD_SD4_DAT7__UART2_TX_DATA | MUX_PAD_CTRL(UART_PAD_CTRL)), 102 IOMUX_PADS(PAD_SD4_DAT4__UART2_RX_DATA | MUX_PAD_CTRL(UART_PAD_CTRL)), 103 }; 104 105 #define PC MUX_PAD_CTRL(I2C_PAD_CTRL) 106 107 /* I2C1: GSC */ 108 struct i2c_pads_info mx6q_i2c_pad_info0 = { 109 .scl = { 110 .i2c_mode = MX6Q_PAD_EIM_D21__I2C1_SCL | PC, 111 .gpio_mode = MX6Q_PAD_EIM_D21__GPIO3_IO21 | PC, 112 .gp = IMX_GPIO_NR(3, 21) 113 }, 114 .sda = { 115 .i2c_mode = MX6Q_PAD_EIM_D28__I2C1_SDA | PC, 116 .gpio_mode = MX6Q_PAD_EIM_D28__GPIO3_IO28 | PC, 117 .gp = IMX_GPIO_NR(3, 28) 118 } 119 }; 120 struct i2c_pads_info mx6dl_i2c_pad_info0 = { 121 .scl = { 122 .i2c_mode = MX6DL_PAD_EIM_D21__I2C1_SCL | PC, 123 .gpio_mode = MX6DL_PAD_EIM_D21__GPIO3_IO21 | PC, 124 .gp = IMX_GPIO_NR(3, 21) 125 }, 126 .sda = { 127 .i2c_mode = MX6DL_PAD_EIM_D28__I2C1_SDA | PC, 128 .gpio_mode = MX6DL_PAD_EIM_D28__GPIO3_IO28 | PC, 129 .gp = IMX_GPIO_NR(3, 28) 130 } 131 }; 132 133 /* I2C2: PMIC/PCIe Switch/PCIe Clock/Mezz */ 134 struct i2c_pads_info mx6q_i2c_pad_info1 = { 135 .scl = { 136 .i2c_mode = MX6Q_PAD_KEY_COL3__I2C2_SCL | PC, 137 .gpio_mode = MX6Q_PAD_KEY_COL3__GPIO4_IO12 | PC, 138 .gp = IMX_GPIO_NR(4, 12) 139 }, 140 .sda = { 141 .i2c_mode = MX6Q_PAD_KEY_ROW3__I2C2_SDA | PC, 142 .gpio_mode = MX6Q_PAD_KEY_ROW3__GPIO4_IO13 | PC, 143 .gp = IMX_GPIO_NR(4, 13) 144 } 145 }; 146 struct i2c_pads_info mx6dl_i2c_pad_info1 = { 147 .scl = { 148 .i2c_mode = MX6DL_PAD_KEY_COL3__I2C2_SCL | PC, 149 .gpio_mode = MX6DL_PAD_KEY_COL3__GPIO4_IO12 | PC, 150 .gp = IMX_GPIO_NR(4, 12) 151 }, 152 .sda = { 153 .i2c_mode = MX6DL_PAD_KEY_ROW3__I2C2_SDA | PC, 154 .gpio_mode = MX6DL_PAD_KEY_ROW3__GPIO4_IO13 | PC, 155 .gp = IMX_GPIO_NR(4, 13) 156 } 157 }; 158 159 /* I2C3: Misc/Expansion */ 160 struct i2c_pads_info mx6q_i2c_pad_info2 = { 161 .scl = { 162 .i2c_mode = MX6Q_PAD_GPIO_3__I2C3_SCL | PC, 163 .gpio_mode = MX6Q_PAD_GPIO_3__GPIO1_IO03 | PC, 164 .gp = IMX_GPIO_NR(1, 3) 165 }, 166 .sda = { 167 .i2c_mode = MX6Q_PAD_GPIO_6__I2C3_SDA | PC, 168 .gpio_mode = MX6Q_PAD_GPIO_6__GPIO1_IO06 | PC, 169 .gp = IMX_GPIO_NR(1, 6) 170 } 171 }; 172 struct i2c_pads_info mx6dl_i2c_pad_info2 = { 173 .scl = { 174 .i2c_mode = MX6DL_PAD_GPIO_3__I2C3_SCL | PC, 175 .gpio_mode = MX6DL_PAD_GPIO_3__GPIO1_IO03 | PC, 176 .gp = IMX_GPIO_NR(1, 3) 177 }, 178 .sda = { 179 .i2c_mode = MX6DL_PAD_GPIO_6__I2C3_SDA | PC, 180 .gpio_mode = MX6DL_PAD_GPIO_6__GPIO1_IO06 | PC, 181 .gp = IMX_GPIO_NR(1, 6) 182 } 183 }; 184 185 /* MMC */ 186 iomux_v3_cfg_t const usdhc3_pads[] = { 187 IOMUX_PADS(PAD_SD3_CLK__SD3_CLK | MUX_PAD_CTRL(USDHC_PAD_CTRL)), 188 IOMUX_PADS(PAD_SD3_CMD__SD3_CMD | MUX_PAD_CTRL(USDHC_PAD_CTRL)), 189 IOMUX_PADS(PAD_SD3_DAT0__SD3_DATA0 | MUX_PAD_CTRL(USDHC_PAD_CTRL)), 190 IOMUX_PADS(PAD_SD3_DAT1__SD3_DATA1 | MUX_PAD_CTRL(USDHC_PAD_CTRL)), 191 IOMUX_PADS(PAD_SD3_DAT2__SD3_DATA2 | MUX_PAD_CTRL(USDHC_PAD_CTRL)), 192 IOMUX_PADS(PAD_SD3_DAT3__SD3_DATA3 | MUX_PAD_CTRL(USDHC_PAD_CTRL)), 193 /* CD */ 194 IOMUX_PADS(PAD_SD3_DAT5__GPIO7_IO00 | MUX_PAD_CTRL(IRQ_PAD_CTRL)), 195 }; 196 197 /* ENET */ 198 iomux_v3_cfg_t const enet_pads[] = { 199 IOMUX_PADS(PAD_ENET_MDIO__ENET_MDIO | MUX_PAD_CTRL(ENET_PAD_CTRL)), 200 IOMUX_PADS(PAD_ENET_MDC__ENET_MDC | MUX_PAD_CTRL(ENET_PAD_CTRL)), 201 IOMUX_PADS(PAD_RGMII_TXC__RGMII_TXC | MUX_PAD_CTRL(ENET_PAD_CTRL)), 202 IOMUX_PADS(PAD_RGMII_TD0__RGMII_TD0 | MUX_PAD_CTRL(ENET_PAD_CTRL)), 203 IOMUX_PADS(PAD_RGMII_TD1__RGMII_TD1 | MUX_PAD_CTRL(ENET_PAD_CTRL)), 204 IOMUX_PADS(PAD_RGMII_TD2__RGMII_TD2 | MUX_PAD_CTRL(ENET_PAD_CTRL)), 205 IOMUX_PADS(PAD_RGMII_TD3__RGMII_TD3 | MUX_PAD_CTRL(ENET_PAD_CTRL)), 206 IOMUX_PADS(PAD_RGMII_TX_CTL__RGMII_TX_CTL | 207 MUX_PAD_CTRL(ENET_PAD_CTRL)), 208 IOMUX_PADS(PAD_ENET_REF_CLK__ENET_TX_CLK | 209 MUX_PAD_CTRL(ENET_PAD_CTRL)), 210 IOMUX_PADS(PAD_RGMII_RXC__RGMII_RXC | MUX_PAD_CTRL(ENET_PAD_CTRL)), 211 IOMUX_PADS(PAD_RGMII_RD0__RGMII_RD0 | MUX_PAD_CTRL(ENET_PAD_CTRL)), 212 IOMUX_PADS(PAD_RGMII_RD1__RGMII_RD1 | MUX_PAD_CTRL(ENET_PAD_CTRL)), 213 IOMUX_PADS(PAD_RGMII_RD2__RGMII_RD2 | MUX_PAD_CTRL(ENET_PAD_CTRL)), 214 IOMUX_PADS(PAD_RGMII_RD3__RGMII_RD3 | MUX_PAD_CTRL(ENET_PAD_CTRL)), 215 IOMUX_PADS(PAD_RGMII_RX_CTL__RGMII_RX_CTL | 216 MUX_PAD_CTRL(ENET_PAD_CTRL)), 217 /* PHY nRST */ 218 IOMUX_PADS(PAD_ENET_TXD0__GPIO1_IO30 | DIO_PAD_CFG), 219 }; 220 221 /* NAND */ 222 iomux_v3_cfg_t const nfc_pads[] = { 223 IOMUX_PADS(PAD_NANDF_CLE__NAND_CLE | MUX_PAD_CTRL(NO_PAD_CTRL)), 224 IOMUX_PADS(PAD_NANDF_ALE__NAND_ALE | MUX_PAD_CTRL(NO_PAD_CTRL)), 225 IOMUX_PADS(PAD_NANDF_WP_B__NAND_WP_B | MUX_PAD_CTRL(NO_PAD_CTRL)), 226 IOMUX_PADS(PAD_NANDF_RB0__NAND_READY_B | MUX_PAD_CTRL(NO_PAD_CTRL)), 227 IOMUX_PADS(PAD_NANDF_CS0__NAND_CE0_B | MUX_PAD_CTRL(NO_PAD_CTRL)), 228 IOMUX_PADS(PAD_SD4_CMD__NAND_RE_B | MUX_PAD_CTRL(NO_PAD_CTRL)), 229 IOMUX_PADS(PAD_SD4_CLK__NAND_WE_B | MUX_PAD_CTRL(NO_PAD_CTRL)), 230 IOMUX_PADS(PAD_NANDF_D0__NAND_DATA00 | MUX_PAD_CTRL(NO_PAD_CTRL)), 231 IOMUX_PADS(PAD_NANDF_D1__NAND_DATA01 | MUX_PAD_CTRL(NO_PAD_CTRL)), 232 IOMUX_PADS(PAD_NANDF_D2__NAND_DATA02 | MUX_PAD_CTRL(NO_PAD_CTRL)), 233 IOMUX_PADS(PAD_NANDF_D3__NAND_DATA03 | MUX_PAD_CTRL(NO_PAD_CTRL)), 234 IOMUX_PADS(PAD_NANDF_D4__NAND_DATA04 | MUX_PAD_CTRL(NO_PAD_CTRL)), 235 IOMUX_PADS(PAD_NANDF_D5__NAND_DATA05 | MUX_PAD_CTRL(NO_PAD_CTRL)), 236 IOMUX_PADS(PAD_NANDF_D6__NAND_DATA06 | MUX_PAD_CTRL(NO_PAD_CTRL)), 237 IOMUX_PADS(PAD_NANDF_D7__NAND_DATA07 | MUX_PAD_CTRL(NO_PAD_CTRL)), 238 }; 239 240 #ifdef CONFIG_CMD_NAND 241 static void setup_gpmi_nand(void) 242 { 243 struct mxc_ccm_reg *mxc_ccm = (struct mxc_ccm_reg *)CCM_BASE_ADDR; 244 245 /* config gpmi nand iomux */ 246 SETUP_IOMUX_PADS(nfc_pads); 247 248 /* config gpmi and bch clock to 100 MHz */ 249 clrsetbits_le32(&mxc_ccm->cs2cdr, 250 MXC_CCM_CS2CDR_ENFC_CLK_PODF_MASK | 251 MXC_CCM_CS2CDR_ENFC_CLK_PRED_MASK | 252 MXC_CCM_CS2CDR_ENFC_CLK_SEL_MASK, 253 MXC_CCM_CS2CDR_ENFC_CLK_PODF(0) | 254 MXC_CCM_CS2CDR_ENFC_CLK_PRED(3) | 255 MXC_CCM_CS2CDR_ENFC_CLK_SEL(3)); 256 257 /* enable gpmi and bch clock gating */ 258 setbits_le32(&mxc_ccm->CCGR4, 259 MXC_CCM_CCGR4_RAWNAND_U_BCH_INPUT_APB_MASK | 260 MXC_CCM_CCGR4_RAWNAND_U_GPMI_BCH_INPUT_BCH_MASK | 261 MXC_CCM_CCGR4_RAWNAND_U_GPMI_BCH_INPUT_GPMI_IO_MASK | 262 MXC_CCM_CCGR4_RAWNAND_U_GPMI_INPUT_APB_MASK | 263 MXC_CCM_CCGR4_PL301_MX6QPER1_BCH_OFFSET); 264 265 /* enable apbh clock gating */ 266 setbits_le32(&mxc_ccm->CCGR0, MXC_CCM_CCGR0_APBHDMA_MASK); 267 } 268 #endif 269 270 static void setup_iomux_enet(void) 271 { 272 SETUP_IOMUX_PADS(enet_pads); 273 274 /* toggle PHY_RST# */ 275 gpio_direction_output(GP_PHY_RST, 0); 276 mdelay(2); 277 gpio_set_value(GP_PHY_RST, 1); 278 } 279 280 static void setup_iomux_uart(void) 281 { 282 SETUP_IOMUX_PADS(uart1_pads); 283 SETUP_IOMUX_PADS(uart2_pads); 284 } 285 286 #ifdef CONFIG_USB_EHCI_MX6 287 iomux_v3_cfg_t const usb_pads[] = { 288 IOMUX_PADS(PAD_GPIO_1__USB_OTG_ID | DIO_PAD_CFG), 289 IOMUX_PADS(PAD_KEY_COL4__USB_OTG_OC | DIO_PAD_CFG), 290 /* OTG PWR */ 291 IOMUX_PADS(PAD_EIM_D22__GPIO3_IO22 | DIO_PAD_CFG), 292 }; 293 294 int board_ehci_hcd_init(int port) 295 { 296 struct ventana_board_info *info = &ventana_info; 297 298 SETUP_IOMUX_PADS(usb_pads); 299 300 /* Reset USB HUB (present on GW54xx/GW53xx) */ 301 switch (info->model[3]) { 302 case '3': /* GW53xx */ 303 case '5': /* GW552x */ 304 SETUP_IOMUX_PAD(PAD_GPIO_9__GPIO1_IO09 | DIO_PAD_CFG); 305 gpio_direction_output(IMX_GPIO_NR(1, 9), 0); 306 mdelay(2); 307 gpio_set_value(IMX_GPIO_NR(1, 9), 1); 308 break; 309 case '4': /* GW54xx */ 310 SETUP_IOMUX_PAD(PAD_SD1_DAT0__GPIO1_IO16 | DIO_PAD_CFG); 311 gpio_direction_output(IMX_GPIO_NR(1, 16), 0); 312 mdelay(2); 313 gpio_set_value(IMX_GPIO_NR(1, 16), 1); 314 break; 315 } 316 317 return 0; 318 } 319 320 int board_ehci_power(int port, int on) 321 { 322 if (port) 323 return 0; 324 gpio_set_value(GP_USB_OTG_PWR, on); 325 return 0; 326 } 327 #endif /* CONFIG_USB_EHCI_MX6 */ 328 329 #ifdef CONFIG_FSL_ESDHC 330 struct fsl_esdhc_cfg usdhc_cfg = { USDHC3_BASE_ADDR }; 331 332 int board_mmc_getcd(struct mmc *mmc) 333 { 334 /* Card Detect */ 335 gpio_direction_input(GP_SD3_CD); 336 return !gpio_get_value(GP_SD3_CD); 337 } 338 339 int board_mmc_init(bd_t *bis) 340 { 341 /* Only one USDHC controller on Ventana */ 342 SETUP_IOMUX_PADS(usdhc3_pads); 343 usdhc_cfg.sdhc_clk = mxc_get_clock(MXC_ESDHC3_CLK); 344 usdhc_cfg.max_bus_width = 4; 345 346 return fsl_esdhc_initialize(bis, &usdhc_cfg); 347 } 348 #endif /* CONFIG_FSL_ESDHC */ 349 350 #ifdef CONFIG_MXC_SPI 351 iomux_v3_cfg_t const ecspi1_pads[] = { 352 /* SS1 */ 353 IOMUX_PADS(PAD_EIM_D19__GPIO3_IO19 | MUX_PAD_CTRL(SPI_PAD_CTRL)), 354 IOMUX_PADS(PAD_EIM_D17__ECSPI1_MISO | MUX_PAD_CTRL(SPI_PAD_CTRL)), 355 IOMUX_PADS(PAD_EIM_D18__ECSPI1_MOSI | MUX_PAD_CTRL(SPI_PAD_CTRL)), 356 IOMUX_PADS(PAD_EIM_D16__ECSPI1_SCLK | MUX_PAD_CTRL(SPI_PAD_CTRL)), 357 }; 358 359 int board_spi_cs_gpio(unsigned bus, unsigned cs) 360 { 361 return (bus == 0 && cs == 0) ? (IMX_GPIO_NR(3, 19)) : -1; 362 } 363 364 static void setup_spi(void) 365 { 366 gpio_direction_output(IMX_GPIO_NR(3, 19), 1); 367 SETUP_IOMUX_PADS(ecspi1_pads); 368 } 369 #endif 370 371 /* configure eth0 PHY board-specific LED behavior */ 372 int board_phy_config(struct phy_device *phydev) 373 { 374 unsigned short val; 375 376 /* Marvel 88E1510 */ 377 if (phydev->phy_id == 0x1410dd1) { 378 /* 379 * Page 3, Register 16: LED[2:0] Function Control Register 380 * LED[0] (SPD:Amber) R16_3.3:0 to 0111: on-GbE link 381 * LED[1] (LNK:Green) R16_3.7:4 to 0001: on-link, blink-activity 382 */ 383 phy_write(phydev, MDIO_DEVAD_NONE, 22, 3); 384 val = phy_read(phydev, MDIO_DEVAD_NONE, 16); 385 val &= 0xff00; 386 val |= 0x0017; 387 phy_write(phydev, MDIO_DEVAD_NONE, 16, val); 388 phy_write(phydev, MDIO_DEVAD_NONE, 22, 0); 389 } 390 391 if (phydev->drv->config) 392 phydev->drv->config(phydev); 393 394 return 0; 395 } 396 397 int board_eth_init(bd_t *bis) 398 { 399 setup_iomux_enet(); 400 401 #ifdef CONFIG_FEC_MXC 402 if (board_type != GW552x) 403 cpu_eth_init(bis); 404 #endif 405 406 #ifdef CONFIG_CI_UDC 407 /* For otg ethernet*/ 408 usb_eth_initialize(bis); 409 #endif 410 411 return 0; 412 } 413 414 #if defined(CONFIG_VIDEO_IPUV3) 415 416 static void enable_hdmi(struct display_info_t const *dev) 417 { 418 imx_enable_hdmi_phy(); 419 } 420 421 static int detect_i2c(struct display_info_t const *dev) 422 { 423 return i2c_set_bus_num(dev->bus) == 0 && 424 i2c_probe(dev->addr) == 0; 425 } 426 427 static void enable_lvds(struct display_info_t const *dev) 428 { 429 struct iomuxc *iomux = (struct iomuxc *) 430 IOMUXC_BASE_ADDR; 431 432 /* set CH0 data width to 24bit (IOMUXC_GPR2:5 0=18bit, 1=24bit) */ 433 u32 reg = readl(&iomux->gpr[2]); 434 reg |= IOMUXC_GPR2_DATA_WIDTH_CH0_24BIT; 435 writel(reg, &iomux->gpr[2]); 436 437 /* Enable Backlight */ 438 SETUP_IOMUX_PAD(PAD_SD1_CMD__GPIO1_IO18 | DIO_PAD_CFG); 439 gpio_direction_output(IMX_GPIO_NR(1, 18), 1); 440 } 441 442 struct display_info_t const displays[] = {{ 443 /* HDMI Output */ 444 .bus = -1, 445 .addr = 0, 446 .pixfmt = IPU_PIX_FMT_RGB24, 447 .detect = detect_hdmi, 448 .enable = enable_hdmi, 449 .mode = { 450 .name = "HDMI", 451 .refresh = 60, 452 .xres = 1024, 453 .yres = 768, 454 .pixclock = 15385, 455 .left_margin = 220, 456 .right_margin = 40, 457 .upper_margin = 21, 458 .lower_margin = 7, 459 .hsync_len = 60, 460 .vsync_len = 10, 461 .sync = FB_SYNC_EXT, 462 .vmode = FB_VMODE_NONINTERLACED 463 } }, { 464 /* Freescale MXC-LVDS1: HannStar HSD100PXN1-A00 w/ egalx_ts cont */ 465 .bus = 2, 466 .addr = 0x4, 467 .pixfmt = IPU_PIX_FMT_LVDS666, 468 .detect = detect_i2c, 469 .enable = enable_lvds, 470 .mode = { 471 .name = "Hannstar-XGA", 472 .refresh = 60, 473 .xres = 1024, 474 .yres = 768, 475 .pixclock = 15385, 476 .left_margin = 220, 477 .right_margin = 40, 478 .upper_margin = 21, 479 .lower_margin = 7, 480 .hsync_len = 60, 481 .vsync_len = 10, 482 .sync = FB_SYNC_EXT, 483 .vmode = FB_VMODE_NONINTERLACED 484 } } }; 485 size_t display_count = ARRAY_SIZE(displays); 486 487 static void setup_display(void) 488 { 489 struct mxc_ccm_reg *mxc_ccm = (struct mxc_ccm_reg *)CCM_BASE_ADDR; 490 struct iomuxc *iomux = (struct iomuxc *)IOMUXC_BASE_ADDR; 491 int reg; 492 493 enable_ipu_clock(); 494 imx_setup_hdmi(); 495 /* Turn on LDB0,IPU,IPU DI0 clocks */ 496 reg = __raw_readl(&mxc_ccm->CCGR3); 497 reg |= MXC_CCM_CCGR3_LDB_DI0_MASK; 498 writel(reg, &mxc_ccm->CCGR3); 499 500 /* set LDB0, LDB1 clk select to 011/011 */ 501 reg = readl(&mxc_ccm->cs2cdr); 502 reg &= ~(MXC_CCM_CS2CDR_LDB_DI0_CLK_SEL_MASK 503 |MXC_CCM_CS2CDR_LDB_DI1_CLK_SEL_MASK); 504 reg |= (3<<MXC_CCM_CS2CDR_LDB_DI0_CLK_SEL_OFFSET) 505 |(3<<MXC_CCM_CS2CDR_LDB_DI1_CLK_SEL_OFFSET); 506 writel(reg, &mxc_ccm->cs2cdr); 507 508 reg = readl(&mxc_ccm->cscmr2); 509 reg |= MXC_CCM_CSCMR2_LDB_DI0_IPU_DIV; 510 writel(reg, &mxc_ccm->cscmr2); 511 512 reg = readl(&mxc_ccm->chsccdr); 513 reg |= (CHSCCDR_CLK_SEL_LDB_DI0 514 <<MXC_CCM_CHSCCDR_IPU1_DI0_CLK_SEL_OFFSET); 515 writel(reg, &mxc_ccm->chsccdr); 516 517 reg = IOMUXC_GPR2_BGREF_RRMODE_EXTERNAL_RES 518 |IOMUXC_GPR2_DI1_VS_POLARITY_ACTIVE_HIGH 519 |IOMUXC_GPR2_DI0_VS_POLARITY_ACTIVE_LOW 520 |IOMUXC_GPR2_BIT_MAPPING_CH1_SPWG 521 |IOMUXC_GPR2_DATA_WIDTH_CH1_18BIT 522 |IOMUXC_GPR2_BIT_MAPPING_CH0_SPWG 523 |IOMUXC_GPR2_DATA_WIDTH_CH0_18BIT 524 |IOMUXC_GPR2_LVDS_CH1_MODE_DISABLED 525 |IOMUXC_GPR2_LVDS_CH0_MODE_ENABLED_DI0; 526 writel(reg, &iomux->gpr[2]); 527 528 reg = readl(&iomux->gpr[3]); 529 reg = (reg & ~IOMUXC_GPR3_LVDS0_MUX_CTL_MASK) 530 | (IOMUXC_GPR3_MUX_SRC_IPU1_DI0 531 <<IOMUXC_GPR3_LVDS0_MUX_CTL_OFFSET); 532 writel(reg, &iomux->gpr[3]); 533 534 /* Backlight CABEN on LVDS connector */ 535 SETUP_IOMUX_PAD(PAD_SD2_CLK__GPIO1_IO10 | DIO_PAD_CFG); 536 gpio_direction_output(IMX_GPIO_NR(1, 10), 0); 537 } 538 #endif /* CONFIG_VIDEO_IPUV3 */ 539 540 /* 541 * Baseboard specific GPIO 542 */ 543 544 /* common to add baseboards */ 545 static iomux_v3_cfg_t const gw_gpio_pads[] = { 546 /* MSATA_EN */ 547 IOMUX_PADS(PAD_SD4_DAT0__GPIO2_IO08 | DIO_PAD_CFG), 548 /* RS232_EN# */ 549 IOMUX_PADS(PAD_SD4_DAT3__GPIO2_IO11 | DIO_PAD_CFG), 550 }; 551 552 /* prototype */ 553 static iomux_v3_cfg_t const gwproto_gpio_pads[] = { 554 /* PANLEDG# */ 555 IOMUX_PADS(PAD_KEY_COL0__GPIO4_IO06 | DIO_PAD_CFG), 556 /* PANLEDR# */ 557 IOMUX_PADS(PAD_KEY_ROW0__GPIO4_IO07 | DIO_PAD_CFG), 558 /* LOCLED# */ 559 IOMUX_PADS(PAD_KEY_ROW4__GPIO4_IO15 | DIO_PAD_CFG), 560 /* RS485_EN */ 561 IOMUX_PADS(PAD_SD3_DAT4__GPIO7_IO01 | DIO_PAD_CFG), 562 /* IOEXP_PWREN# */ 563 IOMUX_PADS(PAD_EIM_A19__GPIO2_IO19 | DIO_PAD_CFG), 564 /* IOEXP_IRQ# */ 565 IOMUX_PADS(PAD_EIM_A20__GPIO2_IO18 | MUX_PAD_CTRL(IRQ_PAD_CTRL)), 566 /* VID_EN */ 567 IOMUX_PADS(PAD_EIM_D31__GPIO3_IO31 | DIO_PAD_CFG), 568 /* DIOI2C_DIS# */ 569 IOMUX_PADS(PAD_GPIO_19__GPIO4_IO05 | DIO_PAD_CFG), 570 /* PCICK_SSON */ 571 IOMUX_PADS(PAD_SD1_CLK__GPIO1_IO20 | DIO_PAD_CFG), 572 /* PCI_RST# */ 573 IOMUX_PADS(PAD_ENET_TXD1__GPIO1_IO29 | DIO_PAD_CFG), 574 }; 575 576 static iomux_v3_cfg_t const gw51xx_gpio_pads[] = { 577 /* PANLEDG# */ 578 IOMUX_PADS(PAD_KEY_COL0__GPIO4_IO06 | DIO_PAD_CFG), 579 /* PANLEDR# */ 580 IOMUX_PADS(PAD_KEY_ROW0__GPIO4_IO07 | DIO_PAD_CFG), 581 /* IOEXP_PWREN# */ 582 IOMUX_PADS(PAD_EIM_A19__GPIO2_IO19 | DIO_PAD_CFG), 583 /* IOEXP_IRQ# */ 584 IOMUX_PADS(PAD_EIM_A20__GPIO2_IO18 | MUX_PAD_CTRL(IRQ_PAD_CTRL)), 585 586 /* GPS_SHDN */ 587 IOMUX_PADS(PAD_GPIO_2__GPIO1_IO02 | DIO_PAD_CFG), 588 /* VID_PWR */ 589 IOMUX_PADS(PAD_CSI0_DATA_EN__GPIO5_IO20 | DIO_PAD_CFG), 590 /* PCI_RST# */ 591 IOMUX_PADS(PAD_GPIO_0__GPIO1_IO00 | DIO_PAD_CFG), 592 /* PCIESKT_WDIS# */ 593 IOMUX_PADS(PAD_GPIO_17__GPIO7_IO12 | DIO_PAD_CFG), 594 }; 595 596 static iomux_v3_cfg_t const gw52xx_gpio_pads[] = { 597 /* PANLEDG# */ 598 IOMUX_PADS(PAD_KEY_COL0__GPIO4_IO06 | DIO_PAD_CFG), 599 /* PANLEDR# */ 600 IOMUX_PADS(PAD_KEY_ROW0__GPIO4_IO07 | DIO_PAD_CFG), 601 /* IOEXP_PWREN# */ 602 IOMUX_PADS(PAD_EIM_A19__GPIO2_IO19 | DIO_PAD_CFG), 603 /* IOEXP_IRQ# */ 604 IOMUX_PADS(PAD_EIM_A20__GPIO2_IO18 | MUX_PAD_CTRL(IRQ_PAD_CTRL)), 605 606 /* MX6_LOCLED# */ 607 IOMUX_PADS(PAD_KEY_ROW4__GPIO4_IO15 | DIO_PAD_CFG), 608 /* GPS_SHDN */ 609 IOMUX_PADS(PAD_ENET_RXD0__GPIO1_IO27 | DIO_PAD_CFG), 610 /* USBOTG_SEL */ 611 IOMUX_PADS(PAD_GPIO_2__GPIO1_IO02 | DIO_PAD_CFG), 612 /* VID_PWR */ 613 IOMUX_PADS(PAD_EIM_D31__GPIO3_IO31 | DIO_PAD_CFG), 614 /* PCI_RST# */ 615 IOMUX_PADS(PAD_ENET_TXD1__GPIO1_IO29 | DIO_PAD_CFG), 616 /* PCIESKT_WDIS# */ 617 IOMUX_PADS(PAD_GPIO_17__GPIO7_IO12 | DIO_PAD_CFG), 618 }; 619 620 static iomux_v3_cfg_t const gw53xx_gpio_pads[] = { 621 /* PANLEDG# */ 622 IOMUX_PADS(PAD_KEY_COL0__GPIO4_IO06 | DIO_PAD_CFG), 623 /* PANLEDR# */ 624 IOMUX_PADS(PAD_KEY_ROW0__GPIO4_IO07 | DIO_PAD_CFG), 625 /* MX6_LOCLED# */ 626 IOMUX_PADS(PAD_KEY_ROW4__GPIO4_IO15 | DIO_PAD_CFG), 627 /* IOEXP_PWREN# */ 628 IOMUX_PADS(PAD_EIM_A19__GPIO2_IO19 | DIO_PAD_CFG), 629 /* IOEXP_IRQ# */ 630 IOMUX_PADS(PAD_EIM_A20__GPIO2_IO18 | MUX_PAD_CTRL(IRQ_PAD_CTRL)), 631 /* DIOI2C_DIS# */ 632 IOMUX_PADS(PAD_GPIO_19__GPIO4_IO05 | DIO_PAD_CFG), 633 /* GPS_SHDN */ 634 IOMUX_PADS(PAD_ENET_RXD0__GPIO1_IO27 | DIO_PAD_CFG), 635 /* VID_EN */ 636 IOMUX_PADS(PAD_EIM_D31__GPIO3_IO31 | DIO_PAD_CFG), 637 /* PCI_RST# */ 638 IOMUX_PADS(PAD_ENET_TXD1__GPIO1_IO29 | DIO_PAD_CFG), 639 /* PCIESKT_WDIS# */ 640 IOMUX_PADS(PAD_GPIO_17__GPIO7_IO12 | DIO_PAD_CFG), 641 }; 642 643 static iomux_v3_cfg_t const gw54xx_gpio_pads[] = { 644 /* PANLEDG# */ 645 IOMUX_PADS(PAD_KEY_COL0__GPIO4_IO06 | DIO_PAD_CFG), 646 /* PANLEDR# */ 647 IOMUX_PADS(PAD_KEY_COL2__GPIO4_IO10 | DIO_PAD_CFG), 648 /* MX6_LOCLED# */ 649 IOMUX_PADS(PAD_KEY_ROW4__GPIO4_IO15 | DIO_PAD_CFG), 650 /* MIPI_DIO */ 651 IOMUX_PADS(PAD_SD1_DAT3__GPIO1_IO21 | DIO_PAD_CFG), 652 /* RS485_EN */ 653 IOMUX_PADS(PAD_EIM_D24__GPIO3_IO24 | DIO_PAD_CFG), 654 /* IOEXP_PWREN# */ 655 IOMUX_PADS(PAD_KEY_ROW0__GPIO4_IO07 | DIO_PAD_CFG), 656 /* IOEXP_IRQ# */ 657 IOMUX_PADS(PAD_KEY_ROW1__GPIO4_IO09 | MUX_PAD_CTRL(IRQ_PAD_CTRL)), 658 /* DIOI2C_DIS# */ 659 IOMUX_PADS(PAD_GPIO_19__GPIO4_IO05 | DIO_PAD_CFG), 660 /* PCICK_SSON */ 661 IOMUX_PADS(PAD_SD1_CLK__GPIO1_IO20 | DIO_PAD_CFG), 662 /* PCI_RST# */ 663 IOMUX_PADS(PAD_ENET_TXD1__GPIO1_IO29 | DIO_PAD_CFG), 664 /* VID_EN */ 665 IOMUX_PADS(PAD_EIM_D31__GPIO3_IO31 | DIO_PAD_CFG), 666 /* PCIESKT_WDIS# */ 667 IOMUX_PADS(PAD_DISP0_DAT23__GPIO5_IO17 | DIO_PAD_CFG), 668 }; 669 670 static iomux_v3_cfg_t const gw552x_gpio_pads[] = { 671 /* PANLEDG# */ 672 IOMUX_PADS(PAD_KEY_COL0__GPIO4_IO06 | DIO_PAD_CFG), 673 /* PANLEDR# */ 674 IOMUX_PADS(PAD_KEY_ROW0__GPIO4_IO07 | DIO_PAD_CFG), 675 /* MX6_LOCLED# */ 676 IOMUX_PADS(PAD_KEY_ROW4__GPIO4_IO15 | DIO_PAD_CFG), 677 /* PCI_RST# */ 678 IOMUX_PADS(PAD_ENET_TXD1__GPIO1_IO29 | DIO_PAD_CFG), 679 /* MX6_DIO[4:9] */ 680 IOMUX_PADS(PAD_CSI0_PIXCLK__GPIO5_IO18 | DIO_PAD_CFG), 681 IOMUX_PADS(PAD_CSI0_DATA_EN__GPIO5_IO20 | DIO_PAD_CFG), 682 IOMUX_PADS(PAD_CSI0_VSYNC__GPIO5_IO21 | DIO_PAD_CFG), 683 IOMUX_PADS(PAD_CSI0_DAT4__GPIO5_IO22 | DIO_PAD_CFG), 684 IOMUX_PADS(PAD_CSI0_DAT5__GPIO5_IO23 | DIO_PAD_CFG), 685 IOMUX_PADS(PAD_CSI0_DAT7__GPIO5_IO25 | DIO_PAD_CFG), 686 /* PCIEGBE1_OFF# */ 687 IOMUX_PADS(PAD_GPIO_1__GPIO1_IO01 | DIO_PAD_CFG), 688 /* PCIEGBE2_OFF# */ 689 IOMUX_PADS(PAD_GPIO_2__GPIO1_IO02 | DIO_PAD_CFG), 690 /* PCIESKT_WDIS# */ 691 IOMUX_PADS(PAD_GPIO_17__GPIO7_IO12 | DIO_PAD_CFG), 692 }; 693 694 /* 695 * each baseboard has 4 user configurable Digital IO lines which can 696 * be pinmuxed as a GPIO or in some cases a PWM 697 */ 698 struct dio_cfg { 699 iomux_v3_cfg_t gpio_padmux[2]; 700 unsigned gpio_param; 701 iomux_v3_cfg_t pwm_padmux[2]; 702 unsigned pwm_param; 703 }; 704 705 struct ventana { 706 /* pinmux */ 707 iomux_v3_cfg_t const *gpio_pads; 708 int num_pads; 709 /* DIO pinmux/val */ 710 struct dio_cfg dio_cfg[4]; 711 /* various gpios (0 if non-existent) */ 712 int leds[3]; 713 int pcie_rst; 714 int mezz_pwren; 715 int mezz_irq; 716 int rs485en; 717 int gps_shdn; 718 int vidin_en; 719 int dioi2c_en; 720 int pcie_sson; 721 int usb_sel; 722 int wdis; 723 }; 724 725 struct ventana gpio_cfg[] = { 726 /* GW5400proto */ 727 { 728 .gpio_pads = gw54xx_gpio_pads, 729 .num_pads = ARRAY_SIZE(gw54xx_gpio_pads)/2, 730 .dio_cfg = { 731 { 732 { IOMUX_PADS(PAD_GPIO_9__GPIO1_IO09) }, 733 IMX_GPIO_NR(1, 9), 734 { IOMUX_PADS(PAD_GPIO_9__PWM1_OUT) }, 735 1 736 }, 737 { 738 { IOMUX_PADS(PAD_SD1_DAT2__GPIO1_IO19) }, 739 IMX_GPIO_NR(1, 19), 740 { IOMUX_PADS(PAD_SD1_DAT2__PWM2_OUT) }, 741 2 742 }, 743 { 744 { IOMUX_PADS(PAD_SD4_DAT1__GPIO2_IO09) }, 745 IMX_GPIO_NR(2, 9), 746 { IOMUX_PADS(PAD_SD4_DAT1__PWM3_OUT) }, 747 3 748 }, 749 { 750 { IOMUX_PADS(PAD_SD4_DAT2__GPIO2_IO10) }, 751 IMX_GPIO_NR(2, 10), 752 { IOMUX_PADS(PAD_SD4_DAT2__PWM4_OUT) }, 753 4 754 }, 755 }, 756 .leds = { 757 IMX_GPIO_NR(4, 6), 758 IMX_GPIO_NR(4, 10), 759 IMX_GPIO_NR(4, 15), 760 }, 761 .pcie_rst = IMX_GPIO_NR(1, 29), 762 .mezz_pwren = IMX_GPIO_NR(4, 7), 763 .mezz_irq = IMX_GPIO_NR(4, 9), 764 .rs485en = IMX_GPIO_NR(3, 24), 765 .dioi2c_en = IMX_GPIO_NR(4, 5), 766 .pcie_sson = IMX_GPIO_NR(1, 20), 767 }, 768 769 /* GW51xx */ 770 { 771 .gpio_pads = gw51xx_gpio_pads, 772 .num_pads = ARRAY_SIZE(gw51xx_gpio_pads)/2, 773 .dio_cfg = { 774 { 775 { IOMUX_PADS(PAD_SD1_DAT0__GPIO1_IO16) }, 776 IMX_GPIO_NR(1, 16), 777 { 0, 0 }, 778 0 779 }, 780 { 781 { IOMUX_PADS(PAD_SD1_DAT2__GPIO1_IO19) }, 782 IMX_GPIO_NR(1, 19), 783 { IOMUX_PADS(PAD_SD1_DAT2__PWM2_OUT) }, 784 2 785 }, 786 { 787 { IOMUX_PADS(PAD_SD1_DAT1__GPIO1_IO17) }, 788 IMX_GPIO_NR(1, 17), 789 { IOMUX_PADS(PAD_SD1_DAT1__PWM3_OUT) }, 790 3 791 }, 792 { 793 { IOMUX_PADS(PAD_SD1_CMD__GPIO1_IO18) }, 794 IMX_GPIO_NR(1, 18), 795 { IOMUX_PADS(PAD_SD1_CMD__PWM4_OUT) }, 796 4 797 }, 798 }, 799 .leds = { 800 IMX_GPIO_NR(4, 6), 801 IMX_GPIO_NR(4, 10), 802 }, 803 .pcie_rst = IMX_GPIO_NR(1, 0), 804 .mezz_pwren = IMX_GPIO_NR(2, 19), 805 .mezz_irq = IMX_GPIO_NR(2, 18), 806 .gps_shdn = IMX_GPIO_NR(1, 2), 807 .vidin_en = IMX_GPIO_NR(5, 20), 808 .wdis = IMX_GPIO_NR(7, 12), 809 }, 810 811 /* GW52xx */ 812 { 813 .gpio_pads = gw52xx_gpio_pads, 814 .num_pads = ARRAY_SIZE(gw52xx_gpio_pads)/2, 815 .dio_cfg = { 816 { 817 { IOMUX_PADS(PAD_SD1_DAT0__GPIO1_IO16) }, 818 IMX_GPIO_NR(1, 16), 819 { 0, 0 }, 820 0 821 }, 822 { 823 { IOMUX_PADS(PAD_SD1_DAT2__GPIO1_IO19) }, 824 IMX_GPIO_NR(1, 19), 825 { IOMUX_PADS(PAD_SD1_DAT2__PWM2_OUT) }, 826 2 827 }, 828 { 829 { IOMUX_PADS(PAD_SD1_DAT1__GPIO1_IO17) }, 830 IMX_GPIO_NR(1, 17), 831 { IOMUX_PADS(PAD_SD1_DAT1__PWM3_OUT) }, 832 3 833 }, 834 { 835 { IOMUX_PADS(PAD_SD1_CLK__GPIO1_IO20) }, 836 IMX_GPIO_NR(1, 20), 837 { 0, 0 }, 838 0 839 }, 840 }, 841 .leds = { 842 IMX_GPIO_NR(4, 6), 843 IMX_GPIO_NR(4, 7), 844 IMX_GPIO_NR(4, 15), 845 }, 846 .pcie_rst = IMX_GPIO_NR(1, 29), 847 .mezz_pwren = IMX_GPIO_NR(2, 19), 848 .mezz_irq = IMX_GPIO_NR(2, 18), 849 .gps_shdn = IMX_GPIO_NR(1, 27), 850 .vidin_en = IMX_GPIO_NR(3, 31), 851 .usb_sel = IMX_GPIO_NR(1, 2), 852 .wdis = IMX_GPIO_NR(7, 12), 853 }, 854 855 /* GW53xx */ 856 { 857 .gpio_pads = gw53xx_gpio_pads, 858 .num_pads = ARRAY_SIZE(gw53xx_gpio_pads)/2, 859 .dio_cfg = { 860 { 861 { IOMUX_PADS(PAD_SD1_DAT0__GPIO1_IO16) }, 862 IMX_GPIO_NR(1, 16), 863 { 0, 0 }, 864 0 865 }, 866 { 867 { IOMUX_PADS(PAD_SD1_DAT2__GPIO1_IO19) }, 868 IMX_GPIO_NR(1, 19), 869 { IOMUX_PADS(PAD_SD1_DAT2__PWM2_OUT) }, 870 2 871 }, 872 { 873 { IOMUX_PADS(PAD_SD1_DAT1__GPIO1_IO17) }, 874 IMX_GPIO_NR(1, 17), 875 { IOMUX_PADS(PAD_SD1_DAT1__PWM3_OUT) }, 876 3 877 }, 878 { 879 {IOMUX_PADS(PAD_SD1_CLK__GPIO1_IO20) }, 880 IMX_GPIO_NR(1, 20), 881 { 0, 0 }, 882 0 883 }, 884 }, 885 .leds = { 886 IMX_GPIO_NR(4, 6), 887 IMX_GPIO_NR(4, 7), 888 IMX_GPIO_NR(4, 15), 889 }, 890 .pcie_rst = IMX_GPIO_NR(1, 29), 891 .mezz_pwren = IMX_GPIO_NR(2, 19), 892 .mezz_irq = IMX_GPIO_NR(2, 18), 893 .gps_shdn = IMX_GPIO_NR(1, 27), 894 .vidin_en = IMX_GPIO_NR(3, 31), 895 .wdis = IMX_GPIO_NR(7, 12), 896 }, 897 898 /* GW54xx */ 899 { 900 .gpio_pads = gw54xx_gpio_pads, 901 .num_pads = ARRAY_SIZE(gw54xx_gpio_pads)/2, 902 .dio_cfg = { 903 { 904 { IOMUX_PADS(PAD_GPIO_9__GPIO1_IO09) }, 905 IMX_GPIO_NR(1, 9), 906 { IOMUX_PADS(PAD_GPIO_9__PWM1_OUT) }, 907 1 908 }, 909 { 910 { IOMUX_PADS(PAD_SD1_DAT2__GPIO1_IO19) }, 911 IMX_GPIO_NR(1, 19), 912 { IOMUX_PADS(PAD_SD1_DAT2__PWM2_OUT) }, 913 2 914 }, 915 { 916 { IOMUX_PADS(PAD_SD4_DAT1__GPIO2_IO09) }, 917 IMX_GPIO_NR(2, 9), 918 { IOMUX_PADS(PAD_SD4_DAT1__PWM3_OUT) }, 919 3 920 }, 921 { 922 { IOMUX_PADS(PAD_SD4_DAT2__GPIO2_IO10) }, 923 IMX_GPIO_NR(2, 10), 924 { IOMUX_PADS(PAD_SD4_DAT2__PWM4_OUT) }, 925 4 926 }, 927 }, 928 .leds = { 929 IMX_GPIO_NR(4, 6), 930 IMX_GPIO_NR(4, 7), 931 IMX_GPIO_NR(4, 15), 932 }, 933 .pcie_rst = IMX_GPIO_NR(1, 29), 934 .mezz_pwren = IMX_GPIO_NR(2, 19), 935 .mezz_irq = IMX_GPIO_NR(2, 18), 936 .rs485en = IMX_GPIO_NR(7, 1), 937 .vidin_en = IMX_GPIO_NR(3, 31), 938 .dioi2c_en = IMX_GPIO_NR(4, 5), 939 .pcie_sson = IMX_GPIO_NR(1, 20), 940 .wdis = IMX_GPIO_NR(5, 17), 941 }, 942 943 /* GW552x */ 944 { 945 .gpio_pads = gw552x_gpio_pads, 946 .num_pads = ARRAY_SIZE(gw552x_gpio_pads)/2, 947 .dio_cfg = { 948 { 949 { IOMUX_PADS(PAD_SD1_DAT0__GPIO1_IO16) }, 950 IMX_GPIO_NR(1, 16), 951 { 0, 0 }, 952 0 953 }, 954 { 955 { IOMUX_PADS(PAD_SD1_DAT2__GPIO1_IO19) }, 956 IMX_GPIO_NR(1, 19), 957 { IOMUX_PADS(PAD_SD1_DAT2__PWM2_OUT) }, 958 2 959 }, 960 { 961 { IOMUX_PADS(PAD_SD1_DAT1__GPIO1_IO17) }, 962 IMX_GPIO_NR(1, 17), 963 { IOMUX_PADS(PAD_SD1_DAT1__PWM3_OUT) }, 964 3 965 }, 966 { 967 { IOMUX_PADS(PAD_SD1_CLK__GPIO1_IO20) }, 968 IMX_GPIO_NR(2, 10), 969 { 0, 0 }, 970 0 971 }, 972 }, 973 .leds = { 974 IMX_GPIO_NR(4, 6), 975 IMX_GPIO_NR(4, 7), 976 IMX_GPIO_NR(4, 15), 977 }, 978 .pcie_rst = IMX_GPIO_NR(1, 29), 979 }, 980 }; 981 982 /* setup board specific PMIC */ 983 int power_init_board(void) 984 { 985 struct pmic *p; 986 u32 reg; 987 988 /* configure PFUZE100 PMIC */ 989 if (board_type == GW54xx || board_type == GW54proto) { 990 power_pfuze100_init(CONFIG_I2C_PMIC); 991 p = pmic_get("PFUZE100"); 992 if (p && !pmic_probe(p)) { 993 pmic_reg_read(p, PFUZE100_DEVICEID, ®); 994 printf("PMIC: PFUZE100 ID=0x%02x\n", reg); 995 996 /* Set VGEN1 to 1.5V and enable */ 997 pmic_reg_read(p, PFUZE100_VGEN1VOL, ®); 998 reg &= ~(LDO_VOL_MASK); 999 reg |= (LDOA_1_50V | LDO_EN); 1000 pmic_reg_write(p, PFUZE100_VGEN1VOL, reg); 1001 1002 /* Set SWBST to 5.0V and enable */ 1003 pmic_reg_read(p, PFUZE100_SWBSTCON1, ®); 1004 reg &= ~(SWBST_MODE_MASK | SWBST_VOL_MASK); 1005 reg |= (SWBST_5_00V | SWBST_MODE_AUTO); 1006 pmic_reg_write(p, PFUZE100_SWBSTCON1, reg); 1007 } 1008 } 1009 1010 /* configure LTC3676 PMIC */ 1011 else { 1012 power_ltc3676_init(CONFIG_I2C_PMIC); 1013 p = pmic_get("LTC3676_PMIC"); 1014 if (p && !pmic_probe(p)) { 1015 puts("PMIC: LTC3676\n"); 1016 /* set board-specific scalar to 1225mV for IMX6Q@1GHz */ 1017 if (is_cpu_type(MXC_CPU_MX6Q)) { 1018 /* mask PGOOD during SW1 transition */ 1019 reg = 0x1d | LTC3676_PGOOD_MASK; 1020 pmic_reg_write(p, LTC3676_DVB1B, reg); 1021 /* set SW1 (VDD_SOC) to 1259mV */ 1022 reg = 0x1d; 1023 pmic_reg_write(p, LTC3676_DVB1A, reg); 1024 1025 /* mask PGOOD during SW3 transition */ 1026 reg = 0x1d | LTC3676_PGOOD_MASK; 1027 pmic_reg_write(p, LTC3676_DVB3B, reg); 1028 /*set SW3 (VDD_ARM) to 1259mV */ 1029 reg = 0x1d; 1030 pmic_reg_write(p, LTC3676_DVB3A, reg); 1031 } 1032 } 1033 } 1034 1035 return 0; 1036 } 1037 1038 /* setup GPIO pinmux and default configuration per baseboard */ 1039 static void setup_board_gpio(int board) 1040 { 1041 struct ventana_board_info *info = &ventana_info; 1042 const char *s; 1043 char arg[10]; 1044 size_t len; 1045 int i; 1046 int quiet = simple_strtol(getenv("quiet"), NULL, 10); 1047 1048 if (board >= GW_UNKNOWN) 1049 return; 1050 1051 /* RS232_EN# */ 1052 gpio_direction_output(GP_RS232_EN, (hwconfig("rs232")) ? 0 : 1); 1053 1054 /* MSATA Enable */ 1055 if (is_cpu_type(MXC_CPU_MX6Q) && 1056 test_bit(EECONFIG_SATA, info->config)) { 1057 gpio_direction_output(GP_MSATA_SEL, 1058 (hwconfig("msata")) ? 1 : 0); 1059 } else { 1060 gpio_direction_output(GP_MSATA_SEL, 0); 1061 } 1062 1063 #if !defined(CONFIG_CMD_PCI) 1064 /* assert PCI_RST# (released by OS when clock is valid) */ 1065 gpio_direction_output(gpio_cfg[board].pcie_rst, 0); 1066 #endif 1067 1068 /* turn off (active-high) user LED's */ 1069 for (i = 0; i < ARRAY_SIZE(gpio_cfg[board].leds); i++) { 1070 if (gpio_cfg[board].leds[i]) 1071 gpio_direction_output(gpio_cfg[board].leds[i], 1); 1072 } 1073 1074 /* Expansion Mezzanine IO */ 1075 if (gpio_cfg[board].mezz_pwren) 1076 gpio_direction_output(gpio_cfg[board].mezz_pwren, 0); 1077 if (gpio_cfg[board].mezz_irq) 1078 gpio_direction_input(gpio_cfg[board].mezz_irq); 1079 1080 /* RS485 Transmit Enable */ 1081 if (gpio_cfg[board].rs485en) 1082 gpio_direction_output(gpio_cfg[board].rs485en, 0); 1083 1084 /* GPS_SHDN */ 1085 if (gpio_cfg[board].gps_shdn) 1086 gpio_direction_output(gpio_cfg[board].gps_shdn, 1); 1087 1088 /* Analog video codec power enable */ 1089 if (gpio_cfg[board].vidin_en) 1090 gpio_direction_output(gpio_cfg[board].vidin_en, 1); 1091 1092 /* DIOI2C_DIS# */ 1093 if (gpio_cfg[board].dioi2c_en) 1094 gpio_direction_output(gpio_cfg[board].dioi2c_en, 0); 1095 1096 /* PCICK_SSON: disable spread-spectrum clock */ 1097 if (gpio_cfg[board].pcie_sson) 1098 gpio_direction_output(gpio_cfg[board].pcie_sson, 0); 1099 1100 /* USBOTG Select (PCISKT or FrontPanel) */ 1101 if (gpio_cfg[board].usb_sel) 1102 gpio_direction_output(gpio_cfg[board].usb_sel, 0); 1103 1104 /* PCISKT_WDIS# (Wireless disable GPIO to miniPCIe sockets) */ 1105 if (gpio_cfg[board].wdis) 1106 gpio_direction_output(gpio_cfg[board].wdis, 1); 1107 1108 /* 1109 * Configure DIO pinmux/padctl registers 1110 * see IMX6DQRM/IMX6SDLRM IOMUXC_SW_PAD_CTL_PAD_* register definitions 1111 */ 1112 for (i = 0; i < 4; i++) { 1113 struct dio_cfg *cfg = &gpio_cfg[board].dio_cfg[i]; 1114 iomux_v3_cfg_t ctrl = DIO_PAD_CFG; 1115 unsigned cputype = is_cpu_type(MXC_CPU_MX6Q) ? 0 : 1; 1116 1117 sprintf(arg, "dio%d", i); 1118 if (!hwconfig(arg)) 1119 continue; 1120 s = hwconfig_subarg(arg, "padctrl", &len); 1121 if (s) { 1122 ctrl = MUX_PAD_CTRL(simple_strtoul(s, NULL, 16) 1123 & 0x1ffff) | MUX_MODE_SION; 1124 } 1125 if (hwconfig_subarg_cmp(arg, "mode", "gpio")) { 1126 if (!quiet) { 1127 printf("DIO%d: GPIO%d_IO%02d (gpio-%d)\n", i, 1128 (cfg->gpio_param/32)+1, 1129 cfg->gpio_param%32, 1130 cfg->gpio_param); 1131 } 1132 imx_iomux_v3_setup_pad(cfg->gpio_padmux[cputype] | 1133 ctrl); 1134 gpio_direction_input(cfg->gpio_param); 1135 } else if (hwconfig_subarg_cmp("dio2", "mode", "pwm") && 1136 cfg->pwm_padmux) { 1137 if (!quiet) 1138 printf("DIO%d: pwm%d\n", i, cfg->pwm_param); 1139 imx_iomux_v3_setup_pad(cfg->pwm_padmux[cputype] | 1140 MUX_PAD_CTRL(ctrl)); 1141 } 1142 } 1143 1144 if (!quiet) { 1145 if (is_cpu_type(MXC_CPU_MX6Q) && 1146 (test_bit(EECONFIG_SATA, info->config))) { 1147 printf("MSATA: %s\n", (hwconfig("msata") ? 1148 "enabled" : "disabled")); 1149 } 1150 printf("RS232: %s\n", (hwconfig("rs232")) ? 1151 "enabled" : "disabled"); 1152 } 1153 } 1154 1155 #if defined(CONFIG_CMD_PCI) 1156 int imx6_pcie_toggle_reset(void) 1157 { 1158 if (board_type < GW_UNKNOWN) { 1159 uint pin = gpio_cfg[board_type].pcie_rst; 1160 gpio_direction_output(pin, 0); 1161 mdelay(50); 1162 gpio_direction_output(pin, 1); 1163 } 1164 return 0; 1165 } 1166 1167 /* 1168 * Most Ventana boards have a PLX PEX860x PCIe switch onboard and use its 1169 * GPIO's as PERST# signals for its downstream ports - configure the GPIO's 1170 * properly and assert reset for 100ms. 1171 */ 1172 void board_pci_fixup_dev(struct pci_controller *hose, pci_dev_t dev, 1173 unsigned short vendor, unsigned short device, 1174 unsigned short class) 1175 { 1176 u32 dw; 1177 1178 debug("%s: %02d:%02d.%02d: %04x:%04x\n", __func__, 1179 PCI_BUS(dev), PCI_DEV(dev), PCI_FUNC(dev), vendor, device); 1180 if (vendor == PCI_VENDOR_ID_PLX && 1181 (device & 0xfff0) == 0x8600 && 1182 PCI_DEV(dev) == 0 && PCI_FUNC(dev) == 0) { 1183 debug("configuring PLX 860X downstream PERST#\n"); 1184 pci_hose_read_config_dword(hose, dev, 0x62c, &dw); 1185 dw |= 0xaaa8; /* GPIO1-7 outputs */ 1186 pci_hose_write_config_dword(hose, dev, 0x62c, dw); 1187 1188 pci_hose_read_config_dword(hose, dev, 0x644, &dw); 1189 dw |= 0xfe; /* GPIO1-7 output high */ 1190 pci_hose_write_config_dword(hose, dev, 0x644, dw); 1191 1192 mdelay(100); 1193 } 1194 } 1195 #endif /* CONFIG_CMD_PCI */ 1196 1197 #ifdef CONFIG_SERIAL_TAG 1198 /* 1199 * called when setting up ATAGS before booting kernel 1200 * populate serialnum from the following (in order of priority): 1201 * serial# env var 1202 * eeprom 1203 */ 1204 void get_board_serial(struct tag_serialnr *serialnr) 1205 { 1206 char *serial = getenv("serial#"); 1207 1208 if (serial) { 1209 serialnr->high = 0; 1210 serialnr->low = simple_strtoul(serial, NULL, 10); 1211 } else if (ventana_info.model[0]) { 1212 serialnr->high = 0; 1213 serialnr->low = ventana_info.serial; 1214 } else { 1215 serialnr->high = 0; 1216 serialnr->low = 0; 1217 } 1218 } 1219 #endif 1220 1221 /* 1222 * Board Support 1223 */ 1224 1225 /* called from SPL board_init_f() */ 1226 int board_early_init_f(void) 1227 { 1228 setup_iomux_uart(); 1229 gpio_direction_output(GP_USB_OTG_PWR, 0); /* OTG power off */ 1230 1231 #if defined(CONFIG_VIDEO_IPUV3) 1232 setup_display(); 1233 #endif 1234 return 0; 1235 } 1236 1237 int dram_init(void) 1238 { 1239 gd->ram_size = imx_ddr_size(); 1240 return 0; 1241 } 1242 1243 int board_init(void) 1244 { 1245 struct iomuxc *const iomuxc_regs = (struct iomuxc *)IOMUXC_BASE_ADDR; 1246 1247 clrsetbits_le32(&iomuxc_regs->gpr[1], 1248 IOMUXC_GPR1_OTG_ID_MASK, 1249 IOMUXC_GPR1_OTG_ID_GPIO1); 1250 1251 /* address of linux boot parameters */ 1252 gd->bd->bi_boot_params = PHYS_SDRAM + 0x100; 1253 1254 #ifdef CONFIG_CMD_NAND 1255 setup_gpmi_nand(); 1256 #endif 1257 #ifdef CONFIG_MXC_SPI 1258 setup_spi(); 1259 #endif 1260 if (is_cpu_type(MXC_CPU_MX6Q)) { 1261 setup_i2c(0, CONFIG_SYS_I2C_SPEED, 0x7f, &mx6q_i2c_pad_info0); 1262 setup_i2c(1, CONFIG_SYS_I2C_SPEED, 0x7f, &mx6q_i2c_pad_info1); 1263 setup_i2c(2, CONFIG_SYS_I2C_SPEED, 0x7f, &mx6q_i2c_pad_info2); 1264 } else { 1265 setup_i2c(0, CONFIG_SYS_I2C_SPEED, 0x7f, &mx6dl_i2c_pad_info0); 1266 setup_i2c(1, CONFIG_SYS_I2C_SPEED, 0x7f, &mx6dl_i2c_pad_info1); 1267 setup_i2c(2, CONFIG_SYS_I2C_SPEED, 0x7f, &mx6dl_i2c_pad_info2); 1268 } 1269 1270 #ifdef CONFIG_CMD_SATA 1271 setup_sata(); 1272 #endif 1273 /* read Gateworks EEPROM into global struct (used later) */ 1274 board_type = read_eeprom(CONFIG_I2C_GSC, &ventana_info); 1275 1276 /* board-specifc GPIO iomux */ 1277 SETUP_IOMUX_PADS(gw_gpio_pads); 1278 if (board_type < GW_UNKNOWN) { 1279 iomux_v3_cfg_t const *p = gpio_cfg[board_type].gpio_pads; 1280 int count = gpio_cfg[board_type].num_pads; 1281 1282 imx_iomux_v3_setup_multiple_pads(p, count); 1283 } 1284 1285 return 0; 1286 } 1287 1288 #if defined(CONFIG_DISPLAY_BOARDINFO_LATE) 1289 /* 1290 * called during late init (after relocation and after board_init()) 1291 * by virtue of CONFIG_DISPLAY_BOARDINFO_LATE as we needed i2c initialized and 1292 * EEPROM read. 1293 */ 1294 int checkboard(void) 1295 { 1296 struct ventana_board_info *info = &ventana_info; 1297 unsigned char buf[4]; 1298 const char *p; 1299 int quiet; /* Quiet or minimal output mode */ 1300 1301 quiet = 0; 1302 p = getenv("quiet"); 1303 if (p) 1304 quiet = simple_strtol(p, NULL, 10); 1305 else 1306 setenv("quiet", "0"); 1307 1308 puts("\nGateworks Corporation Copyright 2014\n"); 1309 if (info->model[0]) { 1310 printf("Model: %s\n", info->model); 1311 printf("MFGDate: %02x-%02x-%02x%02x\n", 1312 info->mfgdate[0], info->mfgdate[1], 1313 info->mfgdate[2], info->mfgdate[3]); 1314 printf("Serial:%d\n", info->serial); 1315 } else { 1316 puts("Invalid EEPROM - board will not function fully\n"); 1317 } 1318 if (quiet) 1319 return 0; 1320 1321 /* Display GSC firmware revision/CRC/status */ 1322 i2c_set_bus_num(CONFIG_I2C_GSC); 1323 if (!gsc_i2c_read(GSC_SC_ADDR, GSC_SC_FWVER, 1, buf, 1)) { 1324 printf("GSC: v%d", buf[0]); 1325 if (!gsc_i2c_read(GSC_SC_ADDR, GSC_SC_STATUS, 1, buf, 4)) { 1326 printf(" 0x%04x", buf[2] | buf[3]<<8); /* CRC */ 1327 printf(" 0x%02x", buf[0]); /* irq status */ 1328 } 1329 puts("\n"); 1330 } 1331 /* Display RTC */ 1332 if (!gsc_i2c_read(GSC_RTC_ADDR, 0x00, 1, buf, 4)) { 1333 printf("RTC: %d\n", 1334 buf[0] | buf[1]<<8 | buf[2]<<16 | buf[3]<<24); 1335 } 1336 1337 return 0; 1338 } 1339 #endif 1340 1341 #ifdef CONFIG_CMD_BMODE 1342 /* 1343 * BOOT_CFG1, BOOT_CFG2, BOOT_CFG3, BOOT_CFG4 1344 * see Table 8-11 and Table 5-9 1345 * BOOT_CFG1[7] = 1 (boot from NAND) 1346 * BOOT_CFG1[5] = 0 - raw NAND 1347 * BOOT_CFG1[4] = 0 - default pad settings 1348 * BOOT_CFG1[3:2] = 00 - devices = 1 1349 * BOOT_CFG1[1:0] = 00 - Row Address Cycles = 3 1350 * BOOT_CFG2[4:3] = 00 - Boot Search Count = 2 1351 * BOOT_CFG2[2:1] = 01 - Pages In Block = 64 1352 * BOOT_CFG2[0] = 0 - Reset time 12ms 1353 */ 1354 static const struct boot_mode board_boot_modes[] = { 1355 /* NAND: 64pages per block, 3 row addr cycles, 2 copies of FCB/DBBT */ 1356 { "nand", MAKE_CFGVAL(0x80, 0x02, 0x00, 0x00) }, 1357 { NULL, 0 }, 1358 }; 1359 #endif 1360 1361 /* late init */ 1362 int misc_init_r(void) 1363 { 1364 struct ventana_board_info *info = &ventana_info; 1365 unsigned char reg; 1366 1367 /* set env vars based on EEPROM data */ 1368 if (ventana_info.model[0]) { 1369 char str[16], fdt[36]; 1370 char *p; 1371 const char *cputype = ""; 1372 int i; 1373 1374 /* 1375 * FDT name will be prefixed with CPU type. Three versions 1376 * will be created each increasingly generic and bootloader 1377 * env scripts will try loading each from most specific to 1378 * least. 1379 */ 1380 if (is_cpu_type(MXC_CPU_MX6Q) || 1381 is_cpu_type(MXC_CPU_MX6D)) 1382 cputype = "imx6q"; 1383 else if (is_cpu_type(MXC_CPU_MX6DL) || 1384 is_cpu_type(MXC_CPU_MX6SOLO)) 1385 cputype = "imx6dl"; 1386 setenv("soctype", cputype); 1387 if (8 << (ventana_info.nand_flash_size-1) >= 2048) 1388 setenv("flash_layout", "large"); 1389 else 1390 setenv("flash_layout", "normal"); 1391 memset(str, 0, sizeof(str)); 1392 for (i = 0; i < (sizeof(str)-1) && info->model[i]; i++) 1393 str[i] = tolower(info->model[i]); 1394 if (!getenv("model")) 1395 setenv("model", str); 1396 if (!getenv("fdt_file")) { 1397 sprintf(fdt, "%s-%s.dtb", cputype, str); 1398 setenv("fdt_file", fdt); 1399 } 1400 p = strchr(str, '-'); 1401 if (p) { 1402 *p++ = 0; 1403 1404 setenv("model_base", str); 1405 if (!getenv("fdt_file1")) { 1406 sprintf(fdt, "%s-%s.dtb", cputype, str); 1407 setenv("fdt_file1", fdt); 1408 } 1409 if (board_type != GW552x) 1410 str[4] = 'x'; 1411 str[5] = 'x'; 1412 str[6] = 0; 1413 if (!getenv("fdt_file2")) { 1414 sprintf(fdt, "%s-%s.dtb", cputype, str); 1415 setenv("fdt_file2", fdt); 1416 } 1417 } 1418 1419 /* initialize env from EEPROM */ 1420 if (test_bit(EECONFIG_ETH0, info->config) && 1421 !getenv("ethaddr")) { 1422 eth_setenv_enetaddr("ethaddr", info->mac0); 1423 } 1424 if (test_bit(EECONFIG_ETH1, info->config) && 1425 !getenv("eth1addr")) { 1426 eth_setenv_enetaddr("eth1addr", info->mac1); 1427 } 1428 1429 /* board serial-number */ 1430 sprintf(str, "%6d", info->serial); 1431 setenv("serial#", str); 1432 } 1433 1434 1435 /* setup baseboard specific GPIO pinmux and config */ 1436 setup_board_gpio(board_type); 1437 1438 #ifdef CONFIG_CMD_BMODE 1439 add_board_boot_modes(board_boot_modes); 1440 #endif 1441 1442 /* 1443 * The Gateworks System Controller implements a boot 1444 * watchdog (always enabled) as a workaround for IMX6 boot related 1445 * errata such as: 1446 * ERR005768 - no fix scheduled 1447 * ERR006282 - fixed in silicon r1.2 1448 * ERR007117 - fixed in silicon r1.3 1449 * ERR007220 - fixed in silicon r1.3 1450 * ERR007926 - no fix scheduled 1451 * see http://cache.freescale.com/files/32bit/doc/errata/IMX6DQCE.pdf 1452 * 1453 * Disable the boot watchdog and display/clear the timeout flag if set 1454 */ 1455 i2c_set_bus_num(CONFIG_I2C_GSC); 1456 if (!gsc_i2c_read(GSC_SC_ADDR, GSC_SC_CTRL1, 1, ®, 1)) { 1457 reg |= (1 << GSC_SC_CTRL1_WDDIS); 1458 if (gsc_i2c_write(GSC_SC_ADDR, GSC_SC_CTRL1, 1, ®, 1)) 1459 puts("Error: could not disable GSC Watchdog\n"); 1460 } else { 1461 puts("Error: could not disable GSC Watchdog\n"); 1462 } 1463 if (!gsc_i2c_read(GSC_SC_ADDR, GSC_SC_STATUS, 1, ®, 1)) { 1464 if (reg & (1 << GSC_SC_IRQ_WATCHDOG)) { /* watchdog timeout */ 1465 puts("GSC boot watchdog timeout detected\n"); 1466 reg &= ~(1 << GSC_SC_IRQ_WATCHDOG); /* clear flag */ 1467 gsc_i2c_write(GSC_SC_ADDR, GSC_SC_STATUS, 1, ®, 1); 1468 } 1469 } 1470 1471 return 0; 1472 } 1473 1474 #if defined(CONFIG_OF_LIBFDT) && defined(CONFIG_OF_BOARD_SETUP) 1475 1476 /* 1477 * called prior to booting kernel or by 'fdt boardsetup' command 1478 * 1479 * unless 'fdt_noauto' env var is set we will update the following in the DTB: 1480 * - mtd partitions based on mtdparts/mtdids env 1481 * - system-serial (board serial num from EEPROM) 1482 * - board (full model from EEPROM) 1483 * - peripherals removed from DTB if not loaded on board (per EEPROM config) 1484 */ 1485 void ft_board_setup(void *blob, bd_t *bd) 1486 { 1487 struct ventana_board_info *info = &ventana_info; 1488 struct ventana_eeprom_config *cfg; 1489 struct node_info nodes[] = { 1490 { "sst,w25q256", MTD_DEV_TYPE_NOR, }, /* SPI flash */ 1491 { "fsl,imx6q-gpmi-nand", MTD_DEV_TYPE_NAND, }, /* NAND flash */ 1492 }; 1493 const char *model = getenv("model"); 1494 1495 if (getenv("fdt_noauto")) { 1496 puts(" Skiping ft_board_setup (fdt_noauto defined)\n"); 1497 return; 1498 } 1499 1500 /* Update partition nodes using info from mtdparts env var */ 1501 puts(" Updating MTD partitions...\n"); 1502 fdt_fixup_mtdparts(blob, nodes, ARRAY_SIZE(nodes)); 1503 1504 if (!model) { 1505 puts("invalid board info: Leaving FDT fully enabled\n"); 1506 return; 1507 } 1508 printf(" Adjusting FDT per EEPROM for %s...\n", model); 1509 1510 /* board serial number */ 1511 fdt_setprop(blob, 0, "system-serial", getenv("serial#"), 1512 strlen(getenv("serial#")) + 1); 1513 1514 /* board (model contains model from device-tree) */ 1515 fdt_setprop(blob, 0, "board", info->model, 1516 strlen((const char *)info->model) + 1); 1517 1518 /* 1519 * Peripheral Config: 1520 * remove nodes by alias path if EEPROM config tells us the 1521 * peripheral is not loaded on the board. 1522 */ 1523 if (getenv("fdt_noconfig")) { 1524 puts(" Skiping periperhal config (fdt_noconfig defined)\n"); 1525 return; 1526 } 1527 cfg = econfig; 1528 while (cfg->name) { 1529 if (!test_bit(cfg->bit, info->config)) { 1530 fdt_del_node_and_alias(blob, cfg->dtalias ? 1531 cfg->dtalias : cfg->name); 1532 } 1533 cfg++; 1534 } 1535 } 1536 #endif /* defined(CONFIG_OF_FLAT_TREE) && defined(CONFIG_OF_BOARD_SETUP) */ 1537 1538