1 /* 2 * Copyright (C) 2013 Gateworks Corporation 3 * 4 * Author: Tim Harvey <tharvey@gateworks.com> 5 * 6 * SPDX-License-Identifier: GPL-2.0+ 7 */ 8 9 #include <common.h> 10 #include <asm/arch/clock.h> 11 #include <asm/arch/crm_regs.h> 12 #include <asm/arch/iomux.h> 13 #include <asm/arch/mx6-pins.h> 14 #include <asm/arch/mxc_hdmi.h> 15 #include <asm/arch/sys_proto.h> 16 #include <asm/gpio.h> 17 #include <asm/imx-common/boot_mode.h> 18 #include <asm/imx-common/sata.h> 19 #include <asm/imx-common/spi.h> 20 #include <asm/imx-common/video.h> 21 #include <asm/io.h> 22 #include <dm.h> 23 #include <dm/platform_data/serial_mxc.h> 24 #include <hwconfig.h> 25 #include <i2c.h> 26 #include <fdt_support.h> 27 #include <fsl_esdhc.h> 28 #include <jffs2/load_kernel.h> 29 #include <linux/ctype.h> 30 #include <miiphy.h> 31 #include <mtd_node.h> 32 #include <netdev.h> 33 #include <pci.h> 34 #include <power/pmic.h> 35 #include <power/ltc3676_pmic.h> 36 #include <power/pfuze100_pmic.h> 37 #include <fdt_support.h> 38 #include <jffs2/load_kernel.h> 39 #include <spi_flash.h> 40 41 #include "gsc.h" 42 #include "common.h" 43 44 DECLARE_GLOBAL_DATA_PTR; 45 46 47 /* 48 * EEPROM board info struct populated by read_eeprom so that we only have to 49 * read it once. 50 */ 51 struct ventana_board_info ventana_info; 52 53 static int board_type; 54 55 /* MMC */ 56 static iomux_v3_cfg_t const usdhc3_pads[] = { 57 IOMUX_PADS(PAD_SD3_CLK__SD3_CLK | MUX_PAD_CTRL(USDHC_PAD_CTRL)), 58 IOMUX_PADS(PAD_SD3_CMD__SD3_CMD | MUX_PAD_CTRL(USDHC_PAD_CTRL)), 59 IOMUX_PADS(PAD_SD3_DAT0__SD3_DATA0 | MUX_PAD_CTRL(USDHC_PAD_CTRL)), 60 IOMUX_PADS(PAD_SD3_DAT1__SD3_DATA1 | MUX_PAD_CTRL(USDHC_PAD_CTRL)), 61 IOMUX_PADS(PAD_SD3_DAT2__SD3_DATA2 | MUX_PAD_CTRL(USDHC_PAD_CTRL)), 62 IOMUX_PADS(PAD_SD3_DAT3__SD3_DATA3 | MUX_PAD_CTRL(USDHC_PAD_CTRL)), 63 IOMUX_PADS(PAD_SD3_DAT5__GPIO7_IO00 | MUX_PAD_CTRL(USDHC_PAD_CTRL)), 64 }; 65 66 /* ENET */ 67 static iomux_v3_cfg_t const enet_pads[] = { 68 IOMUX_PADS(PAD_ENET_MDIO__ENET_MDIO | MUX_PAD_CTRL(ENET_PAD_CTRL)), 69 IOMUX_PADS(PAD_ENET_MDC__ENET_MDC | MUX_PAD_CTRL(ENET_PAD_CTRL)), 70 IOMUX_PADS(PAD_RGMII_TXC__RGMII_TXC | MUX_PAD_CTRL(ENET_PAD_CTRL)), 71 IOMUX_PADS(PAD_RGMII_TD0__RGMII_TD0 | MUX_PAD_CTRL(ENET_PAD_CTRL)), 72 IOMUX_PADS(PAD_RGMII_TD1__RGMII_TD1 | MUX_PAD_CTRL(ENET_PAD_CTRL)), 73 IOMUX_PADS(PAD_RGMII_TD2__RGMII_TD2 | MUX_PAD_CTRL(ENET_PAD_CTRL)), 74 IOMUX_PADS(PAD_RGMII_TD3__RGMII_TD3 | MUX_PAD_CTRL(ENET_PAD_CTRL)), 75 IOMUX_PADS(PAD_RGMII_TX_CTL__RGMII_TX_CTL | 76 MUX_PAD_CTRL(ENET_PAD_CTRL)), 77 IOMUX_PADS(PAD_ENET_REF_CLK__ENET_TX_CLK | 78 MUX_PAD_CTRL(ENET_PAD_CTRL)), 79 IOMUX_PADS(PAD_RGMII_RXC__RGMII_RXC | MUX_PAD_CTRL(ENET_PAD_CTRL)), 80 IOMUX_PADS(PAD_RGMII_RD0__RGMII_RD0 | MUX_PAD_CTRL(ENET_PAD_CTRL)), 81 IOMUX_PADS(PAD_RGMII_RD1__RGMII_RD1 | MUX_PAD_CTRL(ENET_PAD_CTRL)), 82 IOMUX_PADS(PAD_RGMII_RD2__RGMII_RD2 | MUX_PAD_CTRL(ENET_PAD_CTRL)), 83 IOMUX_PADS(PAD_RGMII_RD3__RGMII_RD3 | MUX_PAD_CTRL(ENET_PAD_CTRL)), 84 IOMUX_PADS(PAD_RGMII_RX_CTL__RGMII_RX_CTL | 85 MUX_PAD_CTRL(ENET_PAD_CTRL)), 86 /* PHY nRST */ 87 IOMUX_PADS(PAD_ENET_TXD0__GPIO1_IO30 | DIO_PAD_CFG), 88 }; 89 90 /* NAND */ 91 static iomux_v3_cfg_t const nfc_pads[] = { 92 IOMUX_PADS(PAD_NANDF_CLE__NAND_CLE | MUX_PAD_CTRL(NO_PAD_CTRL)), 93 IOMUX_PADS(PAD_NANDF_ALE__NAND_ALE | MUX_PAD_CTRL(NO_PAD_CTRL)), 94 IOMUX_PADS(PAD_NANDF_WP_B__NAND_WP_B | MUX_PAD_CTRL(NO_PAD_CTRL)), 95 IOMUX_PADS(PAD_NANDF_RB0__NAND_READY_B | MUX_PAD_CTRL(NO_PAD_CTRL)), 96 IOMUX_PADS(PAD_NANDF_CS0__NAND_CE0_B | MUX_PAD_CTRL(NO_PAD_CTRL)), 97 IOMUX_PADS(PAD_SD4_CMD__NAND_RE_B | MUX_PAD_CTRL(NO_PAD_CTRL)), 98 IOMUX_PADS(PAD_SD4_CLK__NAND_WE_B | MUX_PAD_CTRL(NO_PAD_CTRL)), 99 IOMUX_PADS(PAD_NANDF_D0__NAND_DATA00 | MUX_PAD_CTRL(NO_PAD_CTRL)), 100 IOMUX_PADS(PAD_NANDF_D1__NAND_DATA01 | MUX_PAD_CTRL(NO_PAD_CTRL)), 101 IOMUX_PADS(PAD_NANDF_D2__NAND_DATA02 | MUX_PAD_CTRL(NO_PAD_CTRL)), 102 IOMUX_PADS(PAD_NANDF_D3__NAND_DATA03 | MUX_PAD_CTRL(NO_PAD_CTRL)), 103 IOMUX_PADS(PAD_NANDF_D4__NAND_DATA04 | MUX_PAD_CTRL(NO_PAD_CTRL)), 104 IOMUX_PADS(PAD_NANDF_D5__NAND_DATA05 | MUX_PAD_CTRL(NO_PAD_CTRL)), 105 IOMUX_PADS(PAD_NANDF_D6__NAND_DATA06 | MUX_PAD_CTRL(NO_PAD_CTRL)), 106 IOMUX_PADS(PAD_NANDF_D7__NAND_DATA07 | MUX_PAD_CTRL(NO_PAD_CTRL)), 107 }; 108 109 #ifdef CONFIG_CMD_NAND 110 static void setup_gpmi_nand(void) 111 { 112 struct mxc_ccm_reg *mxc_ccm = (struct mxc_ccm_reg *)CCM_BASE_ADDR; 113 114 /* config gpmi nand iomux */ 115 SETUP_IOMUX_PADS(nfc_pads); 116 117 /* config gpmi and bch clock to 100 MHz */ 118 clrsetbits_le32(&mxc_ccm->cs2cdr, 119 MXC_CCM_CS2CDR_ENFC_CLK_PODF_MASK | 120 MXC_CCM_CS2CDR_ENFC_CLK_PRED_MASK | 121 MXC_CCM_CS2CDR_ENFC_CLK_SEL_MASK, 122 MXC_CCM_CS2CDR_ENFC_CLK_PODF(0) | 123 MXC_CCM_CS2CDR_ENFC_CLK_PRED(3) | 124 MXC_CCM_CS2CDR_ENFC_CLK_SEL(3)); 125 126 /* enable gpmi and bch clock gating */ 127 setbits_le32(&mxc_ccm->CCGR4, 128 MXC_CCM_CCGR4_RAWNAND_U_BCH_INPUT_APB_MASK | 129 MXC_CCM_CCGR4_RAWNAND_U_GPMI_BCH_INPUT_BCH_MASK | 130 MXC_CCM_CCGR4_RAWNAND_U_GPMI_BCH_INPUT_GPMI_IO_MASK | 131 MXC_CCM_CCGR4_RAWNAND_U_GPMI_INPUT_APB_MASK | 132 MXC_CCM_CCGR4_PL301_MX6QPER1_BCH_OFFSET); 133 134 /* enable apbh clock gating */ 135 setbits_le32(&mxc_ccm->CCGR0, MXC_CCM_CCGR0_APBHDMA_MASK); 136 } 137 #endif 138 139 static void setup_iomux_enet(int gpio) 140 { 141 SETUP_IOMUX_PADS(enet_pads); 142 143 /* toggle PHY_RST# */ 144 gpio_request(gpio, "phy_rst#"); 145 gpio_direction_output(gpio, 0); 146 mdelay(2); 147 gpio_set_value(gpio, 1); 148 } 149 150 #ifdef CONFIG_USB_EHCI_MX6 151 static iomux_v3_cfg_t const usb_pads[] = { 152 IOMUX_PADS(PAD_GPIO_1__USB_OTG_ID | DIO_PAD_CFG), 153 IOMUX_PADS(PAD_KEY_COL4__USB_OTG_OC | DIO_PAD_CFG), 154 /* OTG PWR */ 155 IOMUX_PADS(PAD_EIM_D22__GPIO3_IO22 | DIO_PAD_CFG), 156 }; 157 158 int board_ehci_hcd_init(int port) 159 { 160 int gpio; 161 162 SETUP_IOMUX_PADS(usb_pads); 163 164 /* Reset USB HUB */ 165 switch (board_type) { 166 case GW53xx: 167 case GW552x: 168 gpio = (IMX_GPIO_NR(1, 9)); 169 break; 170 case GW54proto: 171 case GW54xx: 172 gpio = (IMX_GPIO_NR(1, 16)); 173 break; 174 default: 175 return 0; 176 } 177 178 /* request and toggle hub rst */ 179 gpio_request(gpio, "usb_hub_rst#"); 180 gpio_direction_output(gpio, 0); 181 mdelay(2); 182 gpio_set_value(gpio, 1); 183 184 return 0; 185 } 186 187 int board_ehci_power(int port, int on) 188 { 189 if (port) 190 return 0; 191 gpio_set_value(GP_USB_OTG_PWR, on); 192 return 0; 193 } 194 #endif /* CONFIG_USB_EHCI_MX6 */ 195 196 #ifdef CONFIG_FSL_ESDHC 197 static struct fsl_esdhc_cfg usdhc_cfg = { USDHC3_BASE_ADDR }; 198 199 int board_mmc_getcd(struct mmc *mmc) 200 { 201 /* Card Detect */ 202 gpio_request(GP_SD3_CD, "sd_cd"); 203 gpio_direction_input(GP_SD3_CD); 204 return !gpio_get_value(GP_SD3_CD); 205 } 206 207 int board_mmc_init(bd_t *bis) 208 { 209 /* Only one USDHC controller on Ventana */ 210 SETUP_IOMUX_PADS(usdhc3_pads); 211 usdhc_cfg.sdhc_clk = mxc_get_clock(MXC_ESDHC3_CLK); 212 usdhc_cfg.max_bus_width = 4; 213 214 return fsl_esdhc_initialize(bis, &usdhc_cfg); 215 } 216 #endif /* CONFIG_FSL_ESDHC */ 217 218 #ifdef CONFIG_MXC_SPI 219 iomux_v3_cfg_t const ecspi1_pads[] = { 220 /* SS1 */ 221 IOMUX_PADS(PAD_EIM_D19__GPIO3_IO19 | MUX_PAD_CTRL(SPI_PAD_CTRL)), 222 IOMUX_PADS(PAD_EIM_D17__ECSPI1_MISO | MUX_PAD_CTRL(SPI_PAD_CTRL)), 223 IOMUX_PADS(PAD_EIM_D18__ECSPI1_MOSI | MUX_PAD_CTRL(SPI_PAD_CTRL)), 224 IOMUX_PADS(PAD_EIM_D16__ECSPI1_SCLK | MUX_PAD_CTRL(SPI_PAD_CTRL)), 225 }; 226 227 int board_spi_cs_gpio(unsigned bus, unsigned cs) 228 { 229 return (bus == 0 && cs == 0) ? (IMX_GPIO_NR(3, 19)) : -1; 230 } 231 232 static void setup_spi(void) 233 { 234 gpio_request(IMX_GPIO_NR(3, 19), "spi_cs"); 235 gpio_direction_output(IMX_GPIO_NR(3, 19), 1); 236 SETUP_IOMUX_PADS(ecspi1_pads); 237 } 238 #endif 239 240 /* configure eth0 PHY board-specific LED behavior */ 241 int board_phy_config(struct phy_device *phydev) 242 { 243 unsigned short val; 244 245 /* Marvel 88E1510 */ 246 if (phydev->phy_id == 0x1410dd1) { 247 /* 248 * Page 3, Register 16: LED[2:0] Function Control Register 249 * LED[0] (SPD:Amber) R16_3.3:0 to 0111: on-GbE link 250 * LED[1] (LNK:Green) R16_3.7:4 to 0001: on-link, blink-activity 251 */ 252 phy_write(phydev, MDIO_DEVAD_NONE, 22, 3); 253 val = phy_read(phydev, MDIO_DEVAD_NONE, 16); 254 val &= 0xff00; 255 val |= 0x0017; 256 phy_write(phydev, MDIO_DEVAD_NONE, 16, val); 257 phy_write(phydev, MDIO_DEVAD_NONE, 22, 0); 258 } 259 260 if (phydev->drv->config) 261 phydev->drv->config(phydev); 262 263 return 0; 264 } 265 266 int board_eth_init(bd_t *bis) 267 { 268 #ifdef CONFIG_FEC_MXC 269 struct ventana_board_info *info = &ventana_info; 270 271 if (test_bit(EECONFIG_ETH0, info->config)) { 272 setup_iomux_enet(GP_PHY_RST); 273 cpu_eth_init(bis); 274 } 275 #endif 276 277 #ifdef CONFIG_E1000 278 e1000_initialize(bis); 279 #endif 280 281 #ifdef CONFIG_CI_UDC 282 /* For otg ethernet*/ 283 usb_eth_initialize(bis); 284 #endif 285 286 /* default to the first detected enet dev */ 287 if (!getenv("ethprime")) { 288 struct eth_device *dev = eth_get_dev_by_index(0); 289 if (dev) { 290 setenv("ethprime", dev->name); 291 printf("set ethprime to %s\n", getenv("ethprime")); 292 } 293 } 294 295 return 0; 296 } 297 298 #if defined(CONFIG_VIDEO_IPUV3) 299 300 static void enable_hdmi(struct display_info_t const *dev) 301 { 302 imx_enable_hdmi_phy(); 303 } 304 305 static int detect_i2c(struct display_info_t const *dev) 306 { 307 return i2c_set_bus_num(dev->bus) == 0 && 308 i2c_probe(dev->addr) == 0; 309 } 310 311 static void enable_lvds(struct display_info_t const *dev) 312 { 313 struct iomuxc *iomux = (struct iomuxc *) 314 IOMUXC_BASE_ADDR; 315 316 /* set CH0 data width to 24bit (IOMUXC_GPR2:5 0=18bit, 1=24bit) */ 317 u32 reg = readl(&iomux->gpr[2]); 318 reg |= IOMUXC_GPR2_DATA_WIDTH_CH0_24BIT; 319 writel(reg, &iomux->gpr[2]); 320 321 /* Enable Backlight */ 322 gpio_request(IMX_GPIO_NR(1, 10), "bklt_gpio"); 323 gpio_direction_output(IMX_GPIO_NR(1, 10), 0); 324 gpio_request(IMX_GPIO_NR(1, 18), "bklt_en"); 325 SETUP_IOMUX_PAD(PAD_SD1_CMD__GPIO1_IO18 | DIO_PAD_CFG); 326 gpio_direction_output(IMX_GPIO_NR(1, 18), 1); 327 } 328 329 struct display_info_t const displays[] = {{ 330 /* HDMI Output */ 331 .bus = -1, 332 .addr = 0, 333 .pixfmt = IPU_PIX_FMT_RGB24, 334 .detect = detect_hdmi, 335 .enable = enable_hdmi, 336 .mode = { 337 .name = "HDMI", 338 .refresh = 60, 339 .xres = 1024, 340 .yres = 768, 341 .pixclock = 15385, 342 .left_margin = 220, 343 .right_margin = 40, 344 .upper_margin = 21, 345 .lower_margin = 7, 346 .hsync_len = 60, 347 .vsync_len = 10, 348 .sync = FB_SYNC_EXT, 349 .vmode = FB_VMODE_NONINTERLACED 350 } }, { 351 /* Freescale MXC-LVDS1: HannStar HSD100PXN1-A00 w/ egalx_ts cont */ 352 .bus = 2, 353 .addr = 0x4, 354 .pixfmt = IPU_PIX_FMT_LVDS666, 355 .detect = detect_i2c, 356 .enable = enable_lvds, 357 .mode = { 358 .name = "Hannstar-XGA", 359 .refresh = 60, 360 .xres = 1024, 361 .yres = 768, 362 .pixclock = 15385, 363 .left_margin = 220, 364 .right_margin = 40, 365 .upper_margin = 21, 366 .lower_margin = 7, 367 .hsync_len = 60, 368 .vsync_len = 10, 369 .sync = FB_SYNC_EXT, 370 .vmode = FB_VMODE_NONINTERLACED 371 } }, { 372 /* DLC700JMG-T-4 */ 373 .bus = 0, 374 .addr = 0, 375 .detect = NULL, 376 .enable = enable_lvds, 377 .pixfmt = IPU_PIX_FMT_LVDS666, 378 .mode = { 379 .name = "DLC700JMGT4", 380 .refresh = 60, 381 .xres = 1024, /* 1024x600active pixels */ 382 .yres = 600, 383 .pixclock = 15385, /* 64MHz */ 384 .left_margin = 220, 385 .right_margin = 40, 386 .upper_margin = 21, 387 .lower_margin = 7, 388 .hsync_len = 60, 389 .vsync_len = 10, 390 .sync = FB_SYNC_EXT, 391 .vmode = FB_VMODE_NONINTERLACED 392 } }, { 393 /* DLC800FIG-T-3 */ 394 .bus = 0, 395 .addr = 0, 396 .detect = NULL, 397 .enable = enable_lvds, 398 .pixfmt = IPU_PIX_FMT_LVDS666, 399 .mode = { 400 .name = "DLC800FIGT3", 401 .refresh = 60, 402 .xres = 1024, /* 1024x768 active pixels */ 403 .yres = 768, 404 .pixclock = 15385, /* 64MHz */ 405 .left_margin = 220, 406 .right_margin = 40, 407 .upper_margin = 21, 408 .lower_margin = 7, 409 .hsync_len = 60, 410 .vsync_len = 10, 411 .sync = FB_SYNC_EXT, 412 .vmode = FB_VMODE_NONINTERLACED 413 } } }; 414 size_t display_count = ARRAY_SIZE(displays); 415 416 static void setup_display(void) 417 { 418 struct mxc_ccm_reg *mxc_ccm = (struct mxc_ccm_reg *)CCM_BASE_ADDR; 419 struct iomuxc *iomux = (struct iomuxc *)IOMUXC_BASE_ADDR; 420 int reg; 421 422 enable_ipu_clock(); 423 imx_setup_hdmi(); 424 /* Turn on LDB0,IPU,IPU DI0 clocks */ 425 reg = __raw_readl(&mxc_ccm->CCGR3); 426 reg |= MXC_CCM_CCGR3_LDB_DI0_MASK; 427 writel(reg, &mxc_ccm->CCGR3); 428 429 /* set LDB0, LDB1 clk select to 011/011 */ 430 reg = readl(&mxc_ccm->cs2cdr); 431 reg &= ~(MXC_CCM_CS2CDR_LDB_DI0_CLK_SEL_MASK 432 |MXC_CCM_CS2CDR_LDB_DI1_CLK_SEL_MASK); 433 reg |= (3<<MXC_CCM_CS2CDR_LDB_DI0_CLK_SEL_OFFSET) 434 |(3<<MXC_CCM_CS2CDR_LDB_DI1_CLK_SEL_OFFSET); 435 writel(reg, &mxc_ccm->cs2cdr); 436 437 reg = readl(&mxc_ccm->cscmr2); 438 reg |= MXC_CCM_CSCMR2_LDB_DI0_IPU_DIV; 439 writel(reg, &mxc_ccm->cscmr2); 440 441 reg = readl(&mxc_ccm->chsccdr); 442 reg |= (CHSCCDR_CLK_SEL_LDB_DI0 443 <<MXC_CCM_CHSCCDR_IPU1_DI0_CLK_SEL_OFFSET); 444 writel(reg, &mxc_ccm->chsccdr); 445 446 reg = IOMUXC_GPR2_BGREF_RRMODE_EXTERNAL_RES 447 |IOMUXC_GPR2_DI1_VS_POLARITY_ACTIVE_HIGH 448 |IOMUXC_GPR2_DI0_VS_POLARITY_ACTIVE_LOW 449 |IOMUXC_GPR2_BIT_MAPPING_CH1_SPWG 450 |IOMUXC_GPR2_DATA_WIDTH_CH1_18BIT 451 |IOMUXC_GPR2_BIT_MAPPING_CH0_SPWG 452 |IOMUXC_GPR2_DATA_WIDTH_CH0_18BIT 453 |IOMUXC_GPR2_LVDS_CH1_MODE_DISABLED 454 |IOMUXC_GPR2_LVDS_CH0_MODE_ENABLED_DI0; 455 writel(reg, &iomux->gpr[2]); 456 457 reg = readl(&iomux->gpr[3]); 458 reg = (reg & ~IOMUXC_GPR3_LVDS0_MUX_CTL_MASK) 459 | (IOMUXC_GPR3_MUX_SRC_IPU1_DI0 460 <<IOMUXC_GPR3_LVDS0_MUX_CTL_OFFSET); 461 writel(reg, &iomux->gpr[3]); 462 463 /* LVDS Backlight GPIO on LVDS connector - output low */ 464 SETUP_IOMUX_PAD(PAD_SD2_CLK__GPIO1_IO10 | DIO_PAD_CFG); 465 gpio_direction_output(IMX_GPIO_NR(1, 10), 0); 466 } 467 #endif /* CONFIG_VIDEO_IPUV3 */ 468 469 /* setup board specific PMIC */ 470 int power_init_board(void) 471 { 472 setup_pmic(); 473 return 0; 474 } 475 476 #if defined(CONFIG_CMD_PCI) 477 int imx6_pcie_toggle_reset(void) 478 { 479 if (board_type < GW_UNKNOWN) { 480 uint pin = gpio_cfg[board_type].pcie_rst; 481 gpio_request(pin, "pci_rst#"); 482 gpio_direction_output(pin, 0); 483 mdelay(50); 484 gpio_direction_output(pin, 1); 485 } 486 return 0; 487 } 488 489 /* 490 * Most Ventana boards have a PLX PEX860x PCIe switch onboard and use its 491 * GPIO's as PERST# signals for its downstream ports - configure the GPIO's 492 * properly and assert reset for 100ms. 493 */ 494 #define MAX_PCI_DEVS 32 495 struct pci_dev { 496 pci_dev_t devfn; 497 unsigned short vendor; 498 unsigned short device; 499 unsigned short class; 500 unsigned short busno; /* subbordinate busno */ 501 struct pci_dev *ppar; 502 }; 503 struct pci_dev pci_devs[MAX_PCI_DEVS]; 504 int pci_devno; 505 int pci_bridgeno; 506 507 void board_pci_fixup_dev(struct pci_controller *hose, pci_dev_t dev, 508 unsigned short vendor, unsigned short device, 509 unsigned short class) 510 { 511 int i; 512 u32 dw; 513 struct pci_dev *pdev = &pci_devs[pci_devno++]; 514 515 debug("%s: %02d:%02d.%02d: %04x:%04x\n", __func__, 516 PCI_BUS(dev), PCI_DEV(dev), PCI_FUNC(dev), vendor, device); 517 518 /* store array of devs for later use in device-tree fixup */ 519 pdev->devfn = dev; 520 pdev->vendor = vendor; 521 pdev->device = device; 522 pdev->class = class; 523 pdev->ppar = NULL; 524 if (class == PCI_CLASS_BRIDGE_PCI) 525 pdev->busno = ++pci_bridgeno; 526 else 527 pdev->busno = 0; 528 529 /* fixup RC - it should be 00:00.0 not 00:01.0 */ 530 if (PCI_BUS(dev) == 0) 531 pdev->devfn = 0; 532 533 /* find dev's parent */ 534 for (i = 0; i < pci_devno; i++) { 535 if (pci_devs[i].busno == PCI_BUS(pdev->devfn)) { 536 pdev->ppar = &pci_devs[i]; 537 break; 538 } 539 } 540 541 /* assert downstream PERST# */ 542 if (vendor == PCI_VENDOR_ID_PLX && 543 (device & 0xfff0) == 0x8600 && 544 PCI_DEV(dev) == 0 && PCI_FUNC(dev) == 0) { 545 debug("configuring PLX 860X downstream PERST#\n"); 546 pci_hose_read_config_dword(hose, dev, 0x62c, &dw); 547 dw |= 0xaaa8; /* GPIO1-7 outputs */ 548 pci_hose_write_config_dword(hose, dev, 0x62c, dw); 549 550 pci_hose_read_config_dword(hose, dev, 0x644, &dw); 551 dw |= 0xfe; /* GPIO1-7 output high */ 552 pci_hose_write_config_dword(hose, dev, 0x644, dw); 553 554 mdelay(100); 555 } 556 } 557 #endif /* CONFIG_CMD_PCI */ 558 559 #ifdef CONFIG_SERIAL_TAG 560 /* 561 * called when setting up ATAGS before booting kernel 562 * populate serialnum from the following (in order of priority): 563 * serial# env var 564 * eeprom 565 */ 566 void get_board_serial(struct tag_serialnr *serialnr) 567 { 568 char *serial = getenv("serial#"); 569 570 if (serial) { 571 serialnr->high = 0; 572 serialnr->low = simple_strtoul(serial, NULL, 10); 573 } else if (ventana_info.model[0]) { 574 serialnr->high = 0; 575 serialnr->low = ventana_info.serial; 576 } else { 577 serialnr->high = 0; 578 serialnr->low = 0; 579 } 580 } 581 #endif 582 583 /* 584 * Board Support 585 */ 586 587 int board_early_init_f(void) 588 { 589 setup_iomux_uart(); 590 591 #if defined(CONFIG_VIDEO_IPUV3) 592 setup_display(); 593 #endif 594 return 0; 595 } 596 597 int dram_init(void) 598 { 599 gd->ram_size = imx_ddr_size(); 600 return 0; 601 } 602 603 int board_init(void) 604 { 605 struct iomuxc *const iomuxc_regs = (struct iomuxc *)IOMUXC_BASE_ADDR; 606 607 clrsetbits_le32(&iomuxc_regs->gpr[1], 608 IOMUXC_GPR1_OTG_ID_MASK, 609 IOMUXC_GPR1_OTG_ID_GPIO1); 610 611 /* address of linux boot parameters */ 612 gd->bd->bi_boot_params = PHYS_SDRAM + 0x100; 613 614 #ifdef CONFIG_CMD_NAND 615 setup_gpmi_nand(); 616 #endif 617 #ifdef CONFIG_MXC_SPI 618 setup_spi(); 619 #endif 620 setup_ventana_i2c(); 621 622 #ifdef CONFIG_CMD_SATA 623 setup_sata(); 624 #endif 625 /* read Gateworks EEPROM into global struct (used later) */ 626 board_type = read_eeprom(CONFIG_I2C_GSC, &ventana_info); 627 628 setup_iomux_gpio(board_type, &ventana_info); 629 630 return 0; 631 } 632 633 #if defined(CONFIG_DISPLAY_BOARDINFO_LATE) 634 /* 635 * called during late init (after relocation and after board_init()) 636 * by virtue of CONFIG_DISPLAY_BOARDINFO_LATE as we needed i2c initialized and 637 * EEPROM read. 638 */ 639 int checkboard(void) 640 { 641 struct ventana_board_info *info = &ventana_info; 642 unsigned char buf[4]; 643 const char *p; 644 int quiet; /* Quiet or minimal output mode */ 645 646 quiet = 0; 647 p = getenv("quiet"); 648 if (p) 649 quiet = simple_strtol(p, NULL, 10); 650 else 651 setenv("quiet", "0"); 652 653 puts("\nGateworks Corporation Copyright 2014\n"); 654 if (info->model[0]) { 655 printf("Model: %s\n", info->model); 656 printf("MFGDate: %02x-%02x-%02x%02x\n", 657 info->mfgdate[0], info->mfgdate[1], 658 info->mfgdate[2], info->mfgdate[3]); 659 printf("Serial:%d\n", info->serial); 660 } else { 661 puts("Invalid EEPROM - board will not function fully\n"); 662 } 663 if (quiet) 664 return 0; 665 666 /* Display GSC firmware revision/CRC/status */ 667 gsc_info(0); 668 669 /* Display RTC */ 670 if (!gsc_i2c_read(GSC_RTC_ADDR, 0x00, 1, buf, 4)) { 671 printf("RTC: %d\n", 672 buf[0] | buf[1]<<8 | buf[2]<<16 | buf[3]<<24); 673 } 674 675 return 0; 676 } 677 #endif 678 679 #ifdef CONFIG_CMD_BMODE 680 /* 681 * BOOT_CFG1, BOOT_CFG2, BOOT_CFG3, BOOT_CFG4 682 * see Table 8-11 and Table 5-9 683 * BOOT_CFG1[7] = 1 (boot from NAND) 684 * BOOT_CFG1[5] = 0 - raw NAND 685 * BOOT_CFG1[4] = 0 - default pad settings 686 * BOOT_CFG1[3:2] = 00 - devices = 1 687 * BOOT_CFG1[1:0] = 00 - Row Address Cycles = 3 688 * BOOT_CFG2[4:3] = 00 - Boot Search Count = 2 689 * BOOT_CFG2[2:1] = 01 - Pages In Block = 64 690 * BOOT_CFG2[0] = 0 - Reset time 12ms 691 */ 692 static const struct boot_mode board_boot_modes[] = { 693 /* NAND: 64pages per block, 3 row addr cycles, 2 copies of FCB/DBBT */ 694 { "nand", MAKE_CFGVAL(0x80, 0x02, 0x00, 0x00) }, 695 { NULL, 0 }, 696 }; 697 #endif 698 699 /* late init */ 700 int misc_init_r(void) 701 { 702 struct ventana_board_info *info = &ventana_info; 703 char buf[256]; 704 int i; 705 706 /* set env vars based on EEPROM data */ 707 if (ventana_info.model[0]) { 708 char str[16], fdt[36]; 709 char *p; 710 const char *cputype = ""; 711 712 /* 713 * FDT name will be prefixed with CPU type. Three versions 714 * will be created each increasingly generic and bootloader 715 * env scripts will try loading each from most specific to 716 * least. 717 */ 718 if (is_cpu_type(MXC_CPU_MX6Q) || 719 is_cpu_type(MXC_CPU_MX6D)) 720 cputype = "imx6q"; 721 else if (is_cpu_type(MXC_CPU_MX6DL) || 722 is_cpu_type(MXC_CPU_MX6SOLO)) 723 cputype = "imx6dl"; 724 setenv("soctype", cputype); 725 if (8 << (ventana_info.nand_flash_size-1) >= 2048) 726 setenv("flash_layout", "large"); 727 else 728 setenv("flash_layout", "normal"); 729 memset(str, 0, sizeof(str)); 730 for (i = 0; i < (sizeof(str)-1) && info->model[i]; i++) 731 str[i] = tolower(info->model[i]); 732 setenv("model", str); 733 if (!getenv("fdt_file")) { 734 sprintf(fdt, "%s-%s.dtb", cputype, str); 735 setenv("fdt_file", fdt); 736 } 737 p = strchr(str, '-'); 738 if (p) { 739 *p++ = 0; 740 741 setenv("model_base", str); 742 sprintf(fdt, "%s-%s.dtb", cputype, str); 743 setenv("fdt_file1", fdt); 744 if (board_type != GW551x && 745 board_type != GW552x && 746 board_type != GW553x) 747 str[4] = 'x'; 748 str[5] = 'x'; 749 str[6] = 0; 750 sprintf(fdt, "%s-%s.dtb", cputype, str); 751 setenv("fdt_file2", fdt); 752 } 753 754 /* initialize env from EEPROM */ 755 if (test_bit(EECONFIG_ETH0, info->config) && 756 !getenv("ethaddr")) { 757 eth_setenv_enetaddr("ethaddr", info->mac0); 758 } 759 if (test_bit(EECONFIG_ETH1, info->config) && 760 !getenv("eth1addr")) { 761 eth_setenv_enetaddr("eth1addr", info->mac1); 762 } 763 764 /* board serial-number */ 765 sprintf(str, "%6d", info->serial); 766 setenv("serial#", str); 767 768 /* memory MB */ 769 sprintf(str, "%d", (int) (gd->ram_size >> 20)); 770 setenv("mem_mb", str); 771 } 772 773 /* Set a non-initialized hwconfig based on board configuration */ 774 if (!strcmp(getenv("hwconfig"), "_UNKNOWN_")) { 775 sprintf(buf, "hwconfig="); 776 if (gpio_cfg[board_type].rs232_en) 777 strcat(buf, "rs232;"); 778 for (i = 0; i < gpio_cfg[board_type].dio_num; i++) { 779 char buf1[32]; 780 sprintf(buf1, "dio%d:mode=gpio;", i); 781 if (strlen(buf) + strlen(buf1) < sizeof(buf)) 782 strcat(buf, buf1); 783 } 784 setenv("hwconfig", buf); 785 } 786 787 /* setup baseboard specific GPIO based on board and env */ 788 setup_board_gpio(board_type, info); 789 790 #ifdef CONFIG_CMD_BMODE 791 add_board_boot_modes(board_boot_modes); 792 #endif 793 794 /* disable boot watchdog */ 795 gsc_boot_wd_disable(); 796 797 return 0; 798 } 799 800 #ifdef CONFIG_OF_BOARD_SETUP 801 802 static int ft_sethdmiinfmt(void *blob, char *mode) 803 { 804 int off; 805 806 if (!mode) 807 return -EINVAL; 808 809 off = fdt_node_offset_by_compatible(blob, -1, "nxp,tda1997x"); 810 if (off < 0) 811 return off; 812 813 if (0 == strcasecmp(mode, "yuv422bt656")) { 814 u8 cfg[] = { 0x00, 0x00, 0x00, 0x82, 0x81, 0x00, 815 0x00, 0x00, 0x00 }; 816 mode = "422_ccir"; 817 fdt_setprop(blob, off, "vidout_fmt", mode, strlen(mode) + 1); 818 fdt_setprop_u32(blob, off, "vidout_trc", 1); 819 fdt_setprop_u32(blob, off, "vidout_blc", 1); 820 fdt_setprop(blob, off, "vidout_portcfg", cfg, sizeof(cfg)); 821 printf(" set HDMI input mode to %s\n", mode); 822 } else if (0 == strcasecmp(mode, "yuv422smp")) { 823 u8 cfg[] = { 0x00, 0x00, 0x00, 0x88, 0x87, 0x00, 824 0x82, 0x81, 0x00 }; 825 mode = "422_smp"; 826 fdt_setprop(blob, off, "vidout_fmt", mode, strlen(mode) + 1); 827 fdt_setprop_u32(blob, off, "vidout_trc", 0); 828 fdt_setprop_u32(blob, off, "vidout_blc", 0); 829 fdt_setprop(blob, off, "vidout_portcfg", cfg, sizeof(cfg)); 830 printf(" set HDMI input mode to %s\n", mode); 831 } else { 832 return -EINVAL; 833 } 834 835 return 0; 836 } 837 838 /* enable a property of a node if the node is found */ 839 static inline void ft_enable_path(void *blob, const char *path) 840 { 841 int i = fdt_path_offset(blob, path); 842 if (i >= 0) { 843 debug("enabling %s\n", path); 844 fdt_status_okay(blob, i); 845 } 846 } 847 848 /* remove a property of a node if the node is found */ 849 static inline void ft_delprop_path(void *blob, const char *path, 850 const char *name) 851 { 852 int i = fdt_path_offset(blob, path); 853 if (i) { 854 debug("removing %s/%s\n", path, name); 855 fdt_delprop(blob, i, name); 856 } 857 } 858 859 #if defined(CONFIG_CMD_PCI) 860 #define PCI_ID(x) ( \ 861 (PCI_BUS(x->devfn)<<16)| \ 862 (PCI_DEV(x->devfn)<<11)| \ 863 (PCI_FUNC(x->devfn)<<8) \ 864 ) 865 #define PCIE_PATH "/soc/pcie@0x01000000" 866 int fdt_add_pci_node(void *blob, int par, struct pci_dev *dev) 867 { 868 uint32_t reg[5]; 869 char node[32]; 870 int np; 871 872 sprintf(node, "pcie@%d,%d,%d", PCI_BUS(dev->devfn), 873 PCI_DEV(dev->devfn), PCI_FUNC(dev->devfn)); 874 875 np = fdt_subnode_offset(blob, par, node); 876 if (np >= 0) 877 return np; 878 np = fdt_add_subnode(blob, par, node); 879 if (np < 0) { 880 printf(" %s failed: no space\n", __func__); 881 return np; 882 } 883 884 memset(reg, 0, sizeof(reg)); 885 reg[0] = cpu_to_fdt32(PCI_ID(dev)); 886 fdt_setprop(blob, np, "reg", reg, sizeof(reg)); 887 888 return np; 889 } 890 891 /* build a path of nested PCI devs for all bridges passed through */ 892 int fdt_add_pci_path(void *blob, struct pci_dev *dev) 893 { 894 struct pci_dev *bridges[MAX_PCI_DEVS]; 895 int k, np; 896 897 /* build list of parents */ 898 np = fdt_path_offset(blob, PCIE_PATH); 899 if (np < 0) 900 return np; 901 902 k = 0; 903 while (dev) { 904 bridges[k++] = dev; 905 dev = dev->ppar; 906 }; 907 908 /* now add them the to DT in reverse order */ 909 while (k--) { 910 np = fdt_add_pci_node(blob, np, bridges[k]); 911 if (np < 0) 912 break; 913 } 914 915 return np; 916 } 917 918 /* 919 * The GW16082 has a hardware errata errata such that it's 920 * INTA/B/C/D are mis-mapped to its four slots (slot12-15). Because 921 * of this normal PCI interrupt swizzling will not work so we will 922 * provide an irq-map via device-tree. 923 */ 924 int fdt_fixup_gw16082(void *blob, int np, struct pci_dev *dev) 925 { 926 int len; 927 int host; 928 uint32_t imap_new[8*4*4]; 929 const uint32_t *imap; 930 uint32_t irq[4]; 931 uint32_t reg[4]; 932 int i; 933 934 /* build irq-map based on host controllers map */ 935 host = fdt_path_offset(blob, PCIE_PATH); 936 if (host < 0) { 937 printf(" %s failed: missing host\n", __func__); 938 return host; 939 } 940 941 /* use interrupt data from root complex's node */ 942 imap = fdt_getprop(blob, host, "interrupt-map", &len); 943 if (!imap || len != 128) { 944 printf(" %s failed: invalid interrupt-map\n", 945 __func__); 946 return -FDT_ERR_NOTFOUND; 947 } 948 949 /* obtain irq's of host controller in pin order */ 950 for (i = 0; i < 4; i++) 951 irq[(fdt32_to_cpu(imap[(i*8)+3])-1)%4] = imap[(i*8)+6]; 952 953 /* 954 * determine number of swizzles necessary: 955 * For each bridge we pass through we need to swizzle 956 * the number of the slot we are on. 957 */ 958 struct pci_dev *d; 959 int b; 960 b = 0; 961 d = dev->ppar; 962 while(d && d->ppar) { 963 b += PCI_DEV(d->devfn); 964 d = d->ppar; 965 } 966 967 /* create new irq mappings for slots12-15 968 * <skt> <idsel> <slot> <skt-inta> <skt-intb> 969 * J3 AD28 12 INTD INTA 970 * J4 AD29 13 INTC INTD 971 * J5 AD30 14 INTB INTC 972 * J2 AD31 15 INTA INTB 973 */ 974 for (i = 0; i < 4; i++) { 975 /* addr matches bus:dev:func */ 976 u32 addr = dev->busno << 16 | (12+i) << 11; 977 978 /* default cells from root complex */ 979 memcpy(&imap_new[i*32], imap, 128); 980 /* first cell is PCI device address (BDF) */ 981 imap_new[(i*32)+(0*8)+0] = cpu_to_fdt32(addr); 982 imap_new[(i*32)+(1*8)+0] = cpu_to_fdt32(addr); 983 imap_new[(i*32)+(2*8)+0] = cpu_to_fdt32(addr); 984 imap_new[(i*32)+(3*8)+0] = cpu_to_fdt32(addr); 985 /* third cell is pin */ 986 imap_new[(i*32)+(0*8)+3] = cpu_to_fdt32(1); 987 imap_new[(i*32)+(1*8)+3] = cpu_to_fdt32(2); 988 imap_new[(i*32)+(2*8)+3] = cpu_to_fdt32(3); 989 imap_new[(i*32)+(3*8)+3] = cpu_to_fdt32(4); 990 /* sixth cell is relative interrupt */ 991 imap_new[(i*32)+(0*8)+6] = irq[(15-(12+i)+b+0)%4]; 992 imap_new[(i*32)+(1*8)+6] = irq[(15-(12+i)+b+1)%4]; 993 imap_new[(i*32)+(2*8)+6] = irq[(15-(12+i)+b+2)%4]; 994 imap_new[(i*32)+(3*8)+6] = irq[(15-(12+i)+b+3)%4]; 995 } 996 fdt_setprop(blob, np, "interrupt-map", imap_new, 997 sizeof(imap_new)); 998 reg[0] = cpu_to_fdt32(0xfff00); 999 reg[1] = 0; 1000 reg[2] = 0; 1001 reg[3] = cpu_to_fdt32(0x7); 1002 fdt_setprop(blob, np, "interrupt-map-mask", reg, sizeof(reg)); 1003 fdt_setprop_cell(blob, np, "#interrupt-cells", 1); 1004 fdt_setprop_string(blob, np, "device_type", "pci"); 1005 fdt_setprop_cell(blob, np, "#address-cells", 3); 1006 fdt_setprop_cell(blob, np, "#size-cells", 2); 1007 printf(" Added custom interrupt-map for GW16082\n"); 1008 1009 return 0; 1010 } 1011 1012 /* The sky2 GigE MAC obtains it's MAC addr from device-tree by default */ 1013 int fdt_fixup_sky2(void *blob, int np, struct pci_dev *dev) 1014 { 1015 char *tmp, *end; 1016 char mac[16]; 1017 unsigned char mac_addr[6]; 1018 int j; 1019 1020 sprintf(mac, "eth1addr"); 1021 tmp = getenv(mac); 1022 if (tmp) { 1023 for (j = 0; j < 6; j++) { 1024 mac_addr[j] = tmp ? 1025 simple_strtoul(tmp, &end,16) : 0; 1026 if (tmp) 1027 tmp = (*end) ? end+1 : end; 1028 } 1029 fdt_setprop(blob, np, "local-mac-address", mac_addr, 1030 sizeof(mac_addr)); 1031 printf(" Added mac addr for eth1\n"); 1032 return 0; 1033 } 1034 1035 return -1; 1036 } 1037 1038 /* 1039 * PCI DT nodes must be nested therefore if we need to apply a DT fixup 1040 * we will walk the PCI bus and add bridge nodes up to the device receiving 1041 * the fixup. 1042 */ 1043 void ft_board_pci_fixup(void *blob, bd_t *bd) 1044 { 1045 int i, np; 1046 struct pci_dev *dev; 1047 1048 for (i = 0; i < pci_devno; i++) { 1049 dev = &pci_devs[i]; 1050 1051 /* 1052 * The GW16082 consists of a TI XIO2001 PCIe-to-PCI bridge and 1053 * an EEPROM at i2c1-0x50. 1054 */ 1055 if ((dev->vendor == PCI_VENDOR_ID_TI) && 1056 (dev->device == 0x8240) && 1057 (i2c_set_bus_num(1) == 0) && 1058 (i2c_probe(0x50) == 0)) 1059 { 1060 np = fdt_add_pci_path(blob, dev); 1061 if (np > 0) 1062 fdt_fixup_gw16082(blob, np, dev); 1063 } 1064 1065 /* ethernet1 mac address */ 1066 else if ((dev->vendor == PCI_VENDOR_ID_MARVELL) && 1067 (dev->device == 0x4380)) 1068 { 1069 np = fdt_add_pci_path(blob, dev); 1070 if (np > 0) 1071 fdt_fixup_sky2(blob, np, dev); 1072 } 1073 } 1074 } 1075 #endif /* if defined(CONFIG_CMD_PCI) */ 1076 1077 /* 1078 * called prior to booting kernel or by 'fdt boardsetup' command 1079 * 1080 * unless 'fdt_noauto' env var is set we will update the following in the DTB: 1081 * - mtd partitions based on mtdparts/mtdids env 1082 * - system-serial (board serial num from EEPROM) 1083 * - board (full model from EEPROM) 1084 * - peripherals removed from DTB if not loaded on board (per EEPROM config) 1085 */ 1086 #define UART1_PATH "/soc/aips-bus@02100000/serial@021ec000" 1087 #define WDOG1_PATH "/soc/aips-bus@02000000/wdog@020bc000" 1088 #define WDOG2_PATH "/soc/aips-bus@02000000/wdog@020c0000" 1089 #define GPIO3_PATH "/soc/aips-bus@02000000/gpio@020a4000" 1090 int ft_board_setup(void *blob, bd_t *bd) 1091 { 1092 struct ventana_board_info *info = &ventana_info; 1093 struct ventana_eeprom_config *cfg; 1094 struct node_info nodes[] = { 1095 { "sst,w25q256", MTD_DEV_TYPE_NOR, }, /* SPI flash */ 1096 { "fsl,imx6q-gpmi-nand", MTD_DEV_TYPE_NAND, }, /* NAND flash */ 1097 }; 1098 const char *model = getenv("model"); 1099 const char *display = getenv("display"); 1100 int i; 1101 char rev = 0; 1102 1103 /* determine board revision */ 1104 for (i = sizeof(ventana_info.model) - 1; i > 0; i--) { 1105 if (ventana_info.model[i] >= 'A') { 1106 rev = ventana_info.model[i]; 1107 break; 1108 } 1109 } 1110 1111 if (getenv("fdt_noauto")) { 1112 puts(" Skiping ft_board_setup (fdt_noauto defined)\n"); 1113 return 0; 1114 } 1115 1116 if (test_bit(EECONFIG_NAND, info->config)) { 1117 /* Update partition nodes using info from mtdparts env var */ 1118 puts(" Updating MTD partitions...\n"); 1119 fdt_fixup_mtdparts(blob, nodes, ARRAY_SIZE(nodes)); 1120 } 1121 1122 /* Update display timings from display env var */ 1123 if (display) { 1124 if (fdt_fixup_display(blob, fdt_get_alias(blob, "lvds0"), 1125 display) >= 0) 1126 printf(" Set display timings for %s...\n", display); 1127 } 1128 1129 printf(" Adjusting FDT per EEPROM for %s...\n", model); 1130 1131 /* board serial number */ 1132 fdt_setprop(blob, 0, "system-serial", getenv("serial#"), 1133 strlen(getenv("serial#")) + 1); 1134 1135 /* board (model contains model from device-tree) */ 1136 fdt_setprop(blob, 0, "board", info->model, 1137 strlen((const char *)info->model) + 1); 1138 1139 /* set desired digital video capture format */ 1140 ft_sethdmiinfmt(blob, getenv("hdmiinfmt")); 1141 1142 /* 1143 * Board model specific fixups 1144 */ 1145 switch (board_type) { 1146 case GW51xx: 1147 /* 1148 * disable wdog node for GW51xx-A/B to work around 1149 * errata causing wdog timer to be unreliable. 1150 */ 1151 if (rev >= 'A' && rev < 'C') { 1152 i = fdt_path_offset(blob, WDOG1_PATH); 1153 if (i) 1154 fdt_status_disabled(blob, i); 1155 } 1156 1157 /* GW51xx-E adds WDOG1_B external reset */ 1158 if (rev < 'E') 1159 ft_delprop_path(blob, WDOG1_PATH, 1160 "fsl,ext-reset-output"); 1161 break; 1162 1163 case GW52xx: 1164 /* GW522x Uses GPIO3_IO23 instead of GPIO1_IO29 */ 1165 if (info->model[4] == '2') { 1166 u32 handle = 0; 1167 u32 *range = NULL; 1168 1169 i = fdt_node_offset_by_compatible(blob, -1, 1170 "fsl,imx6q-pcie"); 1171 if (i) 1172 range = (u32 *)fdt_getprop(blob, i, 1173 "reset-gpio", NULL); 1174 1175 if (range) { 1176 i = fdt_path_offset(blob, GPIO3_PATH); 1177 if (i) 1178 handle = fdt_get_phandle(blob, i); 1179 if (handle) { 1180 range[0] = cpu_to_fdt32(handle); 1181 range[1] = cpu_to_fdt32(23); 1182 } 1183 } 1184 1185 /* these have broken usd_vsel */ 1186 if (strstr((const char *)info->model, "SP318-B") || 1187 strstr((const char *)info->model, "SP331-B")) 1188 gpio_cfg[board_type].usd_vsel = 0; 1189 1190 /* GW520x-E adds WDOG1_B external reset */ 1191 if (info->model[4] == '0' && rev < 'E') 1192 ft_delprop_path(blob, WDOG1_PATH, 1193 "fsl,ext-reset-output"); 1194 1195 /* GW522x-B adds WDOG1_B external reset */ 1196 if (info->model[4] == '2' && rev < 'B') 1197 ft_delprop_path(blob, WDOG1_PATH, 1198 "fsl,ext-reset-output"); 1199 } 1200 break; 1201 1202 case GW53xx: 1203 /* GW53xx-E adds WDOG1_B external reset */ 1204 if (rev < 'E') 1205 ft_delprop_path(blob, WDOG1_PATH, 1206 "fsl,ext-reset-output"); 1207 break; 1208 1209 case GW54xx: 1210 /* 1211 * disable serial2 node for GW54xx for compatibility with older 1212 * 3.10.x kernel that improperly had this node enabled in the DT 1213 */ 1214 i = fdt_path_offset(blob, UART1_PATH); 1215 if (i) 1216 fdt_del_node(blob, i); 1217 1218 /* GW54xx-E adds WDOG2_B external reset */ 1219 if (rev < 'E') 1220 ft_delprop_path(blob, WDOG2_PATH, 1221 "fsl,ext-reset-output"); 1222 break; 1223 1224 case GW551x: 1225 /* 1226 * isolate CSI0_DATA_EN for GW551x-A to work around errata 1227 * causing non functional digital video in (it is not hooked up) 1228 */ 1229 if (rev == 'A') { 1230 u32 *range = NULL; 1231 int len; 1232 const u32 *handle = NULL; 1233 1234 i = fdt_node_offset_by_compatible(blob, -1, 1235 "fsl,imx-tda1997x-video"); 1236 if (i) 1237 handle = fdt_getprop(blob, i, "pinctrl-0", 1238 NULL); 1239 if (handle) 1240 i = fdt_node_offset_by_phandle(blob, 1241 fdt32_to_cpu(*handle)); 1242 if (i) 1243 range = (u32 *)fdt_getprop(blob, i, "fsl,pins", 1244 &len); 1245 if (range) { 1246 len /= sizeof(u32); 1247 for (i = 0; i < len; i += 6) { 1248 u32 mux_reg = fdt32_to_cpu(range[i+0]); 1249 u32 conf_reg = fdt32_to_cpu(range[i+1]); 1250 /* mux PAD_CSI0_DATA_EN to GPIO */ 1251 if (is_cpu_type(MXC_CPU_MX6Q) && 1252 mux_reg == 0x260 && 1253 conf_reg == 0x630) 1254 range[i+3] = cpu_to_fdt32(0x5); 1255 else if (!is_cpu_type(MXC_CPU_MX6Q) && 1256 mux_reg == 0x08c && 1257 conf_reg == 0x3a0) 1258 range[i+3] = cpu_to_fdt32(0x5); 1259 } 1260 fdt_setprop_inplace(blob, i, "fsl,pins", range, 1261 len); 1262 } 1263 1264 /* set BT656 video format */ 1265 ft_sethdmiinfmt(blob, "yuv422bt656"); 1266 } 1267 1268 /* GW551x-C adds WDOG1_B external reset */ 1269 if (rev < 'C') 1270 ft_delprop_path(blob, WDOG1_PATH, 1271 "fsl,ext-reset-output"); 1272 break; 1273 } 1274 1275 /* Configure DIO */ 1276 for (i = 0; i < gpio_cfg[board_type].dio_num; i++) { 1277 struct dio_cfg *cfg = &gpio_cfg[board_type].dio_cfg[i]; 1278 char arg[10]; 1279 1280 sprintf(arg, "dio%d", i); 1281 if (!hwconfig(arg)) 1282 continue; 1283 if (hwconfig_subarg_cmp(arg, "mode", "pwm") && cfg->pwm_param) 1284 { 1285 char path[48]; 1286 sprintf(path, "/soc/aips-bus@02000000/pwm@%08x", 1287 0x02080000 + (0x4000 * (cfg->pwm_param - 1))); 1288 printf(" Enabling pwm%d for DIO%d\n", 1289 cfg->pwm_param, i); 1290 ft_enable_path(blob, path); 1291 } 1292 } 1293 1294 /* remove no-1-8-v if UHS-I support is present */ 1295 if (gpio_cfg[board_type].usd_vsel) { 1296 debug("Enabling UHS-I support\n"); 1297 ft_delprop_path(blob, "/soc/aips-bus@02100000/usdhc@02198000", 1298 "no-1-8-v"); 1299 } 1300 1301 #if defined(CONFIG_CMD_PCI) 1302 if (!getenv("nopcifixup")) 1303 ft_board_pci_fixup(blob, bd); 1304 #endif 1305 1306 /* 1307 * Peripheral Config: 1308 * remove nodes by alias path if EEPROM config tells us the 1309 * peripheral is not loaded on the board. 1310 */ 1311 if (getenv("fdt_noconfig")) { 1312 puts(" Skiping periperhal config (fdt_noconfig defined)\n"); 1313 return 0; 1314 } 1315 cfg = econfig; 1316 while (cfg->name) { 1317 if (!test_bit(cfg->bit, info->config)) { 1318 fdt_del_node_and_alias(blob, cfg->dtalias ? 1319 cfg->dtalias : cfg->name); 1320 } 1321 cfg++; 1322 } 1323 1324 return 0; 1325 } 1326 #endif /* CONFIG_OF_BOARD_SETUP */ 1327 1328 static struct mxc_serial_platdata ventana_mxc_serial_plat = { 1329 .reg = (struct mxc_uart *)UART2_BASE, 1330 }; 1331 1332 U_BOOT_DEVICE(ventana_serial) = { 1333 .name = "serial_mxc", 1334 .platdata = &ventana_mxc_serial_plat, 1335 }; 1336