1 /* 2 * Copyright (C) 2013 Gateworks Corporation 3 * 4 * Author: Tim Harvey <tharvey@gateworks.com> 5 * 6 * SPDX-License-Identifier: GPL-2.0+ 7 */ 8 9 #include <linux/errno.h> 10 #include <common.h> 11 #include <i2c.h> 12 #include <linux/ctype.h> 13 14 #include "ventana_eeprom.h" 15 #include "gsc.h" 16 17 /* 18 * The Gateworks System Controller will fail to ACK a master transaction if 19 * it is busy, which can occur during its 1HZ timer tick while reading ADC's. 20 * When this does occur, it will never be busy long enough to fail more than 21 * 2 back-to-back transfers. Thus we wrap i2c_read and i2c_write with 22 * 3 retries. 23 */ 24 int gsc_i2c_read(uchar chip, uint addr, int alen, uchar *buf, int len) 25 { 26 int retry = 3; 27 int n = 0; 28 int ret; 29 30 while (n++ < retry) { 31 ret = i2c_read(chip, addr, alen, buf, len); 32 if (!ret) 33 break; 34 debug("%s: 0x%02x 0x%02x retry%d: %d\n", __func__, chip, addr, 35 n, ret); 36 if (ret != -ENODEV) 37 break; 38 mdelay(10); 39 } 40 return ret; 41 } 42 43 int gsc_i2c_write(uchar chip, uint addr, int alen, uchar *buf, int len) 44 { 45 int retry = 3; 46 int n = 0; 47 int ret; 48 49 while (n++ < retry) { 50 ret = i2c_write(chip, addr, alen, buf, len); 51 if (!ret) 52 break; 53 debug("%s: 0x%02x 0x%02x retry%d: %d\n", __func__, chip, addr, 54 n, ret); 55 if (ret != -ENODEV) 56 break; 57 mdelay(10); 58 } 59 mdelay(100); 60 return ret; 61 } 62 63 static void read_hwmon(const char *name, uint reg, uint size) 64 { 65 unsigned char buf[3]; 66 uint ui; 67 68 printf("%-8s:", name); 69 memset(buf, 0, sizeof(buf)); 70 if (gsc_i2c_read(GSC_HWMON_ADDR, reg, 1, buf, size)) { 71 puts("fRD\n"); 72 } else { 73 ui = buf[0] | (buf[1]<<8) | (buf[2]<<16); 74 if (reg == GSC_HWMON_TEMP && ui > 0x8000) 75 ui -= 0xffff; 76 if (ui == 0xffffff) 77 puts("invalid\n"); 78 else 79 printf("%d\n", ui); 80 } 81 } 82 83 int gsc_info(int verbose) 84 { 85 unsigned char buf[16]; 86 87 i2c_set_bus_num(0); 88 if (gsc_i2c_read(GSC_SC_ADDR, 0, 1, buf, 16)) 89 return CMD_RET_FAILURE; 90 91 printf("GSC: v%d", buf[GSC_SC_FWVER]); 92 printf(" 0x%04x", buf[GSC_SC_FWCRC] | buf[GSC_SC_FWCRC+1]<<8); 93 printf(" WDT:%sabled", (buf[GSC_SC_CTRL1] & (1<<GSC_SC_CTRL1_WDEN)) 94 ? "en" : "dis"); 95 if (buf[GSC_SC_STATUS] & (1 << GSC_SC_IRQ_WATCHDOG)) { 96 buf[GSC_SC_STATUS] &= ~(1 << GSC_SC_IRQ_WATCHDOG); 97 puts(" WDT_RESET"); 98 gsc_i2c_write(GSC_SC_ADDR, GSC_SC_STATUS, 1, 99 &buf[GSC_SC_STATUS], 1); 100 } 101 if (!gsc_i2c_read(GSC_HWMON_ADDR, GSC_HWMON_TEMP, 1, buf, 2)) { 102 int ui = buf[0] | buf[1]<<8; 103 if (ui > 0x8000) 104 ui -= 0xffff; 105 printf(" board temp at %dC", ui / 10); 106 } 107 puts("\n"); 108 if (!verbose) 109 return CMD_RET_SUCCESS; 110 111 read_hwmon("Temp", GSC_HWMON_TEMP, 2); 112 read_hwmon("VIN", GSC_HWMON_VIN, 3); 113 read_hwmon("VBATT", GSC_HWMON_VBATT, 3); 114 read_hwmon("VDD_3P3", GSC_HWMON_VDD_3P3, 3); 115 read_hwmon("VDD_ARM", GSC_HWMON_VDD_CORE, 3); 116 read_hwmon("VDD_SOC", GSC_HWMON_VDD_SOC, 3); 117 read_hwmon("VDD_HIGH", GSC_HWMON_VDD_HIGH, 3); 118 read_hwmon("VDD_DDR", GSC_HWMON_VDD_DDR, 3); 119 read_hwmon("VDD_5P0", GSC_HWMON_VDD_5P0, 3); 120 if (strncasecmp((const char*) ventana_info.model, "GW553", 5)) 121 read_hwmon("VDD_2P5", GSC_HWMON_VDD_2P5, 3); 122 read_hwmon("VDD_1P8", GSC_HWMON_VDD_1P8, 3); 123 read_hwmon("VDD_IO2", GSC_HWMON_VDD_IO2, 3); 124 switch (ventana_info.model[3]) { 125 case '1': /* GW51xx */ 126 read_hwmon("VDD_IO3", GSC_HWMON_VDD_IO4, 3); /* -C rev */ 127 break; 128 case '2': /* GW52xx */ 129 break; 130 case '3': /* GW53xx */ 131 read_hwmon("VDD_IO4", GSC_HWMON_VDD_IO4, 3); /* -C rev */ 132 read_hwmon("VDD_GPS", GSC_HWMON_VDD_IO3, 3); 133 break; 134 case '4': /* GW54xx */ 135 read_hwmon("VDD_IO3", GSC_HWMON_VDD_IO4, 3); /* -C rev */ 136 read_hwmon("VDD_GPS", GSC_HWMON_VDD_IO3, 3); 137 break; 138 case '5': /* GW55xx */ 139 break; 140 } 141 return 0; 142 } 143 144 /* 145 * The Gateworks System Controller implements a boot 146 * watchdog (always enabled) as a workaround for IMX6 boot related 147 * errata such as: 148 * ERR005768 - no fix scheduled 149 * ERR006282 - fixed in silicon r1.2 150 * ERR007117 - fixed in silicon r1.3 151 * ERR007220 - fixed in silicon r1.3 152 * ERR007926 - no fix scheduled 153 * see http://cache.freescale.com/files/32bit/doc/errata/IMX6DQCE.pdf 154 * 155 * Disable the boot watchdog 156 */ 157 int gsc_boot_wd_disable(void) 158 { 159 u8 reg; 160 161 i2c_set_bus_num(CONFIG_I2C_GSC); 162 if (!gsc_i2c_read(GSC_SC_ADDR, GSC_SC_CTRL1, 1, ®, 1)) { 163 reg |= (1 << GSC_SC_CTRL1_WDDIS); 164 if (!gsc_i2c_write(GSC_SC_ADDR, GSC_SC_CTRL1, 1, ®, 1)) 165 return 0; 166 } 167 puts("Error: could not disable GSC Watchdog\n"); 168 return 1; 169 } 170 171 #ifdef CONFIG_CMD_GSC 172 static int do_gsc_sleep(cmd_tbl_t *cmdtp, int flag, int argc, 173 char * const argv[]) 174 { 175 unsigned char reg; 176 unsigned long secs = 0; 177 178 if (argc < 2) 179 return CMD_RET_USAGE; 180 181 secs = simple_strtoul(argv[1], NULL, 10); 182 printf("GSC Sleeping for %ld seconds\n", secs); 183 184 i2c_set_bus_num(0); 185 reg = (secs >> 24) & 0xff; 186 if (gsc_i2c_write(GSC_SC_ADDR, 9, 1, ®, 1)) 187 goto error; 188 reg = (secs >> 16) & 0xff; 189 if (gsc_i2c_write(GSC_SC_ADDR, 8, 1, ®, 1)) 190 goto error; 191 reg = (secs >> 8) & 0xff; 192 if (gsc_i2c_write(GSC_SC_ADDR, 7, 1, ®, 1)) 193 goto error; 194 reg = secs & 0xff; 195 if (gsc_i2c_write(GSC_SC_ADDR, 6, 1, ®, 1)) 196 goto error; 197 if (gsc_i2c_read(GSC_SC_ADDR, GSC_SC_CTRL1, 1, ®, 1)) 198 goto error; 199 reg |= (1 << 2); 200 if (gsc_i2c_write(GSC_SC_ADDR, GSC_SC_CTRL1, 1, ®, 1)) 201 goto error; 202 reg &= ~(1 << 2); 203 reg |= 0x3; 204 if (gsc_i2c_write(GSC_SC_ADDR, GSC_SC_CTRL1, 1, ®, 1)) 205 goto error; 206 207 return CMD_RET_SUCCESS; 208 209 error: 210 printf("i2c error\n"); 211 return CMD_RET_FAILURE; 212 } 213 214 static int do_gsc_wd(cmd_tbl_t *cmdtp, int flag, int argc, char * const argv[]) 215 { 216 unsigned char reg; 217 218 if (argc < 2) 219 return CMD_RET_USAGE; 220 221 if (strcasecmp(argv[1], "enable") == 0) { 222 int timeout = 0; 223 224 if (argc > 2) 225 timeout = simple_strtoul(argv[2], NULL, 10); 226 i2c_set_bus_num(0); 227 if (gsc_i2c_read(GSC_SC_ADDR, GSC_SC_CTRL1, 1, ®, 1)) 228 return CMD_RET_FAILURE; 229 reg &= ~((1 << GSC_SC_CTRL1_WDEN) | (1 << GSC_SC_CTRL1_WDTIME)); 230 if (timeout == 60) 231 reg |= (1 << GSC_SC_CTRL1_WDTIME); 232 else 233 timeout = 30; 234 reg |= (1 << GSC_SC_CTRL1_WDEN); 235 if (gsc_i2c_write(GSC_SC_ADDR, GSC_SC_CTRL1, 1, ®, 1)) 236 return CMD_RET_FAILURE; 237 printf("GSC Watchdog enabled with timeout=%d seconds\n", 238 timeout); 239 } else if (strcasecmp(argv[1], "disable") == 0) { 240 i2c_set_bus_num(0); 241 if (gsc_i2c_read(GSC_SC_ADDR, GSC_SC_CTRL1, 1, ®, 1)) 242 return CMD_RET_FAILURE; 243 reg &= ~((1 << GSC_SC_CTRL1_WDEN) | (1 << GSC_SC_CTRL1_WDTIME)); 244 if (gsc_i2c_write(GSC_SC_ADDR, GSC_SC_CTRL1, 1, ®, 1)) 245 return CMD_RET_FAILURE; 246 printf("GSC Watchdog disabled\n"); 247 } else { 248 return CMD_RET_USAGE; 249 } 250 return CMD_RET_SUCCESS; 251 } 252 253 static int do_gsc(cmd_tbl_t *cmdtp, int flag, int argc, char * const argv[]) 254 { 255 if (argc < 2) 256 return gsc_info(1); 257 258 if (strcasecmp(argv[1], "wd") == 0) 259 return do_gsc_wd(cmdtp, flag, --argc, ++argv); 260 else if (strcasecmp(argv[1], "sleep") == 0) 261 return do_gsc_sleep(cmdtp, flag, --argc, ++argv); 262 263 return CMD_RET_USAGE; 264 } 265 266 U_BOOT_CMD( 267 gsc, 4, 1, do_gsc, "GSC configuration", 268 "[wd enable [30|60]]|[wd disable]|[sleep <secs>]\n" 269 ); 270 271 #endif /* CONFIG_CMD_GSC */ 272