1 /* 2 * Copyright (C) 2013 Gateworks Corporation 3 * 4 * Author: Tim Harvey <tharvey@gateworks.com> 5 * 6 * SPDX-License-Identifier: GPL-2.0+ 7 */ 8 9 #include <asm/errno.h> 10 #include <common.h> 11 #include <i2c.h> 12 #include <linux/ctype.h> 13 14 #include "gsc.h" 15 16 /* 17 * The Gateworks System Controller will fail to ACK a master transaction if 18 * it is busy, which can occur during its 1HZ timer tick while reading ADC's. 19 * When this does occur, it will never be busy long enough to fail more than 20 * 2 back-to-back transfers. Thus we wrap i2c_read and i2c_write with 21 * 3 retries. 22 */ 23 int gsc_i2c_read(uchar chip, uint addr, int alen, uchar *buf, int len) 24 { 25 int retry = 3; 26 int n = 0; 27 int ret; 28 29 while (n++ < retry) { 30 ret = i2c_read(chip, addr, alen, buf, len); 31 if (!ret) 32 break; 33 debug("%s: 0x%02x 0x%02x retry%d: %d\n", __func__, chip, addr, 34 n, ret); 35 if (ret != -ENODEV) 36 break; 37 mdelay(10); 38 } 39 return ret; 40 } 41 42 int gsc_i2c_write(uchar chip, uint addr, int alen, uchar *buf, int len) 43 { 44 int retry = 3; 45 int n = 0; 46 int ret; 47 48 while (n++ < retry) { 49 ret = i2c_write(chip, addr, alen, buf, len); 50 if (!ret) 51 break; 52 debug("%s: 0x%02x 0x%02x retry%d: %d\n", __func__, chip, addr, 53 n, ret); 54 if (ret != -ENODEV) 55 break; 56 mdelay(10); 57 } 58 mdelay(100); 59 return ret; 60 } 61 62 static void read_hwmon(const char *name, uint reg, uint size) 63 { 64 unsigned char buf[3]; 65 uint ui; 66 67 printf("%-8s:", name); 68 memset(buf, 0, sizeof(buf)); 69 if (gsc_i2c_read(GSC_HWMON_ADDR, reg, 1, buf, size)) { 70 puts("fRD\n"); 71 } else { 72 ui = buf[0] | (buf[1]<<8) | (buf[2]<<16); 73 if (ui == 0xffffff) 74 puts("invalid\n"); 75 else 76 printf("%d\n", ui); 77 } 78 } 79 80 int gsc_info(int verbose) 81 { 82 const char *model = getenv("model"); 83 unsigned char buf[16]; 84 85 i2c_set_bus_num(0); 86 if (gsc_i2c_read(GSC_SC_ADDR, 0, 1, buf, 16)) 87 return CMD_RET_FAILURE; 88 89 printf("GSC: v%d", buf[GSC_SC_FWVER]); 90 printf(" 0x%04x", buf[GSC_SC_FWCRC] | buf[GSC_SC_FWCRC+1]<<8); 91 printf(" WDT:%sabled", (buf[GSC_SC_CTRL1] & (1<<GSC_SC_CTRL1_WDEN)) 92 ? "en" : "dis"); 93 if (buf[GSC_SC_STATUS] & (1 << GSC_SC_IRQ_WATCHDOG)) { 94 buf[GSC_SC_STATUS] &= ~(1 << GSC_SC_IRQ_WATCHDOG); 95 puts(" WDT_RESET"); 96 gsc_i2c_write(GSC_SC_ADDR, GSC_SC_STATUS, 1, 97 &buf[GSC_SC_STATUS], 1); 98 } 99 puts("\n"); 100 if (!verbose) 101 return CMD_RET_SUCCESS; 102 103 read_hwmon("Temp", GSC_HWMON_TEMP, 2); 104 read_hwmon("VIN", GSC_HWMON_VIN, 3); 105 read_hwmon("VBATT", GSC_HWMON_VBATT, 3); 106 read_hwmon("VDD_3P3", GSC_HWMON_VDD_3P3, 3); 107 read_hwmon("VDD_ARM", GSC_HWMON_VDD_CORE, 3); 108 read_hwmon("VDD_SOC", GSC_HWMON_VDD_SOC, 3); 109 read_hwmon("VDD_HIGH", GSC_HWMON_VDD_HIGH, 3); 110 read_hwmon("VDD_DDR", GSC_HWMON_VDD_DDR, 3); 111 read_hwmon("VDD_5P0", GSC_HWMON_VDD_5P0, 3); 112 read_hwmon("VDD_2P5", GSC_HWMON_VDD_2P5, 3); 113 read_hwmon("VDD_1P8", GSC_HWMON_VDD_1P8, 3); 114 read_hwmon("VDD_IO2", GSC_HWMON_VDD_IO2, 3); 115 switch (model[3]) { 116 case '1': /* GW51xx */ 117 read_hwmon("VDD_IO3", GSC_HWMON_VDD_IO4, 3); /* -C rev */ 118 break; 119 case '2': /* GW52xx */ 120 break; 121 case '3': /* GW53xx */ 122 read_hwmon("VDD_IO4", GSC_HWMON_VDD_IO4, 3); /* -C rev */ 123 read_hwmon("VDD_GPS", GSC_HWMON_VDD_IO3, 3); 124 break; 125 case '4': /* GW54xx */ 126 read_hwmon("VDD_IO3", GSC_HWMON_VDD_IO4, 3); /* -C rev */ 127 read_hwmon("VDD_GPS", GSC_HWMON_VDD_IO3, 3); 128 break; 129 case '5': /* GW55xx */ 130 break; 131 } 132 return 0; 133 } 134 135 /* 136 * The Gateworks System Controller implements a boot 137 * watchdog (always enabled) as a workaround for IMX6 boot related 138 * errata such as: 139 * ERR005768 - no fix scheduled 140 * ERR006282 - fixed in silicon r1.2 141 * ERR007117 - fixed in silicon r1.3 142 * ERR007220 - fixed in silicon r1.3 143 * ERR007926 - no fix scheduled 144 * see http://cache.freescale.com/files/32bit/doc/errata/IMX6DQCE.pdf 145 * 146 * Disable the boot watchdog 147 */ 148 int gsc_boot_wd_disable(void) 149 { 150 u8 reg; 151 152 i2c_set_bus_num(CONFIG_I2C_GSC); 153 if (!gsc_i2c_read(GSC_SC_ADDR, GSC_SC_CTRL1, 1, ®, 1)) { 154 reg |= (1 << GSC_SC_CTRL1_WDDIS); 155 if (!gsc_i2c_write(GSC_SC_ADDR, GSC_SC_CTRL1, 1, ®, 1)) 156 return 0; 157 } 158 puts("Error: could not disable GSC Watchdog\n"); 159 return 1; 160 } 161 162 #ifdef CONFIG_CMD_GSC 163 static int do_gsc_wd(cmd_tbl_t *cmdtp, int flag, int argc, char * const argv[]) 164 { 165 unsigned char reg; 166 167 if (argc < 2) 168 return CMD_RET_USAGE; 169 170 if (strcasecmp(argv[1], "enable") == 0) { 171 int timeout = 0; 172 173 if (argc > 2) 174 timeout = simple_strtoul(argv[2], NULL, 10); 175 i2c_set_bus_num(0); 176 if (gsc_i2c_read(GSC_SC_ADDR, GSC_SC_CTRL1, 1, ®, 1)) 177 return CMD_RET_FAILURE; 178 reg &= ~((1 << GSC_SC_CTRL1_WDEN) | (1 << GSC_SC_CTRL1_WDTIME)); 179 if (timeout == 60) 180 reg |= (1 << GSC_SC_CTRL1_WDTIME); 181 else 182 timeout = 30; 183 reg |= (1 << GSC_SC_CTRL1_WDEN); 184 if (gsc_i2c_write(GSC_SC_ADDR, GSC_SC_CTRL1, 1, ®, 1)) 185 return CMD_RET_FAILURE; 186 printf("GSC Watchdog enabled with timeout=%d seconds\n", 187 timeout); 188 } else if (strcasecmp(argv[1], "disable") == 0) { 189 i2c_set_bus_num(0); 190 if (gsc_i2c_read(GSC_SC_ADDR, GSC_SC_CTRL1, 1, ®, 1)) 191 return CMD_RET_FAILURE; 192 reg &= ~((1 << GSC_SC_CTRL1_WDEN) | (1 << GSC_SC_CTRL1_WDTIME)); 193 if (gsc_i2c_write(GSC_SC_ADDR, GSC_SC_CTRL1, 1, ®, 1)) 194 return CMD_RET_FAILURE; 195 printf("GSC Watchdog disabled\n"); 196 } else { 197 return CMD_RET_USAGE; 198 } 199 return CMD_RET_SUCCESS; 200 } 201 202 static int do_gsc(cmd_tbl_t *cmdtp, int flag, int argc, char * const argv[]) 203 { 204 if (argc < 2) 205 return gsc_info(1); 206 207 if (strcasecmp(argv[1], "wd") == 0) 208 return do_gsc_wd(cmdtp, flag, --argc, ++argv); 209 210 return CMD_RET_USAGE; 211 } 212 213 U_BOOT_CMD( 214 gsc, 4, 1, do_gsc, "GSC configuration", 215 "[wd enable [30|60]]|[wd disable]\n" 216 ); 217 218 #endif /* CONFIG_CMD_GSC */ 219