1 /* 2 * Copyright 2013 Freescale Semiconductor, Inc. 3 * 4 * SPDX-License-Identifier: GPL-2.0+ 5 */ 6 7 #include <common.h> 8 #include <asm/io.h> 9 #include <asm/arch/imx-regs.h> 10 #include <asm/arch/iomux-vf610.h> 11 #include <asm/arch/crm_regs.h> 12 #include <asm/arch/clock.h> 13 #include <mmc.h> 14 #include <fsl_esdhc.h> 15 #include <miiphy.h> 16 #include <netdev.h> 17 #include <i2c.h> 18 19 DECLARE_GLOBAL_DATA_PTR; 20 21 #define UART_PAD_CTRL (PAD_CTL_PUS_100K_UP | PAD_CTL_SPEED_MED | \ 22 PAD_CTL_DSE_25ohm | PAD_CTL_OBE_IBE_ENABLE) 23 24 #define ESDHC_PAD_CTRL (PAD_CTL_PUS_100K_UP | PAD_CTL_SPEED_HIGH | \ 25 PAD_CTL_DSE_20ohm | PAD_CTL_OBE_IBE_ENABLE) 26 27 #define ENET_PAD_CTRL (PAD_CTL_PUS_47K_UP | PAD_CTL_SPEED_HIGH | \ 28 PAD_CTL_DSE_50ohm | PAD_CTL_OBE_IBE_ENABLE) 29 30 void setup_iomux_ddr(void) 31 { 32 static const iomux_v3_cfg_t ddr_pads[] = { 33 VF610_PAD_DDR_A15__DDR_A_15, 34 VF610_PAD_DDR_A14__DDR_A_14, 35 VF610_PAD_DDR_A13__DDR_A_13, 36 VF610_PAD_DDR_A12__DDR_A_12, 37 VF610_PAD_DDR_A11__DDR_A_11, 38 VF610_PAD_DDR_A10__DDR_A_10, 39 VF610_PAD_DDR_A9__DDR_A_9, 40 VF610_PAD_DDR_A8__DDR_A_8, 41 VF610_PAD_DDR_A7__DDR_A_7, 42 VF610_PAD_DDR_A6__DDR_A_6, 43 VF610_PAD_DDR_A5__DDR_A_5, 44 VF610_PAD_DDR_A4__DDR_A_4, 45 VF610_PAD_DDR_A3__DDR_A_3, 46 VF610_PAD_DDR_A2__DDR_A_2, 47 VF610_PAD_DDR_A1__DDR_A_1, 48 VF610_PAD_DDR_A0__DDR_A_0, 49 VF610_PAD_DDR_BA2__DDR_BA_2, 50 VF610_PAD_DDR_BA1__DDR_BA_1, 51 VF610_PAD_DDR_BA0__DDR_BA_0, 52 VF610_PAD_DDR_CAS__DDR_CAS_B, 53 VF610_PAD_DDR_CKE__DDR_CKE_0, 54 VF610_PAD_DDR_CLK__DDR_CLK_0, 55 VF610_PAD_DDR_CS__DDR_CS_B_0, 56 VF610_PAD_DDR_D15__DDR_D_15, 57 VF610_PAD_DDR_D14__DDR_D_14, 58 VF610_PAD_DDR_D13__DDR_D_13, 59 VF610_PAD_DDR_D12__DDR_D_12, 60 VF610_PAD_DDR_D11__DDR_D_11, 61 VF610_PAD_DDR_D10__DDR_D_10, 62 VF610_PAD_DDR_D9__DDR_D_9, 63 VF610_PAD_DDR_D8__DDR_D_8, 64 VF610_PAD_DDR_D7__DDR_D_7, 65 VF610_PAD_DDR_D6__DDR_D_6, 66 VF610_PAD_DDR_D5__DDR_D_5, 67 VF610_PAD_DDR_D4__DDR_D_4, 68 VF610_PAD_DDR_D3__DDR_D_3, 69 VF610_PAD_DDR_D2__DDR_D_2, 70 VF610_PAD_DDR_D1__DDR_D_1, 71 VF610_PAD_DDR_D0__DDR_D_0, 72 VF610_PAD_DDR_DQM1__DDR_DQM_1, 73 VF610_PAD_DDR_DQM0__DDR_DQM_0, 74 VF610_PAD_DDR_DQS1__DDR_DQS_1, 75 VF610_PAD_DDR_DQS0__DDR_DQS_0, 76 VF610_PAD_DDR_RAS__DDR_RAS_B, 77 VF610_PAD_DDR_WE__DDR_WE_B, 78 VF610_PAD_DDR_ODT1__DDR_ODT_0, 79 VF610_PAD_DDR_ODT0__DDR_ODT_1, 80 VF610_PAD_DDR_RESETB, 81 }; 82 83 imx_iomux_v3_setup_multiple_pads(ddr_pads, ARRAY_SIZE(ddr_pads)); 84 } 85 86 void ddr_phy_init(void) 87 { 88 struct ddrmr_regs *ddrmr = (struct ddrmr_regs *)DDR_BASE_ADDR; 89 90 writel(DDRMC_PHY_DQ_TIMING, &ddrmr->phy[0]); 91 writel(DDRMC_PHY_DQ_TIMING, &ddrmr->phy[16]); 92 writel(DDRMC_PHY_DQ_TIMING, &ddrmr->phy[32]); 93 94 writel(DDRMC_PHY_DQS_TIMING, &ddrmr->phy[1]); 95 writel(DDRMC_PHY_DQS_TIMING, &ddrmr->phy[17]); 96 97 writel(DDRMC_PHY_CTRL, &ddrmr->phy[2]); 98 writel(DDRMC_PHY_CTRL, &ddrmr->phy[18]); 99 writel(DDRMC_PHY_CTRL, &ddrmr->phy[34]); 100 101 writel(DDRMC_PHY_MASTER_CTRL, &ddrmr->phy[3]); 102 writel(DDRMC_PHY_MASTER_CTRL, &ddrmr->phy[19]); 103 writel(DDRMC_PHY_MASTER_CTRL, &ddrmr->phy[35]); 104 105 writel(DDRMC_PHY_SLAVE_CTRL, &ddrmr->phy[4]); 106 writel(DDRMC_PHY_SLAVE_CTRL, &ddrmr->phy[20]); 107 writel(DDRMC_PHY_SLAVE_CTRL, &ddrmr->phy[36]); 108 109 /* LPDDR2 only parameter */ 110 writel(DDRMC_PHY_OFF, &ddrmr->phy[49]); 111 112 writel(DDRMC_PHY50_DDR3_MODE | DDRMC_PHY50_EN_SW_HALF_CYCLE, 113 &ddrmr->phy[50]); 114 115 /* Processor Pad ODT settings */ 116 writel(DDRMC_PHY_PROC_PAD_ODT, &ddrmr->phy[52]); 117 } 118 119 void ddr_ctrl_init(void) 120 { 121 struct ddrmr_regs *ddrmr = (struct ddrmr_regs *)DDR_BASE_ADDR; 122 123 writel(DDRMC_CR00_DRAM_CLASS_DDR3, &ddrmr->cr[0]); 124 writel(DDRMC_CR02_DRAM_TINIT(32), &ddrmr->cr[2]); 125 writel(DDRMC_CR10_TRST_PWRON(80000), &ddrmr->cr[10]); 126 127 writel(DDRMC_CR11_CKE_INACTIVE(200000), &ddrmr->cr[11]); 128 writel(DDRMC_CR12_WRLAT(5) | DDRMC_CR12_CASLAT_LIN(12), &ddrmr->cr[12]); 129 writel(DDRMC_CR13_TRC(21) | DDRMC_CR13_TRRD(4) | DDRMC_CR13_TCCD(4), 130 &ddrmr->cr[13]); 131 writel(DDRMC_CR14_TFAW(20) | DDRMC_CR14_TRP(6) | DDRMC_CR14_TWTR(4) | 132 DDRMC_CR14_TRAS_MIN(15), &ddrmr->cr[14]); 133 writel(DDRMC_CR16_TMRD(4) | DDRMC_CR16_TRTP(4), &ddrmr->cr[16]); 134 writel(DDRMC_CR17_TRAS_MAX(28080) | DDRMC_CR17_TMOD(12), 135 &ddrmr->cr[17]); 136 writel(DDRMC_CR18_TCKESR(4) | DDRMC_CR18_TCKE(3), &ddrmr->cr[18]); 137 138 writel(DDRMC_CR20_AP_EN, &ddrmr->cr[20]); 139 writel(DDRMC_CR21_TRCD_INT(6) | DDRMC_CR21_CCMAP_EN, &ddrmr->cr[21]); 140 141 writel(DDRMC_CR22_TDAL(12), &ddrmr->cr[22]); 142 writel(DDRMC_CR23_BSTLEN(3) | DDRMC_CR23_TDLL(512), &ddrmr->cr[23]); 143 writel(DDRMC_CR24_TRP_AB(6), &ddrmr->cr[24]); 144 145 writel(DDRMC_CR25_TREF_EN, &ddrmr->cr[25]); 146 writel(DDRMC_CR26_TREF(3120) | DDRMC_CR26_TRFC(44), &ddrmr->cr[26]); 147 writel(DDRMC_CR28_TREF_INT(0), &ddrmr->cr[28]); 148 writel(DDRMC_CR29_TPDEX(3), &ddrmr->cr[29]); 149 150 writel(DDRMC_CR30_TXPDLL(10), &ddrmr->cr[30]); 151 writel(DDRMC_CR31_TXSNR(48) | DDRMC_CR31_TXSR(468), &ddrmr->cr[31]); 152 writel(DDRMC_CR33_EN_QK_SREF, &ddrmr->cr[33]); 153 writel(DDRMC_CR34_CKSRX(5) | DDRMC_CR34_CKSRE(5), &ddrmr->cr[34]); 154 155 writel(DDRMC_CR38_FREQ_CHG_EN(0), &ddrmr->cr[38]); 156 writel(DDRMC_CR39_PHY_INI_COM(1024) | DDRMC_CR39_PHY_INI_STA(16) | 157 DDRMC_CR39_FRQ_CH_DLLOFF(2), &ddrmr->cr[39]); 158 159 writel(DDRMC_CR41_PHY_INI_STRT_INI_DIS, &ddrmr->cr[41]); 160 writel(DDRMC_CR48_MR1_DA_0(70) | DDRMC_CR48_MR0_DA_0(1056), 161 &ddrmr->cr[48]); 162 163 writel(DDRMC_CR66_ZQCL(256) | DDRMC_CR66_ZQINIT(512), &ddrmr->cr[66]); 164 writel(DDRMC_CR67_ZQCS(64), &ddrmr->cr[67]); 165 writel(DDRMC_CR69_ZQ_ON_SREF_EX(2), &ddrmr->cr[69]); 166 167 writel(DDRMC_CR70_REF_PER_ZQ(64), &ddrmr->cr[70]); 168 writel(DDRMC_CR72_ZQCS_ROTATE(0), &ddrmr->cr[72]); 169 170 writel(DDRMC_CR73_APREBIT(10) | DDRMC_CR73_COL_DIFF(1) | 171 DDRMC_CR73_ROW_DIFF(3), &ddrmr->cr[73]); 172 writel(DDRMC_CR74_BANKSPLT_EN | DDRMC_CR74_ADDR_CMP_EN | 173 DDRMC_CR74_CMD_AGE_CNT(64) | DDRMC_CR74_AGE_CNT(64), 174 &ddrmr->cr[74]); 175 writel(DDRMC_CR75_RW_PG_EN | DDRMC_CR75_RW_EN | DDRMC_CR75_PRI_EN | 176 DDRMC_CR75_PLEN, &ddrmr->cr[75]); 177 writel(DDRMC_CR76_NQENT_ACTDIS(3) | DDRMC_CR76_D_RW_G_BKCN(3) | 178 DDRMC_CR76_W2R_SPLT_EN, &ddrmr->cr[76]); 179 writel(DDRMC_CR77_CS_MAP | DDRMC_CR77_DI_RD_INTLEAVE | 180 DDRMC_CR77_SWAP_EN, &ddrmr->cr[77]); 181 writel(DDRMC_CR78_Q_FULLNESS(7) | DDRMC_CR78_BUR_ON_FLY_BIT(12), 182 &ddrmr->cr[78]); 183 writel(DDRMC_CR79_CTLUPD_AREF(0), &ddrmr->cr[79]); 184 185 writel(DDRMC_CR82_INT_MASK, &ddrmr->cr[82]); 186 187 writel(DDRMC_CR87_ODT_WR_MAPCS0, &ddrmr->cr[87]); 188 writel(DDRMC_CR88_TODTL_CMD(4), &ddrmr->cr[88]); 189 writel(DDRMC_CR89_AODT_RWSMCS(2), &ddrmr->cr[89]); 190 191 writel(DDRMC_CR91_R2W_SMCSDL(2), &ddrmr->cr[91]); 192 writel(DDRMC_CR96_WLMRD(40) | DDRMC_CR96_WLDQSEN(25), &ddrmr->cr[96]); 193 writel(DDRMC_CR97_WRLVL_EN, &ddrmr->cr[97]); 194 writel(DDRMC_CR98_WRLVL_DL_0, &ddrmr->cr[98]); 195 writel(DDRMC_CR99_WRLVL_DL_1, &ddrmr->cr[99]); 196 197 writel(DDRMC_CR102_RDLVL_GT_REGEN | DDRMC_CR102_RDLVL_REG_EN, 198 &ddrmr->cr[102]); 199 200 writel(DDRMC_CR105_RDLVL_DL_0(0), &ddrmr->cr[105]); 201 writel(DDRMC_CR106_RDLVL_GTDL_0(4), &ddrmr->cr[106]); 202 writel(DDRMC_CR110_RDLVL_GTDL_1(4), &ddrmr->cr[110]); 203 writel(DDRMC_CR114_RDLVL_GTDL_2(0), &ddrmr->cr[114]); 204 writel(DDRMC_CR115_RDLVL_GTDL_2(0), &ddrmr->cr[115]); 205 206 writel(DDRMC_CR117_AXI0_W_PRI(0) | DDRMC_CR117_AXI0_R_PRI(0), 207 &ddrmr->cr[117]); 208 writel(DDRMC_CR118_AXI1_W_PRI(1) | DDRMC_CR118_AXI1_R_PRI(1), 209 &ddrmr->cr[118]); 210 211 writel(DDRMC_CR120_AXI0_PRI1_RPRI(2) | DDRMC_CR120_AXI0_PRI0_RPRI(2), 212 &ddrmr->cr[120]); 213 writel(DDRMC_CR121_AXI0_PRI3_RPRI(2) | DDRMC_CR121_AXI0_PRI2_RPRI(2), 214 &ddrmr->cr[121]); 215 writel(DDRMC_CR122_AXI1_PRI1_RPRI(1) | DDRMC_CR122_AXI1_PRI0_RPRI(1) | 216 DDRMC_CR122_AXI0_PRIRLX(100), &ddrmr->cr[122]); 217 writel(DDRMC_CR123_AXI1_P_ODR_EN | DDRMC_CR123_AXI1_PRI3_RPRI(1) | 218 DDRMC_CR123_AXI1_PRI2_RPRI(1), &ddrmr->cr[123]); 219 writel(DDRMC_CR124_AXI1_PRIRLX(100), &ddrmr->cr[124]); 220 221 writel(DDRMC_CR126_PHY_RDLAT(8), &ddrmr->cr[126]); 222 writel(DDRMC_CR132_WRLAT_ADJ(5) | DDRMC_CR132_RDLAT_ADJ(6), 223 &ddrmr->cr[132]); 224 writel(DDRMC_CR137_PHYCTL_DL(2), &ddrmr->cr[137]); 225 writel(DDRMC_CR138_PHY_WRLV_MXDL(256) | DDRMC_CR138_PHYDRAM_CK_EN(1), 226 &ddrmr->cr[138]); 227 writel(DDRMC_CR139_PHY_WRLV_RESPLAT(4) | DDRMC_CR139_PHY_WRLV_LOAD(7) | 228 DDRMC_CR139_PHY_WRLV_DLL(3) | DDRMC_CR139_PHY_WRLV_EN(3), 229 &ddrmr->cr[139]); 230 writel(DDRMC_CR140_PHY_WRLV_WW(64), &ddrmr->cr[140]); 231 writel(DDRMC_CR143_RDLV_GAT_MXDL(1536) | DDRMC_CR143_RDLV_MXDL(128), 232 &ddrmr->cr[143]); 233 writel(DDRMC_CR144_PHY_RDLVL_RES(4) | DDRMC_CR144_PHY_RDLV_LOAD(7) | 234 DDRMC_CR144_PHY_RDLV_DLL(3) | DDRMC_CR144_PHY_RDLV_EN(3), 235 &ddrmr->cr[144]); 236 writel(DDRMC_CR145_PHY_RDLV_RR(64), &ddrmr->cr[145]); 237 writel(DDRMC_CR146_PHY_RDLVL_RESP(64), &ddrmr->cr[146]); 238 writel(DDRMC_CR147_RDLV_RESP_MASK(983040), &ddrmr->cr[147]); 239 writel(DDRMC_CR148_RDLV_GATE_RESP_MASK(983040), &ddrmr->cr[148]); 240 writel(DDRMC_CR151_RDLV_GAT_DQ_ZERO_CNT(1) | 241 DDRMC_CR151_RDLVL_DQ_ZERO_CNT(1), &ddrmr->cr[151]); 242 243 writel(DDRMC_CR154_PAD_ZQ_EARLY_CMP_EN_TIMER(13) | 244 DDRMC_CR154_PAD_ZQ_MODE(1) | DDRMC_CR154_DDR_SEL_PAD_CONTR(3) | 245 DDRMC_CR154_PAD_ZQ_HW_FOR(1), &ddrmr->cr[154]); 246 writel(DDRMC_CR155_PAD_ODT_BYTE1(2) | DDRMC_CR155_PAD_ODT_BYTE0(2), 247 &ddrmr->cr[155]); 248 writel(DDRMC_CR158_TWR(6), &ddrmr->cr[158]); 249 writel(DDRMC_CR161_ODT_EN(1) | DDRMC_CR161_TODTH_RD(2) | 250 DDRMC_CR161_TODTH_WR(2), &ddrmr->cr[161]); 251 252 ddr_phy_init(); 253 254 writel(DDRMC_CR00_DRAM_CLASS_DDR3 | DDRMC_CR00_START, &ddrmr->cr[0]); 255 256 udelay(200); 257 } 258 259 int dram_init(void) 260 { 261 setup_iomux_ddr(); 262 263 ddr_ctrl_init(); 264 gd->ram_size = get_ram_size((void *)PHYS_SDRAM, PHYS_SDRAM_SIZE); 265 266 return 0; 267 } 268 269 static void setup_iomux_uart(void) 270 { 271 static const iomux_v3_cfg_t uart1_pads[] = { 272 NEW_PAD_CTRL(VF610_PAD_PTB4__UART1_TX, UART_PAD_CTRL), 273 NEW_PAD_CTRL(VF610_PAD_PTB5__UART1_RX, UART_PAD_CTRL), 274 }; 275 276 imx_iomux_v3_setup_multiple_pads(uart1_pads, ARRAY_SIZE(uart1_pads)); 277 } 278 279 static void setup_iomux_enet(void) 280 { 281 static const iomux_v3_cfg_t enet0_pads[] = { 282 NEW_PAD_CTRL(VF610_PAD_PTA6__RMII0_CLKIN, ENET_PAD_CTRL), 283 NEW_PAD_CTRL(VF610_PAD_PTC1__RMII0_MDIO, ENET_PAD_CTRL), 284 NEW_PAD_CTRL(VF610_PAD_PTC0__RMII0_MDC, ENET_PAD_CTRL), 285 NEW_PAD_CTRL(VF610_PAD_PTC2__RMII0_CRS_DV, ENET_PAD_CTRL), 286 NEW_PAD_CTRL(VF610_PAD_PTC3__RMII0_RD1, ENET_PAD_CTRL), 287 NEW_PAD_CTRL(VF610_PAD_PTC4__RMII0_RD0, ENET_PAD_CTRL), 288 NEW_PAD_CTRL(VF610_PAD_PTC5__RMII0_RXER, ENET_PAD_CTRL), 289 NEW_PAD_CTRL(VF610_PAD_PTC6__RMII0_TD1, ENET_PAD_CTRL), 290 NEW_PAD_CTRL(VF610_PAD_PTC7__RMII0_TD0, ENET_PAD_CTRL), 291 NEW_PAD_CTRL(VF610_PAD_PTC8__RMII0_TXEN, ENET_PAD_CTRL), 292 }; 293 294 imx_iomux_v3_setup_multiple_pads(enet0_pads, ARRAY_SIZE(enet0_pads)); 295 } 296 297 static void setup_iomux_i2c(void) 298 { 299 static const iomux_v3_cfg_t i2c0_pads[] = { 300 VF610_PAD_PTB14__I2C0_SCL, 301 VF610_PAD_PTB15__I2C0_SDA, 302 }; 303 304 imx_iomux_v3_setup_multiple_pads(i2c0_pads, ARRAY_SIZE(i2c0_pads)); 305 } 306 307 #ifdef CONFIG_NAND_VF610_NFC 308 static void setup_iomux_nfc(void) 309 { 310 static const iomux_v3_cfg_t nfc_pads[] = { 311 VF610_PAD_PTD31__NF_IO15, 312 VF610_PAD_PTD30__NF_IO14, 313 VF610_PAD_PTD29__NF_IO13, 314 VF610_PAD_PTD28__NF_IO12, 315 VF610_PAD_PTD27__NF_IO11, 316 VF610_PAD_PTD26__NF_IO10, 317 VF610_PAD_PTD25__NF_IO9, 318 VF610_PAD_PTD24__NF_IO8, 319 VF610_PAD_PTD23__NF_IO7, 320 VF610_PAD_PTD22__NF_IO6, 321 VF610_PAD_PTD21__NF_IO5, 322 VF610_PAD_PTD20__NF_IO4, 323 VF610_PAD_PTD19__NF_IO3, 324 VF610_PAD_PTD18__NF_IO2, 325 VF610_PAD_PTD17__NF_IO1, 326 VF610_PAD_PTD16__NF_IO0, 327 VF610_PAD_PTB24__NF_WE_B, 328 VF610_PAD_PTB25__NF_CE0_B, 329 VF610_PAD_PTB27__NF_RE_B, 330 VF610_PAD_PTC26__NF_RB_B, 331 VF610_PAD_PTC27__NF_ALE, 332 VF610_PAD_PTC28__NF_CLE 333 }; 334 335 imx_iomux_v3_setup_multiple_pads(nfc_pads, ARRAY_SIZE(nfc_pads)); 336 } 337 #endif 338 339 340 static void setup_iomux_qspi(void) 341 { 342 static const iomux_v3_cfg_t qspi0_pads[] = { 343 VF610_PAD_PTD0__QSPI0_A_QSCK, 344 VF610_PAD_PTD1__QSPI0_A_CS0, 345 VF610_PAD_PTD2__QSPI0_A_DATA3, 346 VF610_PAD_PTD3__QSPI0_A_DATA2, 347 VF610_PAD_PTD4__QSPI0_A_DATA1, 348 VF610_PAD_PTD5__QSPI0_A_DATA0, 349 VF610_PAD_PTD7__QSPI0_B_QSCK, 350 VF610_PAD_PTD8__QSPI0_B_CS0, 351 VF610_PAD_PTD9__QSPI0_B_DATA3, 352 VF610_PAD_PTD10__QSPI0_B_DATA2, 353 VF610_PAD_PTD11__QSPI0_B_DATA1, 354 VF610_PAD_PTD12__QSPI0_B_DATA0, 355 }; 356 357 imx_iomux_v3_setup_multiple_pads(qspi0_pads, ARRAY_SIZE(qspi0_pads)); 358 } 359 360 #ifdef CONFIG_FSL_ESDHC 361 struct fsl_esdhc_cfg esdhc_cfg[1] = { 362 {ESDHC1_BASE_ADDR}, 363 }; 364 365 int board_mmc_getcd(struct mmc *mmc) 366 { 367 /* eSDHC1 is always present */ 368 return 1; 369 } 370 371 int board_mmc_init(bd_t *bis) 372 { 373 static const iomux_v3_cfg_t esdhc1_pads[] = { 374 NEW_PAD_CTRL(VF610_PAD_PTA24__ESDHC1_CLK, ESDHC_PAD_CTRL), 375 NEW_PAD_CTRL(VF610_PAD_PTA25__ESDHC1_CMD, ESDHC_PAD_CTRL), 376 NEW_PAD_CTRL(VF610_PAD_PTA26__ESDHC1_DAT0, ESDHC_PAD_CTRL), 377 NEW_PAD_CTRL(VF610_PAD_PTA27__ESDHC1_DAT1, ESDHC_PAD_CTRL), 378 NEW_PAD_CTRL(VF610_PAD_PTA28__ESDHC1_DAT2, ESDHC_PAD_CTRL), 379 NEW_PAD_CTRL(VF610_PAD_PTA29__ESDHC1_DAT3, ESDHC_PAD_CTRL), 380 }; 381 382 esdhc_cfg[0].sdhc_clk = mxc_get_clock(MXC_ESDHC_CLK); 383 384 imx_iomux_v3_setup_multiple_pads( 385 esdhc1_pads, ARRAY_SIZE(esdhc1_pads)); 386 387 return fsl_esdhc_initialize(bis, &esdhc_cfg[0]); 388 } 389 #endif 390 391 static void clock_init(void) 392 { 393 struct ccm_reg *ccm = (struct ccm_reg *)CCM_BASE_ADDR; 394 struct anadig_reg *anadig = (struct anadig_reg *)ANADIG_BASE_ADDR; 395 396 clrsetbits_le32(&ccm->ccgr0, CCM_REG_CTRL_MASK, 397 CCM_CCGR0_UART1_CTRL_MASK); 398 clrsetbits_le32(&ccm->ccgr1, CCM_REG_CTRL_MASK, 399 CCM_CCGR1_PIT_CTRL_MASK | CCM_CCGR1_WDOGA5_CTRL_MASK); 400 clrsetbits_le32(&ccm->ccgr2, CCM_REG_CTRL_MASK, 401 CCM_CCGR2_IOMUXC_CTRL_MASK | CCM_CCGR2_PORTA_CTRL_MASK | 402 CCM_CCGR2_PORTB_CTRL_MASK | CCM_CCGR2_PORTC_CTRL_MASK | 403 CCM_CCGR2_PORTD_CTRL_MASK | CCM_CCGR2_PORTE_CTRL_MASK | 404 CCM_CCGR2_QSPI0_CTRL_MASK); 405 clrsetbits_le32(&ccm->ccgr3, CCM_REG_CTRL_MASK, 406 CCM_CCGR3_ANADIG_CTRL_MASK); 407 clrsetbits_le32(&ccm->ccgr4, CCM_REG_CTRL_MASK, 408 CCM_CCGR4_WKUP_CTRL_MASK | CCM_CCGR4_CCM_CTRL_MASK | 409 CCM_CCGR4_GPC_CTRL_MASK | CCM_CCGR4_I2C0_CTRL_MASK); 410 clrsetbits_le32(&ccm->ccgr6, CCM_REG_CTRL_MASK, 411 CCM_CCGR6_OCOTP_CTRL_MASK | CCM_CCGR6_DDRMC_CTRL_MASK); 412 clrsetbits_le32(&ccm->ccgr7, CCM_REG_CTRL_MASK, 413 CCM_CCGR7_SDHC1_CTRL_MASK); 414 clrsetbits_le32(&ccm->ccgr9, CCM_REG_CTRL_MASK, 415 CCM_CCGR9_FEC0_CTRL_MASK | CCM_CCGR9_FEC1_CTRL_MASK); 416 clrsetbits_le32(&ccm->ccgr10, CCM_REG_CTRL_MASK, 417 CCM_CCGR10_NFC_CTRL_MASK); 418 419 clrsetbits_le32(&anadig->pll2_ctrl, ANADIG_PLL2_CTRL_POWERDOWN, 420 ANADIG_PLL2_CTRL_ENABLE | ANADIG_PLL2_CTRL_DIV_SELECT); 421 clrsetbits_le32(&anadig->pll1_ctrl, ANADIG_PLL1_CTRL_POWERDOWN, 422 ANADIG_PLL1_CTRL_ENABLE | ANADIG_PLL1_CTRL_DIV_SELECT); 423 424 clrsetbits_le32(&ccm->ccr, CCM_CCR_OSCNT_MASK, 425 CCM_CCR_FIRC_EN | CCM_CCR_OSCNT(5)); 426 clrsetbits_le32(&ccm->ccsr, CCM_REG_CTRL_MASK, 427 CCM_CCSR_PLL1_PFD_CLK_SEL(3) | CCM_CCSR_PLL2_PFD4_EN | 428 CCM_CCSR_PLL2_PFD3_EN | CCM_CCSR_PLL2_PFD2_EN | 429 CCM_CCSR_PLL2_PFD1_EN | CCM_CCSR_PLL1_PFD4_EN | 430 CCM_CCSR_PLL1_PFD3_EN | CCM_CCSR_PLL1_PFD2_EN | 431 CCM_CCSR_PLL1_PFD1_EN | CCM_CCSR_DDRC_CLK_SEL(1) | 432 CCM_CCSR_FAST_CLK_SEL(1) | CCM_CCSR_SYS_CLK_SEL(4)); 433 clrsetbits_le32(&ccm->cacrr, CCM_REG_CTRL_MASK, 434 CCM_CACRR_IPG_CLK_DIV(1) | CCM_CACRR_BUS_CLK_DIV(2) | 435 CCM_CACRR_ARM_CLK_DIV(0)); 436 clrsetbits_le32(&ccm->cscmr1, CCM_REG_CTRL_MASK, 437 CCM_CSCMR1_ESDHC1_CLK_SEL(3) | CCM_CSCMR1_QSPI0_CLK_SEL(3) | 438 CCM_CSCMR1_NFC_CLK_SEL(0)); 439 clrsetbits_le32(&ccm->cscdr1, CCM_REG_CTRL_MASK, 440 CCM_CSCDR1_RMII_CLK_EN); 441 clrsetbits_le32(&ccm->cscdr2, CCM_REG_CTRL_MASK, 442 CCM_CSCDR2_ESDHC1_EN | CCM_CSCDR2_ESDHC1_CLK_DIV(0) | 443 CCM_CSCDR2_NFC_EN); 444 clrsetbits_le32(&ccm->cscdr3, CCM_REG_CTRL_MASK, 445 CCM_CSCDR3_QSPI0_EN | CCM_CSCDR3_QSPI0_DIV(1) | 446 CCM_CSCDR3_QSPI0_X2_DIV(1) | CCM_CSCDR3_QSPI0_X4_DIV(3) | 447 CCM_CSCDR3_NFC_PRE_DIV(5)); 448 clrsetbits_le32(&ccm->cscmr2, CCM_REG_CTRL_MASK, 449 CCM_CSCMR2_RMII_CLK_SEL(0)); 450 } 451 452 static void mscm_init(void) 453 { 454 struct mscm_ir *mscmir = (struct mscm_ir *)MSCM_IR_BASE_ADDR; 455 int i; 456 457 for (i = 0; i < MSCM_IRSPRC_NUM; i++) 458 writew(MSCM_IRSPRC_CP0_EN, &mscmir->irsprc[i]); 459 } 460 461 int board_phy_config(struct phy_device *phydev) 462 { 463 if (phydev->drv->config) 464 phydev->drv->config(phydev); 465 466 return 0; 467 } 468 469 int board_early_init_f(void) 470 { 471 clock_init(); 472 mscm_init(); 473 474 setup_iomux_uart(); 475 setup_iomux_enet(); 476 setup_iomux_i2c(); 477 setup_iomux_qspi(); 478 #ifdef CONFIG_NAND_VF610_NFC 479 setup_iomux_nfc(); 480 #endif 481 482 return 0; 483 } 484 485 int board_init(void) 486 { 487 /* address of boot parameters */ 488 gd->bd->bi_boot_params = PHYS_SDRAM + 0x100; 489 490 return 0; 491 } 492 493 int checkboard(void) 494 { 495 puts("Board: vf610twr\n"); 496 497 return 0; 498 } 499