18c653124SAlison Wang /* 28c653124SAlison Wang * Copyright 2013 Freescale Semiconductor, Inc. 38c653124SAlison Wang * 41a459660SWolfgang Denk * SPDX-License-Identifier: GPL-2.0+ 58c653124SAlison Wang */ 68c653124SAlison Wang 78c653124SAlison Wang #include <common.h> 88c653124SAlison Wang #include <asm/io.h> 98c653124SAlison Wang #include <asm/arch/imx-regs.h> 108c653124SAlison Wang #include <asm/arch/iomux-vf610.h> 118c653124SAlison Wang #include <asm/arch/crm_regs.h> 128c653124SAlison Wang #include <asm/arch/clock.h> 138c653124SAlison Wang #include <mmc.h> 148c653124SAlison Wang #include <fsl_esdhc.h> 158c653124SAlison Wang #include <miiphy.h> 168c653124SAlison Wang #include <netdev.h> 171221b3d7SAlison Wang #include <i2c.h> 188c653124SAlison Wang 198c653124SAlison Wang DECLARE_GLOBAL_DATA_PTR; 208c653124SAlison Wang 218c653124SAlison Wang #define UART_PAD_CTRL (PAD_CTL_PUS_100K_UP | PAD_CTL_SPEED_MED | \ 228c653124SAlison Wang PAD_CTL_DSE_25ohm | PAD_CTL_OBE_IBE_ENABLE) 238c653124SAlison Wang 248c653124SAlison Wang #define ESDHC_PAD_CTRL (PAD_CTL_PUS_100K_UP | PAD_CTL_SPEED_HIGH | \ 258c653124SAlison Wang PAD_CTL_DSE_20ohm | PAD_CTL_OBE_IBE_ENABLE) 268c653124SAlison Wang 278c653124SAlison Wang #define ENET_PAD_CTRL (PAD_CTL_PUS_47K_UP | PAD_CTL_SPEED_HIGH | \ 288c653124SAlison Wang PAD_CTL_DSE_50ohm | PAD_CTL_OBE_IBE_ENABLE) 298c653124SAlison Wang 308c653124SAlison Wang void setup_iomux_ddr(void) 318c653124SAlison Wang { 328c653124SAlison Wang static const iomux_v3_cfg_t ddr_pads[] = { 338c653124SAlison Wang VF610_PAD_DDR_A15__DDR_A_15, 348c653124SAlison Wang VF610_PAD_DDR_A14__DDR_A_14, 358c653124SAlison Wang VF610_PAD_DDR_A13__DDR_A_13, 368c653124SAlison Wang VF610_PAD_DDR_A12__DDR_A_12, 378c653124SAlison Wang VF610_PAD_DDR_A11__DDR_A_11, 388c653124SAlison Wang VF610_PAD_DDR_A10__DDR_A_10, 398c653124SAlison Wang VF610_PAD_DDR_A9__DDR_A_9, 408c653124SAlison Wang VF610_PAD_DDR_A8__DDR_A_8, 418c653124SAlison Wang VF610_PAD_DDR_A7__DDR_A_7, 428c653124SAlison Wang VF610_PAD_DDR_A6__DDR_A_6, 438c653124SAlison Wang VF610_PAD_DDR_A5__DDR_A_5, 448c653124SAlison Wang VF610_PAD_DDR_A4__DDR_A_4, 458c653124SAlison Wang VF610_PAD_DDR_A3__DDR_A_3, 468c653124SAlison Wang VF610_PAD_DDR_A2__DDR_A_2, 478c653124SAlison Wang VF610_PAD_DDR_A1__DDR_A_1, 488c653124SAlison Wang VF610_PAD_DDR_BA2__DDR_BA_2, 498c653124SAlison Wang VF610_PAD_DDR_BA1__DDR_BA_1, 508c653124SAlison Wang VF610_PAD_DDR_BA0__DDR_BA_0, 518c653124SAlison Wang VF610_PAD_DDR_CAS__DDR_CAS_B, 528c653124SAlison Wang VF610_PAD_DDR_CKE__DDR_CKE_0, 538c653124SAlison Wang VF610_PAD_DDR_CLK__DDR_CLK_0, 548c653124SAlison Wang VF610_PAD_DDR_CS__DDR_CS_B_0, 558c653124SAlison Wang VF610_PAD_DDR_D15__DDR_D_15, 568c653124SAlison Wang VF610_PAD_DDR_D14__DDR_D_14, 578c653124SAlison Wang VF610_PAD_DDR_D13__DDR_D_13, 588c653124SAlison Wang VF610_PAD_DDR_D12__DDR_D_12, 598c653124SAlison Wang VF610_PAD_DDR_D11__DDR_D_11, 608c653124SAlison Wang VF610_PAD_DDR_D10__DDR_D_10, 618c653124SAlison Wang VF610_PAD_DDR_D9__DDR_D_9, 628c653124SAlison Wang VF610_PAD_DDR_D8__DDR_D_8, 638c653124SAlison Wang VF610_PAD_DDR_D7__DDR_D_7, 648c653124SAlison Wang VF610_PAD_DDR_D6__DDR_D_6, 658c653124SAlison Wang VF610_PAD_DDR_D5__DDR_D_5, 668c653124SAlison Wang VF610_PAD_DDR_D4__DDR_D_4, 678c653124SAlison Wang VF610_PAD_DDR_D3__DDR_D_3, 688c653124SAlison Wang VF610_PAD_DDR_D2__DDR_D_2, 698c653124SAlison Wang VF610_PAD_DDR_D1__DDR_D_1, 708c653124SAlison Wang VF610_PAD_DDR_D0__DDR_D_0, 718c653124SAlison Wang VF610_PAD_DDR_DQM1__DDR_DQM_1, 728c653124SAlison Wang VF610_PAD_DDR_DQM0__DDR_DQM_0, 738c653124SAlison Wang VF610_PAD_DDR_DQS1__DDR_DQS_1, 748c653124SAlison Wang VF610_PAD_DDR_DQS0__DDR_DQS_0, 758c653124SAlison Wang VF610_PAD_DDR_RAS__DDR_RAS_B, 768c653124SAlison Wang VF610_PAD_DDR_WE__DDR_WE_B, 778c653124SAlison Wang VF610_PAD_DDR_ODT1__DDR_ODT_0, 788c653124SAlison Wang VF610_PAD_DDR_ODT0__DDR_ODT_1, 798c653124SAlison Wang }; 808c653124SAlison Wang 818c653124SAlison Wang imx_iomux_v3_setup_multiple_pads(ddr_pads, ARRAY_SIZE(ddr_pads)); 828c653124SAlison Wang } 838c653124SAlison Wang 848c653124SAlison Wang void ddr_phy_init(void) 858c653124SAlison Wang { 868c653124SAlison Wang struct ddrmr_regs *ddrmr = (struct ddrmr_regs *)DDR_BASE_ADDR; 878c653124SAlison Wang 888c653124SAlison Wang writel(DDRMC_PHY_DQ_TIMING, &ddrmr->phy[0]); 898c653124SAlison Wang writel(DDRMC_PHY_DQ_TIMING, &ddrmr->phy[16]); 908c653124SAlison Wang writel(DDRMC_PHY_DQ_TIMING, &ddrmr->phy[32]); 918c653124SAlison Wang writel(DDRMC_PHY_DQ_TIMING, &ddrmr->phy[48]); 928c653124SAlison Wang 938c653124SAlison Wang writel(DDRMC_PHY_DQS_TIMING, &ddrmr->phy[1]); 948c653124SAlison Wang writel(DDRMC_PHY_DQS_TIMING, &ddrmr->phy[17]); 958c653124SAlison Wang writel(DDRMC_PHY_DQS_TIMING, &ddrmr->phy[33]); 968c653124SAlison Wang writel(DDRMC_PHY_DQS_TIMING, &ddrmr->phy[49]); 978c653124SAlison Wang 988c653124SAlison Wang writel(DDRMC_PHY_CTRL, &ddrmr->phy[2]); 998c653124SAlison Wang writel(DDRMC_PHY_CTRL, &ddrmr->phy[18]); 1008c653124SAlison Wang writel(DDRMC_PHY_CTRL, &ddrmr->phy[34]); 1018c653124SAlison Wang writel(DDRMC_PHY_CTRL, &ddrmr->phy[50]); 1028c653124SAlison Wang 1038c653124SAlison Wang writel(DDRMC_PHY_MASTER_CTRL, &ddrmr->phy[3]); 1048c653124SAlison Wang writel(DDRMC_PHY_MASTER_CTRL, &ddrmr->phy[19]); 1058c653124SAlison Wang writel(DDRMC_PHY_MASTER_CTRL, &ddrmr->phy[35]); 1068c653124SAlison Wang writel(DDRMC_PHY_MASTER_CTRL, &ddrmr->phy[51]); 1078c653124SAlison Wang 1088c653124SAlison Wang writel(DDRMC_PHY_SLAVE_CTRL, &ddrmr->phy[4]); 1098c653124SAlison Wang writel(DDRMC_PHY_SLAVE_CTRL, &ddrmr->phy[20]); 1108c653124SAlison Wang writel(DDRMC_PHY_SLAVE_CTRL, &ddrmr->phy[36]); 1118c653124SAlison Wang writel(DDRMC_PHY_SLAVE_CTRL, &ddrmr->phy[52]); 1128c653124SAlison Wang 1138c653124SAlison Wang writel(DDRMC_PHY50_DDR3_MODE | DDRMC_PHY50_EN_SW_HALF_CYCLE, 1148c653124SAlison Wang &ddrmr->phy[50]); 1158c653124SAlison Wang } 1168c653124SAlison Wang 1178c653124SAlison Wang void ddr_ctrl_init(void) 1188c653124SAlison Wang { 1198c653124SAlison Wang struct ddrmr_regs *ddrmr = (struct ddrmr_regs *)DDR_BASE_ADDR; 1208c653124SAlison Wang 1218c653124SAlison Wang writel(DDRMC_CR00_DRAM_CLASS_DDR3, &ddrmr->cr[0]); 1228c653124SAlison Wang writel(DDRMC_CR02_DRAM_TINIT(32), &ddrmr->cr[2]); 1238c653124SAlison Wang writel(DDRMC_CR10_TRST_PWRON(124), &ddrmr->cr[10]); 1248c653124SAlison Wang 1258c653124SAlison Wang writel(DDRMC_CR11_CKE_INACTIVE(80000), &ddrmr->cr[11]); 1268c653124SAlison Wang writel(DDRMC_CR12_WRLAT(5) | DDRMC_CR12_CASLAT_LIN(12), &ddrmr->cr[12]); 1278c653124SAlison Wang writel(DDRMC_CR13_TRC(21) | DDRMC_CR13_TRRD(4) | DDRMC_CR13_TCCD(4) | 1288c653124SAlison Wang DDRMC_CR13_TBST_INT_INTERVAL(4), &ddrmr->cr[13]); 1298c653124SAlison Wang writel(DDRMC_CR14_TFAW(20) | DDRMC_CR14_TRP(6) | DDRMC_CR14_TWTR(4) | 1308c653124SAlison Wang DDRMC_CR14_TRAS_MIN(15), &ddrmr->cr[14]); 1318c653124SAlison Wang writel(DDRMC_CR16_TMRD(4) | DDRMC_CR16_TRTP(4), &ddrmr->cr[16]); 1328c653124SAlison Wang writel(DDRMC_CR17_TRAS_MAX(28080) | DDRMC_CR17_TMOD(12), 1338c653124SAlison Wang &ddrmr->cr[17]); 1348c653124SAlison Wang writel(DDRMC_CR18_TCKESR(4) | DDRMC_CR18_TCKE(3), &ddrmr->cr[18]); 1358c653124SAlison Wang 1368c653124SAlison Wang writel(DDRMC_CR20_AP_EN, &ddrmr->cr[20]); 1378c653124SAlison Wang writel(DDRMC_CR21_TRCD_INT(6) | DDRMC_CR21_TRAS_LOCKOUT | 1388c653124SAlison Wang DDRMC_CR21_CCMAP_EN, &ddrmr->cr[21]); 1398c653124SAlison Wang 1408c653124SAlison Wang writel(DDRMC_CR22_TDAL(11), &ddrmr->cr[22]); 1418c653124SAlison Wang writel(DDRMC_CR23_BSTLEN(3) | DDRMC_CR23_TDLL(512), &ddrmr->cr[23]); 1428c653124SAlison Wang writel(DDRMC_CR24_TRP_AB(6), &ddrmr->cr[24]); 1438c653124SAlison Wang 1448c653124SAlison Wang writel(DDRMC_CR25_TREF_EN, &ddrmr->cr[25]); 1458c653124SAlison Wang writel(DDRMC_CR26_TREF(3112) | DDRMC_CR26_TRFC(44), &ddrmr->cr[26]); 1468c653124SAlison Wang writel(DDRMC_CR28_TREF_INT(5), &ddrmr->cr[28]); 1478c653124SAlison Wang writel(DDRMC_CR29_TPDEX(3), &ddrmr->cr[29]); 1488c653124SAlison Wang 1498c653124SAlison Wang writel(DDRMC_CR30_TXPDLL(10), &ddrmr->cr[30]); 1508c653124SAlison Wang writel(DDRMC_CR31_TXSNR(68) | DDRMC_CR31_TXSR(512), &ddrmr->cr[31]); 1518c653124SAlison Wang writel(DDRMC_CR33_EN_QK_SREF, &ddrmr->cr[33]); 1528c653124SAlison Wang writel(DDRMC_CR34_CKSRX(5) | DDRMC_CR34_CKSRE(5), &ddrmr->cr[34]); 1538c653124SAlison Wang 1548c653124SAlison Wang writel(DDRMC_CR38_FREQ_CHG_EN, &ddrmr->cr[38]); 1558c653124SAlison Wang writel(DDRMC_CR39_PHY_INI_COM(1024) | DDRMC_CR39_PHY_INI_STA(16) | 1568c653124SAlison Wang DDRMC_CR39_FRQ_CH_DLLOFF(2), &ddrmr->cr[39]); 1578c653124SAlison Wang 1588c653124SAlison Wang writel(DDRMC_CR41_PHY_INI_STRT_INI_DIS, &ddrmr->cr[41]); 1598c653124SAlison Wang writel(DDRMC_CR48_MR1_DA_0(70) | DDRMC_CR48_MR0_DA_0(1056), 1608c653124SAlison Wang &ddrmr->cr[48]); 1618c653124SAlison Wang 1628c653124SAlison Wang writel(DDRMC_CR66_ZQCL(256) | DDRMC_CR66_ZQINIT(512), &ddrmr->cr[66]); 1638c653124SAlison Wang writel(DDRMC_CR67_ZQCS(64), &ddrmr->cr[67]); 1648c653124SAlison Wang writel(DDRMC_CR69_ZQ_ON_SREF_EX(2), &ddrmr->cr[69]); 1658c653124SAlison Wang 1668c653124SAlison Wang writel(DDRMC_CR70_REF_PER_ZQ(64), &ddrmr->cr[70]); 1678c653124SAlison Wang writel(DDRMC_CR72_ZQCS_ROTATE, &ddrmr->cr[72]); 1688c653124SAlison Wang 1698c653124SAlison Wang writel(DDRMC_CR73_APREBIT(10) | DDRMC_CR73_COL_DIFF(1) | 1708c653124SAlison Wang DDRMC_CR73_ROW_DIFF(3), &ddrmr->cr[73]); 1718c653124SAlison Wang writel(DDRMC_CR74_BANKSPLT_EN | DDRMC_CR74_ADDR_CMP_EN | 1728c653124SAlison Wang DDRMC_CR74_CMD_AGE_CNT(255) | DDRMC_CR74_AGE_CNT(255), 1738c653124SAlison Wang &ddrmr->cr[74]); 1748c653124SAlison Wang writel(DDRMC_CR75_RW_PG_EN | DDRMC_CR75_RW_EN | DDRMC_CR75_PRI_EN | 1758c653124SAlison Wang DDRMC_CR75_PLEN, &ddrmr->cr[75]); 1768c653124SAlison Wang writel(DDRMC_CR76_NQENT_ACTDIS(3) | DDRMC_CR76_D_RW_G_BKCN(3) | 1778c653124SAlison Wang DDRMC_CR76_W2R_SPLT_EN | DDRMC_CR76_CS_EN, &ddrmr->cr[76]); 1788c653124SAlison Wang writel(DDRMC_CR77_CS_MAP | DDRMC_CR77_DI_RD_INTLEAVE | 1798c653124SAlison Wang DDRMC_CR77_SWAP_EN, &ddrmr->cr[77]); 1808c653124SAlison Wang writel(DDRMC_CR78_BUR_ON_FLY_BIT(12), &ddrmr->cr[78]); 1818c653124SAlison Wang writel(DDRMC_CR79_CTLUPD_AREF, &ddrmr->cr[79]); 1828c653124SAlison Wang 1838c653124SAlison Wang writel(DDRMC_CR82_INT_MASK, &ddrmr->cr[82]); 1848c653124SAlison Wang 1858c653124SAlison Wang writel(DDRMC_CR87_ODT_WR_MAPCS0 | DDRMC_CR87_ODT_RD_MAPCS0, 1868c653124SAlison Wang &ddrmr->cr[87]); 1878c653124SAlison Wang writel(DDRMC_CR88_TODTL_CMD(4), &ddrmr->cr[88]); 1888c653124SAlison Wang writel(DDRMC_CR89_AODT_RWSMCS(2), &ddrmr->cr[89]); 1898c653124SAlison Wang 1908c653124SAlison Wang writel(DDRMC_CR91_R2W_SMCSDL(2), &ddrmr->cr[91]); 1918c653124SAlison Wang writel(DDRMC_CR96_WLMRD(40) | DDRMC_CR96_WLDQSEN(25), &ddrmr->cr[96]); 1928c653124SAlison Wang 1938c653124SAlison Wang writel(DDRMC_CR105_RDLVL_DL_0(32), &ddrmr->cr[105]); 1948c653124SAlison Wang writel(DDRMC_CR110_RDLVL_DL_1(32), &ddrmr->cr[110]); 1958c653124SAlison Wang writel(DDRMC_CR114_RDLVL_GTDL_2(8224), &ddrmr->cr[114]); 1968c653124SAlison Wang 1978c653124SAlison Wang writel(DDRMC_CR117_AXI0_W_PRI(1) | DDRMC_CR117_AXI0_R_PRI(1), 1988c653124SAlison Wang &ddrmr->cr[117]); 1998c653124SAlison Wang writel(DDRMC_CR118_AXI1_W_PRI(1) | DDRMC_CR118_AXI1_R_PRI(1), 2008c653124SAlison Wang &ddrmr->cr[118]); 2018c653124SAlison Wang 2028c653124SAlison Wang writel(DDRMC_CR120_AXI0_PRI1_RPRI(2) | DDRMC_CR120_AXI0_PRI0_RPRI(2), 2038c653124SAlison Wang &ddrmr->cr[120]); 2048c653124SAlison Wang writel(DDRMC_CR121_AXI0_PRI3_RPRI(2) | DDRMC_CR121_AXI0_PRI2_RPRI(2), 2058c653124SAlison Wang &ddrmr->cr[121]); 2068c653124SAlison Wang writel(DDRMC_CR122_AXI1_PRI1_RPRI(1) | DDRMC_CR122_AXI1_PRI0_RPRI(1) | 2078c653124SAlison Wang DDRMC_CR122_AXI0_PRIRLX(100), &ddrmr->cr[122]); 2088c653124SAlison Wang writel(DDRMC_CR123_AXI1_PRI3_RPRI(1) | DDRMC_CR123_AXI1_PRI2_RPRI(1), 2098c653124SAlison Wang &ddrmr->cr[123]); 2108c653124SAlison Wang writel(DDRMC_CR124_AXI1_PRIRLX(100), &ddrmr->cr[124]); 2118c653124SAlison Wang 2128c653124SAlison Wang writel(DDRMC_CR126_PHY_RDLAT(11), &ddrmr->cr[126]); 2138c653124SAlison Wang writel(DDRMC_CR132_WRLAT_ADJ(5) | DDRMC_CR132_RDLAT_ADJ(6), 2148c653124SAlison Wang &ddrmr->cr[132]); 2158c653124SAlison Wang writel(DDRMC_CR139_PHY_WRLV_RESPLAT(4) | DDRMC_CR139_PHY_WRLV_LOAD(7) | 2168c653124SAlison Wang DDRMC_CR139_PHY_WRLV_DLL(3) | DDRMC_CR139_PHY_WRLV_EN(3), 2178c653124SAlison Wang &ddrmr->cr[139]); 2188c653124SAlison Wang 2198c653124SAlison Wang writel(DDRMC_CR154_PAD_ZQ_EARLY_CMP_EN_TIMER(13) | 22056d83d1cSStefan Agner DDRMC_CR154_PAD_ZQ_MODE(1) | 22156d83d1cSStefan Agner DDRMC_CR154_DDR_SEL_PAD_CONTR(3), &ddrmr->cr[154]); 2228c653124SAlison Wang writel(DDRMC_CR155_AXI0_AWCACHE | DDRMC_CR155_PAD_ODT_BYTE1(2), 2238c653124SAlison Wang &ddrmr->cr[155]); 2248c653124SAlison Wang writel(DDRMC_CR158_TWR(6), &ddrmr->cr[158]); 2258c653124SAlison Wang 2268c653124SAlison Wang ddr_phy_init(); 2278c653124SAlison Wang 2288c653124SAlison Wang writel(DDRMC_CR00_DRAM_CLASS_DDR3 | DDRMC_CR00_START, &ddrmr->cr[0]); 2298c653124SAlison Wang 2308c653124SAlison Wang udelay(200); 2318c653124SAlison Wang } 2328c653124SAlison Wang 2338c653124SAlison Wang int dram_init(void) 2348c653124SAlison Wang { 2358c653124SAlison Wang setup_iomux_ddr(); 2368c653124SAlison Wang 2378c653124SAlison Wang ddr_ctrl_init(); 2388c653124SAlison Wang gd->ram_size = get_ram_size((void *)PHYS_SDRAM, PHYS_SDRAM_SIZE); 2398c653124SAlison Wang 2408c653124SAlison Wang return 0; 2418c653124SAlison Wang } 2428c653124SAlison Wang 2438c653124SAlison Wang static void setup_iomux_uart(void) 2448c653124SAlison Wang { 2458c653124SAlison Wang static const iomux_v3_cfg_t uart1_pads[] = { 2468c653124SAlison Wang NEW_PAD_CTRL(VF610_PAD_PTB4__UART1_TX, UART_PAD_CTRL), 2478c653124SAlison Wang NEW_PAD_CTRL(VF610_PAD_PTB5__UART1_RX, UART_PAD_CTRL), 2488c653124SAlison Wang }; 2498c653124SAlison Wang 2508c653124SAlison Wang imx_iomux_v3_setup_multiple_pads(uart1_pads, ARRAY_SIZE(uart1_pads)); 2518c653124SAlison Wang } 2528c653124SAlison Wang 2538c653124SAlison Wang static void setup_iomux_enet(void) 2548c653124SAlison Wang { 2558c653124SAlison Wang static const iomux_v3_cfg_t enet0_pads[] = { 2568c653124SAlison Wang NEW_PAD_CTRL(VF610_PAD_PTA6__RMII0_CLKIN, ENET_PAD_CTRL), 2578c653124SAlison Wang NEW_PAD_CTRL(VF610_PAD_PTC1__RMII0_MDIO, ENET_PAD_CTRL), 2588c653124SAlison Wang NEW_PAD_CTRL(VF610_PAD_PTC0__RMII0_MDC, ENET_PAD_CTRL), 2598c653124SAlison Wang NEW_PAD_CTRL(VF610_PAD_PTC2__RMII0_CRS_DV, ENET_PAD_CTRL), 2608c653124SAlison Wang NEW_PAD_CTRL(VF610_PAD_PTC3__RMII0_RD1, ENET_PAD_CTRL), 2618c653124SAlison Wang NEW_PAD_CTRL(VF610_PAD_PTC4__RMII0_RD0, ENET_PAD_CTRL), 2628c653124SAlison Wang NEW_PAD_CTRL(VF610_PAD_PTC5__RMII0_RXER, ENET_PAD_CTRL), 2638c653124SAlison Wang NEW_PAD_CTRL(VF610_PAD_PTC6__RMII0_TD1, ENET_PAD_CTRL), 2648c653124SAlison Wang NEW_PAD_CTRL(VF610_PAD_PTC7__RMII0_TD0, ENET_PAD_CTRL), 2658c653124SAlison Wang NEW_PAD_CTRL(VF610_PAD_PTC8__RMII0_TXEN, ENET_PAD_CTRL), 2668c653124SAlison Wang }; 2678c653124SAlison Wang 2688c653124SAlison Wang imx_iomux_v3_setup_multiple_pads(enet0_pads, ARRAY_SIZE(enet0_pads)); 2698c653124SAlison Wang } 2708c653124SAlison Wang 2711221b3d7SAlison Wang static void setup_iomux_i2c(void) 2721221b3d7SAlison Wang { 2731221b3d7SAlison Wang static const iomux_v3_cfg_t i2c0_pads[] = { 2741221b3d7SAlison Wang VF610_PAD_PTB14__I2C0_SCL, 2751221b3d7SAlison Wang VF610_PAD_PTB15__I2C0_SDA, 2761221b3d7SAlison Wang }; 2771221b3d7SAlison Wang 2781221b3d7SAlison Wang imx_iomux_v3_setup_multiple_pads(i2c0_pads, ARRAY_SIZE(i2c0_pads)); 2791221b3d7SAlison Wang } 2801221b3d7SAlison Wang 281*cb6d04d6SChao Fu static void setup_iomux_qspi(void) 282*cb6d04d6SChao Fu { 283*cb6d04d6SChao Fu static const iomux_v3_cfg_t qspi0_pads[] = { 284*cb6d04d6SChao Fu VF610_PAD_PTD0__QSPI0_A_QSCK, 285*cb6d04d6SChao Fu VF610_PAD_PTD1__QSPI0_A_CS0, 286*cb6d04d6SChao Fu VF610_PAD_PTD2__QSPI0_A_DATA3, 287*cb6d04d6SChao Fu VF610_PAD_PTD3__QSPI0_A_DATA2, 288*cb6d04d6SChao Fu VF610_PAD_PTD4__QSPI0_A_DATA1, 289*cb6d04d6SChao Fu VF610_PAD_PTD5__QSPI0_A_DATA0, 290*cb6d04d6SChao Fu VF610_PAD_PTD7__QSPI0_B_QSCK, 291*cb6d04d6SChao Fu VF610_PAD_PTD8__QSPI0_B_CS0, 292*cb6d04d6SChao Fu VF610_PAD_PTD9__QSPI0_B_DATA3, 293*cb6d04d6SChao Fu VF610_PAD_PTD10__QSPI0_B_DATA2, 294*cb6d04d6SChao Fu VF610_PAD_PTD11__QSPI0_B_DATA1, 295*cb6d04d6SChao Fu VF610_PAD_PTD12__QSPI0_B_DATA0, 296*cb6d04d6SChao Fu }; 297*cb6d04d6SChao Fu 298*cb6d04d6SChao Fu imx_iomux_v3_setup_multiple_pads(qspi0_pads, ARRAY_SIZE(qspi0_pads)); 299*cb6d04d6SChao Fu } 300*cb6d04d6SChao Fu 3018c653124SAlison Wang #ifdef CONFIG_FSL_ESDHC 3028c653124SAlison Wang struct fsl_esdhc_cfg esdhc_cfg[1] = { 3038c653124SAlison Wang {ESDHC1_BASE_ADDR}, 3048c653124SAlison Wang }; 3058c653124SAlison Wang 3068c653124SAlison Wang int board_mmc_getcd(struct mmc *mmc) 3078c653124SAlison Wang { 3088c653124SAlison Wang /* eSDHC1 is always present */ 3098c653124SAlison Wang return 1; 3108c653124SAlison Wang } 3118c653124SAlison Wang 3128c653124SAlison Wang int board_mmc_init(bd_t *bis) 3138c653124SAlison Wang { 3148c653124SAlison Wang static const iomux_v3_cfg_t esdhc1_pads[] = { 3158c653124SAlison Wang NEW_PAD_CTRL(VF610_PAD_PTA24__ESDHC1_CLK, ESDHC_PAD_CTRL), 3168c653124SAlison Wang NEW_PAD_CTRL(VF610_PAD_PTA25__ESDHC1_CMD, ESDHC_PAD_CTRL), 3178c653124SAlison Wang NEW_PAD_CTRL(VF610_PAD_PTA26__ESDHC1_DAT0, ESDHC_PAD_CTRL), 3188c653124SAlison Wang NEW_PAD_CTRL(VF610_PAD_PTA27__ESDHC1_DAT1, ESDHC_PAD_CTRL), 3198c653124SAlison Wang NEW_PAD_CTRL(VF610_PAD_PTA28__ESDHC1_DAT2, ESDHC_PAD_CTRL), 3208c653124SAlison Wang NEW_PAD_CTRL(VF610_PAD_PTA29__ESDHC1_DAT3, ESDHC_PAD_CTRL), 3218c653124SAlison Wang }; 3228c653124SAlison Wang 3238c653124SAlison Wang esdhc_cfg[0].sdhc_clk = mxc_get_clock(MXC_ESDHC_CLK); 3248c653124SAlison Wang 3258c653124SAlison Wang imx_iomux_v3_setup_multiple_pads( 3268c653124SAlison Wang esdhc1_pads, ARRAY_SIZE(esdhc1_pads)); 3278c653124SAlison Wang 3284a1c7b13SFabio Estevam return fsl_esdhc_initialize(bis, &esdhc_cfg[0]); 3298c653124SAlison Wang } 3308c653124SAlison Wang #endif 3318c653124SAlison Wang 3328c653124SAlison Wang static void clock_init(void) 3338c653124SAlison Wang { 3348c653124SAlison Wang struct ccm_reg *ccm = (struct ccm_reg *)CCM_BASE_ADDR; 3358c653124SAlison Wang struct anadig_reg *anadig = (struct anadig_reg *)ANADIG_BASE_ADDR; 3368c653124SAlison Wang 3378c653124SAlison Wang clrsetbits_le32(&ccm->ccgr0, CCM_REG_CTRL_MASK, 3388c653124SAlison Wang CCM_CCGR0_UART1_CTRL_MASK); 3398c653124SAlison Wang clrsetbits_le32(&ccm->ccgr1, CCM_REG_CTRL_MASK, 3408c653124SAlison Wang CCM_CCGR1_PIT_CTRL_MASK | CCM_CCGR1_WDOGA5_CTRL_MASK); 3418c653124SAlison Wang clrsetbits_le32(&ccm->ccgr2, CCM_REG_CTRL_MASK, 3428c653124SAlison Wang CCM_CCGR2_IOMUXC_CTRL_MASK | CCM_CCGR2_PORTA_CTRL_MASK | 3438c653124SAlison Wang CCM_CCGR2_PORTB_CTRL_MASK | CCM_CCGR2_PORTC_CTRL_MASK | 344*cb6d04d6SChao Fu CCM_CCGR2_PORTD_CTRL_MASK | CCM_CCGR2_PORTE_CTRL_MASK | 345*cb6d04d6SChao Fu CCM_CCGR2_QSPI0_CTRL_MASK); 3468c653124SAlison Wang clrsetbits_le32(&ccm->ccgr3, CCM_REG_CTRL_MASK, 3478c653124SAlison Wang CCM_CCGR3_ANADIG_CTRL_MASK); 3488c653124SAlison Wang clrsetbits_le32(&ccm->ccgr4, CCM_REG_CTRL_MASK, 3498c653124SAlison Wang CCM_CCGR4_WKUP_CTRL_MASK | CCM_CCGR4_CCM_CTRL_MASK | 3501221b3d7SAlison Wang CCM_CCGR4_GPC_CTRL_MASK | CCM_CCGR4_I2C0_CTRL_MASK); 3518c653124SAlison Wang clrsetbits_le32(&ccm->ccgr6, CCM_REG_CTRL_MASK, 3528c653124SAlison Wang CCM_CCGR6_OCOTP_CTRL_MASK | CCM_CCGR6_DDRMC_CTRL_MASK); 3538c653124SAlison Wang clrsetbits_le32(&ccm->ccgr7, CCM_REG_CTRL_MASK, 3548c653124SAlison Wang CCM_CCGR7_SDHC1_CTRL_MASK); 3558c653124SAlison Wang clrsetbits_le32(&ccm->ccgr9, CCM_REG_CTRL_MASK, 3568c653124SAlison Wang CCM_CCGR9_FEC0_CTRL_MASK | CCM_CCGR9_FEC1_CTRL_MASK); 3578c653124SAlison Wang 3588c653124SAlison Wang clrsetbits_le32(&anadig->pll2_ctrl, ANADIG_PLL2_CTRL_POWERDOWN, 3598c653124SAlison Wang ANADIG_PLL2_CTRL_ENABLE | ANADIG_PLL2_CTRL_DIV_SELECT); 3608c653124SAlison Wang clrsetbits_le32(&anadig->pll1_ctrl, ANADIG_PLL1_CTRL_POWERDOWN, 3618c653124SAlison Wang ANADIG_PLL1_CTRL_ENABLE | ANADIG_PLL1_CTRL_DIV_SELECT); 3628c653124SAlison Wang 3638c653124SAlison Wang clrsetbits_le32(&ccm->ccr, CCM_CCR_OSCNT_MASK, 3648c653124SAlison Wang CCM_CCR_FIRC_EN | CCM_CCR_OSCNT(5)); 3658c653124SAlison Wang clrsetbits_le32(&ccm->ccsr, CCM_REG_CTRL_MASK, 3668c653124SAlison Wang CCM_CCSR_PLL1_PFD_CLK_SEL(3) | CCM_CCSR_PLL2_PFD4_EN | 3678c653124SAlison Wang CCM_CCSR_PLL2_PFD3_EN | CCM_CCSR_PLL2_PFD2_EN | 3688c653124SAlison Wang CCM_CCSR_PLL2_PFD1_EN | CCM_CCSR_PLL1_PFD4_EN | 3698c653124SAlison Wang CCM_CCSR_PLL1_PFD3_EN | CCM_CCSR_PLL1_PFD2_EN | 3708c653124SAlison Wang CCM_CCSR_PLL1_PFD1_EN | CCM_CCSR_DDRC_CLK_SEL(1) | 3718c653124SAlison Wang CCM_CCSR_FAST_CLK_SEL(1) | CCM_CCSR_SYS_CLK_SEL(4)); 3728c653124SAlison Wang clrsetbits_le32(&ccm->cacrr, CCM_REG_CTRL_MASK, 3738c653124SAlison Wang CCM_CACRR_IPG_CLK_DIV(1) | CCM_CACRR_BUS_CLK_DIV(2) | 3748c653124SAlison Wang CCM_CACRR_ARM_CLK_DIV(0)); 3758c653124SAlison Wang clrsetbits_le32(&ccm->cscmr1, CCM_REG_CTRL_MASK, 376*cb6d04d6SChao Fu CCM_CSCMR1_ESDHC1_CLK_SEL(3) | CCM_CSCMR1_QSPI0_CLK_SEL(3)); 3778c653124SAlison Wang clrsetbits_le32(&ccm->cscdr1, CCM_REG_CTRL_MASK, 3788c653124SAlison Wang CCM_CSCDR1_RMII_CLK_EN); 3798c653124SAlison Wang clrsetbits_le32(&ccm->cscdr2, CCM_REG_CTRL_MASK, 3808c653124SAlison Wang CCM_CSCDR2_ESDHC1_EN | CCM_CSCDR2_ESDHC1_CLK_DIV(0)); 381*cb6d04d6SChao Fu clrsetbits_le32(&ccm->cscdr3, CCM_REG_CTRL_MASK, 382*cb6d04d6SChao Fu CCM_CSCDR3_QSPI0_EN | CCM_CSCDR3_QSPI0_DIV(1) | 383*cb6d04d6SChao Fu CCM_CSCDR3_QSPI0_X2_DIV(1) | CCM_CSCDR3_QSPI0_X4_DIV(3)); 3848c653124SAlison Wang clrsetbits_le32(&ccm->cscmr2, CCM_REG_CTRL_MASK, 3858c653124SAlison Wang CCM_CSCMR2_RMII_CLK_SEL(0)); 3868c653124SAlison Wang } 3878c653124SAlison Wang 3888c653124SAlison Wang static void mscm_init(void) 3898c653124SAlison Wang { 3908c653124SAlison Wang struct mscm_ir *mscmir = (struct mscm_ir *)MSCM_IR_BASE_ADDR; 3918c653124SAlison Wang int i; 3928c653124SAlison Wang 3938c653124SAlison Wang for (i = 0; i < MSCM_IRSPRC_NUM; i++) 3948c653124SAlison Wang writew(MSCM_IRSPRC_CP0_EN, &mscmir->irsprc[i]); 3958c653124SAlison Wang } 3968c653124SAlison Wang 3978c653124SAlison Wang int board_phy_config(struct phy_device *phydev) 3988c653124SAlison Wang { 3998c653124SAlison Wang if (phydev->drv->config) 4008c653124SAlison Wang phydev->drv->config(phydev); 4018c653124SAlison Wang 4028c653124SAlison Wang return 0; 4038c653124SAlison Wang } 4048c653124SAlison Wang 4058c653124SAlison Wang int board_early_init_f(void) 4068c653124SAlison Wang { 4078c653124SAlison Wang clock_init(); 4088c653124SAlison Wang mscm_init(); 4098c653124SAlison Wang 4108c653124SAlison Wang setup_iomux_uart(); 4118c653124SAlison Wang setup_iomux_enet(); 4121221b3d7SAlison Wang setup_iomux_i2c(); 413*cb6d04d6SChao Fu setup_iomux_qspi(); 4148c653124SAlison Wang 4158c653124SAlison Wang return 0; 4168c653124SAlison Wang } 4178c653124SAlison Wang 4188c653124SAlison Wang int board_init(void) 4198c653124SAlison Wang { 4208c653124SAlison Wang /* address of boot parameters */ 4218c653124SAlison Wang gd->bd->bi_boot_params = PHYS_SDRAM + 0x100; 4228c653124SAlison Wang 4238c653124SAlison Wang return 0; 4248c653124SAlison Wang } 4258c653124SAlison Wang 4268c653124SAlison Wang int checkboard(void) 4278c653124SAlison Wang { 4288c653124SAlison Wang puts("Board: vf610twr\n"); 4298c653124SAlison Wang 4308c653124SAlison Wang return 0; 4318c653124SAlison Wang } 432