18c653124SAlison Wang /* 28c653124SAlison Wang * Copyright 2013 Freescale Semiconductor, Inc. 38c653124SAlison Wang * 41a459660SWolfgang Denk * SPDX-License-Identifier: GPL-2.0+ 58c653124SAlison Wang */ 68c653124SAlison Wang 78c653124SAlison Wang #include <common.h> 88c653124SAlison Wang #include <asm/io.h> 98c653124SAlison Wang #include <asm/arch/imx-regs.h> 108c653124SAlison Wang #include <asm/arch/iomux-vf610.h> 11c7ea243cSSanchayan Maity #include <asm/arch/ddrmc-vf610.h> 128c653124SAlison Wang #include <asm/arch/crm_regs.h> 138c653124SAlison Wang #include <asm/arch/clock.h> 148c653124SAlison Wang #include <mmc.h> 158c653124SAlison Wang #include <fsl_esdhc.h> 168c653124SAlison Wang #include <miiphy.h> 178c653124SAlison Wang #include <netdev.h> 181221b3d7SAlison Wang #include <i2c.h> 198c653124SAlison Wang 208c653124SAlison Wang DECLARE_GLOBAL_DATA_PTR; 218c653124SAlison Wang 228c653124SAlison Wang #define UART_PAD_CTRL (PAD_CTL_PUS_100K_UP | PAD_CTL_SPEED_MED | \ 238c653124SAlison Wang PAD_CTL_DSE_25ohm | PAD_CTL_OBE_IBE_ENABLE) 248c653124SAlison Wang 258c653124SAlison Wang #define ESDHC_PAD_CTRL (PAD_CTL_PUS_100K_UP | PAD_CTL_SPEED_HIGH | \ 268c653124SAlison Wang PAD_CTL_DSE_20ohm | PAD_CTL_OBE_IBE_ENABLE) 278c653124SAlison Wang 288c653124SAlison Wang #define ENET_PAD_CTRL (PAD_CTL_PUS_47K_UP | PAD_CTL_SPEED_HIGH | \ 298c653124SAlison Wang PAD_CTL_DSE_50ohm | PAD_CTL_OBE_IBE_ENABLE) 308c653124SAlison Wang 313f353cecSAlbert ARIBAUD \\(3ADEV\\) static struct ddrmc_cr_setting vf610twr_cr_settings[] = { 323f353cecSAlbert ARIBAUD \\(3ADEV\\) /* levelling */ 333f353cecSAlbert ARIBAUD \\(3ADEV\\) { DDRMC_CR97_WRLVL_EN, 97 }, 343f353cecSAlbert ARIBAUD \\(3ADEV\\) { DDRMC_CR98_WRLVL_DL_0(0), 98 }, 353f353cecSAlbert ARIBAUD \\(3ADEV\\) { DDRMC_CR99_WRLVL_DL_1(0), 99 }, 363f353cecSAlbert ARIBAUD \\(3ADEV\\) { DDRMC_CR102_RDLVL_REG_EN | DDRMC_CR102_RDLVL_GT_REGEN, 102 }, 373f353cecSAlbert ARIBAUD \\(3ADEV\\) { DDRMC_CR105_RDLVL_DL_0(0), 105 }, 383f353cecSAlbert ARIBAUD \\(3ADEV\\) { DDRMC_CR106_RDLVL_GTDL_0(4), 106 }, 393f353cecSAlbert ARIBAUD \\(3ADEV\\) { DDRMC_CR110_RDLVL_DL_1(0) | DDRMC_CR110_RDLVL_GTDL_1(4), 110 }, 403f353cecSAlbert ARIBAUD \\(3ADEV\\) /* AXI */ 413f353cecSAlbert ARIBAUD \\(3ADEV\\) { DDRMC_CR117_AXI0_W_PRI(0) | DDRMC_CR117_AXI0_R_PRI(0), 117 }, 423f353cecSAlbert ARIBAUD \\(3ADEV\\) { DDRMC_CR118_AXI1_W_PRI(1) | DDRMC_CR118_AXI1_R_PRI(1), 118 }, 433f353cecSAlbert ARIBAUD \\(3ADEV\\) { DDRMC_CR120_AXI0_PRI1_RPRI(2) | 443f353cecSAlbert ARIBAUD \\(3ADEV\\) DDRMC_CR120_AXI0_PRI0_RPRI(2), 120 }, 453f353cecSAlbert ARIBAUD \\(3ADEV\\) { DDRMC_CR121_AXI0_PRI3_RPRI(2) | 463f353cecSAlbert ARIBAUD \\(3ADEV\\) DDRMC_CR121_AXI0_PRI2_RPRI(2), 121 }, 473f353cecSAlbert ARIBAUD \\(3ADEV\\) { DDRMC_CR122_AXI1_PRI1_RPRI(1) | DDRMC_CR122_AXI1_PRI0_RPRI(1) | 483f353cecSAlbert ARIBAUD \\(3ADEV\\) DDRMC_CR122_AXI0_PRIRLX(100), 122 }, 493f353cecSAlbert ARIBAUD \\(3ADEV\\) { DDRMC_CR123_AXI1_P_ODR_EN | DDRMC_CR123_AXI1_PRI3_RPRI(1) | 503f353cecSAlbert ARIBAUD \\(3ADEV\\) DDRMC_CR123_AXI1_PRI2_RPRI(1), 123 }, 513f353cecSAlbert ARIBAUD \\(3ADEV\\) { DDRMC_CR124_AXI1_PRIRLX(100), 124 }, 523f353cecSAlbert ARIBAUD \\(3ADEV\\) { DDRMC_CR126_PHY_RDLAT(8), 126 }, 533f353cecSAlbert ARIBAUD \\(3ADEV\\) { DDRMC_CR132_WRLAT_ADJ(5) | 543f353cecSAlbert ARIBAUD \\(3ADEV\\) DDRMC_CR132_RDLAT_ADJ(6), 132 }, 553f353cecSAlbert ARIBAUD \\(3ADEV\\) { DDRMC_CR137_PHYCTL_DL(2), 137 }, 563f353cecSAlbert ARIBAUD \\(3ADEV\\) { DDRMC_CR138_PHY_WRLV_MXDL(256) | 573f353cecSAlbert ARIBAUD \\(3ADEV\\) DDRMC_CR138_PHYDRAM_CK_EN(1), 138 }, 583f353cecSAlbert ARIBAUD \\(3ADEV\\) { DDRMC_CR139_PHY_WRLV_RESPLAT(4) | DDRMC_CR139_PHY_WRLV_LOAD(7) | 593f353cecSAlbert ARIBAUD \\(3ADEV\\) DDRMC_CR139_PHY_WRLV_DLL(3) | 603f353cecSAlbert ARIBAUD \\(3ADEV\\) DDRMC_CR139_PHY_WRLV_EN(3), 139 }, 613f353cecSAlbert ARIBAUD \\(3ADEV\\) { DDRMC_CR140_PHY_WRLV_WW(64), 140 }, 623f353cecSAlbert ARIBAUD \\(3ADEV\\) { DDRMC_CR143_RDLV_GAT_MXDL(1536) | 633f353cecSAlbert ARIBAUD \\(3ADEV\\) DDRMC_CR143_RDLV_MXDL(128), 143 }, 643f353cecSAlbert ARIBAUD \\(3ADEV\\) { DDRMC_CR144_PHY_RDLVL_RES(4) | DDRMC_CR144_PHY_RDLV_LOAD(7) | 653f353cecSAlbert ARIBAUD \\(3ADEV\\) DDRMC_CR144_PHY_RDLV_DLL(3) | 663f353cecSAlbert ARIBAUD \\(3ADEV\\) DDRMC_CR144_PHY_RDLV_EN(3), 144 }, 673f353cecSAlbert ARIBAUD \\(3ADEV\\) { DDRMC_CR145_PHY_RDLV_RR(64), 145 }, 683f353cecSAlbert ARIBAUD \\(3ADEV\\) { DDRMC_CR146_PHY_RDLVL_RESP(64), 146 }, 693f353cecSAlbert ARIBAUD \\(3ADEV\\) { DDRMC_CR147_RDLV_RESP_MASK(983040), 147 }, 703f353cecSAlbert ARIBAUD \\(3ADEV\\) { DDRMC_CR148_RDLV_GATE_RESP_MASK(983040), 148 }, 713f353cecSAlbert ARIBAUD \\(3ADEV\\) { DDRMC_CR151_RDLV_GAT_DQ_ZERO_CNT(1) | 723f353cecSAlbert ARIBAUD \\(3ADEV\\) DDRMC_CR151_RDLVL_DQ_ZERO_CNT(1), 151 }, 733f353cecSAlbert ARIBAUD \\(3ADEV\\) 743f353cecSAlbert ARIBAUD \\(3ADEV\\) { DDRMC_CR154_PAD_ZQ_EARLY_CMP_EN_TIMER(13) | 753f353cecSAlbert ARIBAUD \\(3ADEV\\) DDRMC_CR154_PAD_ZQ_MODE(1) | 763f353cecSAlbert ARIBAUD \\(3ADEV\\) DDRMC_CR154_DDR_SEL_PAD_CONTR(3) | 773f353cecSAlbert ARIBAUD \\(3ADEV\\) DDRMC_CR154_PAD_ZQ_HW_FOR(1), 154 }, 783f353cecSAlbert ARIBAUD \\(3ADEV\\) { DDRMC_CR155_PAD_ODT_BYTE1(1) | DDRMC_CR155_PAD_ODT_BYTE0(1), 155 }, 793f353cecSAlbert ARIBAUD \\(3ADEV\\) { DDRMC_CR158_TWR(6), 158 }, 803f353cecSAlbert ARIBAUD \\(3ADEV\\) { DDRMC_CR161_ODT_EN(1) | DDRMC_CR161_TODTH_RD(2) | 813f353cecSAlbert ARIBAUD \\(3ADEV\\) DDRMC_CR161_TODTH_WR(2), 161 }, 823f353cecSAlbert ARIBAUD \\(3ADEV\\) /* end marker */ 833f353cecSAlbert ARIBAUD \\(3ADEV\\) { 0, -1 } 84c7ea243cSSanchayan Maity }; 858c653124SAlison Wang 863f353cecSAlbert ARIBAUD \\(3ADEV\\) int dram_init(void) 873f353cecSAlbert ARIBAUD \\(3ADEV\\) { 88c7ea243cSSanchayan Maity static const struct ddr3_jedec_timings timings = { 89c7ea243cSSanchayan Maity .tinit = 5, 90c7ea243cSSanchayan Maity .trst_pwron = 80000, 91c7ea243cSSanchayan Maity .cke_inactive = 200000, 92c7ea243cSSanchayan Maity .wrlat = 5, 93c7ea243cSSanchayan Maity .caslat_lin = 12, 94c7ea243cSSanchayan Maity .trc = 21, 95c7ea243cSSanchayan Maity .trrd = 4, 96c7ea243cSSanchayan Maity .tccd = 4, 973f353cecSAlbert ARIBAUD \\(3ADEV\\) .tbst_int_interval = 0, 98c7ea243cSSanchayan Maity .tfaw = 20, 99c7ea243cSSanchayan Maity .trp = 6, 100c7ea243cSSanchayan Maity .twtr = 4, 101c7ea243cSSanchayan Maity .tras_min = 15, 102c7ea243cSSanchayan Maity .tmrd = 4, 103c7ea243cSSanchayan Maity .trtp = 4, 104c7ea243cSSanchayan Maity .tras_max = 28080, 105c7ea243cSSanchayan Maity .tmod = 12, 106c7ea243cSSanchayan Maity .tckesr = 4, 107c7ea243cSSanchayan Maity .tcke = 3, 108c7ea243cSSanchayan Maity .trcd_int = 6, 1093f353cecSAlbert ARIBAUD \\(3ADEV\\) .tras_lockout = 0, 110c7ea243cSSanchayan Maity .tdal = 12, 111*4b8cdd48SAnthony Felice .bstlen = 3, 112c7ea243cSSanchayan Maity .tdll = 512, 113c7ea243cSSanchayan Maity .trp_ab = 6, 114c7ea243cSSanchayan Maity .tref = 3120, 115c7ea243cSSanchayan Maity .trfc = 44, 1163f353cecSAlbert ARIBAUD \\(3ADEV\\) .tref_int = 0, 117c7ea243cSSanchayan Maity .tpdex = 3, 118c7ea243cSSanchayan Maity .txpdll = 10, 119c7ea243cSSanchayan Maity .txsnr = 48, 120c7ea243cSSanchayan Maity .txsr = 468, 121c7ea243cSSanchayan Maity .cksrx = 5, 122c7ea243cSSanchayan Maity .cksre = 5, 1233f353cecSAlbert ARIBAUD \\(3ADEV\\) .freq_chg_en = 0, 124c7ea243cSSanchayan Maity .zqcl = 256, 125c7ea243cSSanchayan Maity .zqinit = 512, 126c7ea243cSSanchayan Maity .zqcs = 64, 127c7ea243cSSanchayan Maity .ref_per_zq = 64, 1283f353cecSAlbert ARIBAUD \\(3ADEV\\) .zqcs_rotate = 0, 129c7ea243cSSanchayan Maity .aprebit = 10, 1303f353cecSAlbert ARIBAUD \\(3ADEV\\) .cmd_age_cnt = 64, 1313f353cecSAlbert ARIBAUD \\(3ADEV\\) .age_cnt = 64, 1323f353cecSAlbert ARIBAUD \\(3ADEV\\) .q_fullness = 7, 1333f353cecSAlbert ARIBAUD \\(3ADEV\\) .odt_rd_mapcs0 = 0, 1343f353cecSAlbert ARIBAUD \\(3ADEV\\) .odt_wr_mapcs0 = 1, 135c7ea243cSSanchayan Maity .wlmrd = 40, 136c7ea243cSSanchayan Maity .wldqsen = 25, 137c7ea243cSSanchayan Maity }; 138c7ea243cSSanchayan Maity 1393f353cecSAlbert ARIBAUD \\(3ADEV\\) ddrmc_setup_iomux(NULL, 0); 140c7ea243cSSanchayan Maity 1413f353cecSAlbert ARIBAUD \\(3ADEV\\) ddrmc_ctrl_init_ddr3(&timings, vf610twr_cr_settings, NULL, 1, 3); 1428c653124SAlison Wang gd->ram_size = get_ram_size((void *)PHYS_SDRAM, PHYS_SDRAM_SIZE); 1438c653124SAlison Wang 1448c653124SAlison Wang return 0; 1458c653124SAlison Wang } 1468c653124SAlison Wang 1478c653124SAlison Wang static void setup_iomux_uart(void) 1488c653124SAlison Wang { 1498c653124SAlison Wang static const iomux_v3_cfg_t uart1_pads[] = { 1508c653124SAlison Wang NEW_PAD_CTRL(VF610_PAD_PTB4__UART1_TX, UART_PAD_CTRL), 1518c653124SAlison Wang NEW_PAD_CTRL(VF610_PAD_PTB5__UART1_RX, UART_PAD_CTRL), 1528c653124SAlison Wang }; 1538c653124SAlison Wang 1548c653124SAlison Wang imx_iomux_v3_setup_multiple_pads(uart1_pads, ARRAY_SIZE(uart1_pads)); 1558c653124SAlison Wang } 1568c653124SAlison Wang 1578c653124SAlison Wang static void setup_iomux_enet(void) 1588c653124SAlison Wang { 1598c653124SAlison Wang static const iomux_v3_cfg_t enet0_pads[] = { 1608c653124SAlison Wang NEW_PAD_CTRL(VF610_PAD_PTA6__RMII0_CLKIN, ENET_PAD_CTRL), 1618c653124SAlison Wang NEW_PAD_CTRL(VF610_PAD_PTC1__RMII0_MDIO, ENET_PAD_CTRL), 1628c653124SAlison Wang NEW_PAD_CTRL(VF610_PAD_PTC0__RMII0_MDC, ENET_PAD_CTRL), 1638c653124SAlison Wang NEW_PAD_CTRL(VF610_PAD_PTC2__RMII0_CRS_DV, ENET_PAD_CTRL), 1648c653124SAlison Wang NEW_PAD_CTRL(VF610_PAD_PTC3__RMII0_RD1, ENET_PAD_CTRL), 1658c653124SAlison Wang NEW_PAD_CTRL(VF610_PAD_PTC4__RMII0_RD0, ENET_PAD_CTRL), 1668c653124SAlison Wang NEW_PAD_CTRL(VF610_PAD_PTC5__RMII0_RXER, ENET_PAD_CTRL), 1678c653124SAlison Wang NEW_PAD_CTRL(VF610_PAD_PTC6__RMII0_TD1, ENET_PAD_CTRL), 1688c653124SAlison Wang NEW_PAD_CTRL(VF610_PAD_PTC7__RMII0_TD0, ENET_PAD_CTRL), 1698c653124SAlison Wang NEW_PAD_CTRL(VF610_PAD_PTC8__RMII0_TXEN, ENET_PAD_CTRL), 1708c653124SAlison Wang }; 1718c653124SAlison Wang 1728c653124SAlison Wang imx_iomux_v3_setup_multiple_pads(enet0_pads, ARRAY_SIZE(enet0_pads)); 1738c653124SAlison Wang } 1748c653124SAlison Wang 1751221b3d7SAlison Wang static void setup_iomux_i2c(void) 1761221b3d7SAlison Wang { 1771221b3d7SAlison Wang static const iomux_v3_cfg_t i2c0_pads[] = { 1781221b3d7SAlison Wang VF610_PAD_PTB14__I2C0_SCL, 1791221b3d7SAlison Wang VF610_PAD_PTB15__I2C0_SDA, 1801221b3d7SAlison Wang }; 1811221b3d7SAlison Wang 1821221b3d7SAlison Wang imx_iomux_v3_setup_multiple_pads(i2c0_pads, ARRAY_SIZE(i2c0_pads)); 1831221b3d7SAlison Wang } 1841221b3d7SAlison Wang 185d6d07a9bSStefan Agner #ifdef CONFIG_NAND_VF610_NFC 186d6d07a9bSStefan Agner static void setup_iomux_nfc(void) 187d6d07a9bSStefan Agner { 188d6d07a9bSStefan Agner static const iomux_v3_cfg_t nfc_pads[] = { 189d6d07a9bSStefan Agner VF610_PAD_PTD31__NF_IO15, 190d6d07a9bSStefan Agner VF610_PAD_PTD30__NF_IO14, 191d6d07a9bSStefan Agner VF610_PAD_PTD29__NF_IO13, 192d6d07a9bSStefan Agner VF610_PAD_PTD28__NF_IO12, 193d6d07a9bSStefan Agner VF610_PAD_PTD27__NF_IO11, 194d6d07a9bSStefan Agner VF610_PAD_PTD26__NF_IO10, 195d6d07a9bSStefan Agner VF610_PAD_PTD25__NF_IO9, 196d6d07a9bSStefan Agner VF610_PAD_PTD24__NF_IO8, 197d6d07a9bSStefan Agner VF610_PAD_PTD23__NF_IO7, 198d6d07a9bSStefan Agner VF610_PAD_PTD22__NF_IO6, 199d6d07a9bSStefan Agner VF610_PAD_PTD21__NF_IO5, 200d6d07a9bSStefan Agner VF610_PAD_PTD20__NF_IO4, 201d6d07a9bSStefan Agner VF610_PAD_PTD19__NF_IO3, 202d6d07a9bSStefan Agner VF610_PAD_PTD18__NF_IO2, 203d6d07a9bSStefan Agner VF610_PAD_PTD17__NF_IO1, 204d6d07a9bSStefan Agner VF610_PAD_PTD16__NF_IO0, 205d6d07a9bSStefan Agner VF610_PAD_PTB24__NF_WE_B, 206d6d07a9bSStefan Agner VF610_PAD_PTB25__NF_CE0_B, 207d6d07a9bSStefan Agner VF610_PAD_PTB27__NF_RE_B, 208d6d07a9bSStefan Agner VF610_PAD_PTC26__NF_RB_B, 209d6d07a9bSStefan Agner VF610_PAD_PTC27__NF_ALE, 210d6d07a9bSStefan Agner VF610_PAD_PTC28__NF_CLE 211d6d07a9bSStefan Agner }; 212d6d07a9bSStefan Agner 213d6d07a9bSStefan Agner imx_iomux_v3_setup_multiple_pads(nfc_pads, ARRAY_SIZE(nfc_pads)); 214d6d07a9bSStefan Agner } 215d6d07a9bSStefan Agner #endif 216d6d07a9bSStefan Agner 217d6d07a9bSStefan Agner 218cb6d04d6SChao Fu static void setup_iomux_qspi(void) 219cb6d04d6SChao Fu { 220cb6d04d6SChao Fu static const iomux_v3_cfg_t qspi0_pads[] = { 221cb6d04d6SChao Fu VF610_PAD_PTD0__QSPI0_A_QSCK, 222cb6d04d6SChao Fu VF610_PAD_PTD1__QSPI0_A_CS0, 223cb6d04d6SChao Fu VF610_PAD_PTD2__QSPI0_A_DATA3, 224cb6d04d6SChao Fu VF610_PAD_PTD3__QSPI0_A_DATA2, 225cb6d04d6SChao Fu VF610_PAD_PTD4__QSPI0_A_DATA1, 226cb6d04d6SChao Fu VF610_PAD_PTD5__QSPI0_A_DATA0, 227cb6d04d6SChao Fu VF610_PAD_PTD7__QSPI0_B_QSCK, 228cb6d04d6SChao Fu VF610_PAD_PTD8__QSPI0_B_CS0, 229cb6d04d6SChao Fu VF610_PAD_PTD9__QSPI0_B_DATA3, 230cb6d04d6SChao Fu VF610_PAD_PTD10__QSPI0_B_DATA2, 231cb6d04d6SChao Fu VF610_PAD_PTD11__QSPI0_B_DATA1, 232cb6d04d6SChao Fu VF610_PAD_PTD12__QSPI0_B_DATA0, 233cb6d04d6SChao Fu }; 234cb6d04d6SChao Fu 235cb6d04d6SChao Fu imx_iomux_v3_setup_multiple_pads(qspi0_pads, ARRAY_SIZE(qspi0_pads)); 236cb6d04d6SChao Fu } 237cb6d04d6SChao Fu 2388c653124SAlison Wang #ifdef CONFIG_FSL_ESDHC 2398c653124SAlison Wang struct fsl_esdhc_cfg esdhc_cfg[1] = { 2408c653124SAlison Wang {ESDHC1_BASE_ADDR}, 2418c653124SAlison Wang }; 2428c653124SAlison Wang 2438c653124SAlison Wang int board_mmc_getcd(struct mmc *mmc) 2448c653124SAlison Wang { 2458c653124SAlison Wang /* eSDHC1 is always present */ 2468c653124SAlison Wang return 1; 2478c653124SAlison Wang } 2488c653124SAlison Wang 2498c653124SAlison Wang int board_mmc_init(bd_t *bis) 2508c653124SAlison Wang { 2518c653124SAlison Wang static const iomux_v3_cfg_t esdhc1_pads[] = { 2528c653124SAlison Wang NEW_PAD_CTRL(VF610_PAD_PTA24__ESDHC1_CLK, ESDHC_PAD_CTRL), 2538c653124SAlison Wang NEW_PAD_CTRL(VF610_PAD_PTA25__ESDHC1_CMD, ESDHC_PAD_CTRL), 2548c653124SAlison Wang NEW_PAD_CTRL(VF610_PAD_PTA26__ESDHC1_DAT0, ESDHC_PAD_CTRL), 2558c653124SAlison Wang NEW_PAD_CTRL(VF610_PAD_PTA27__ESDHC1_DAT1, ESDHC_PAD_CTRL), 2568c653124SAlison Wang NEW_PAD_CTRL(VF610_PAD_PTA28__ESDHC1_DAT2, ESDHC_PAD_CTRL), 2578c653124SAlison Wang NEW_PAD_CTRL(VF610_PAD_PTA29__ESDHC1_DAT3, ESDHC_PAD_CTRL), 2588c653124SAlison Wang }; 2598c653124SAlison Wang 2608c653124SAlison Wang esdhc_cfg[0].sdhc_clk = mxc_get_clock(MXC_ESDHC_CLK); 2618c653124SAlison Wang 2628c653124SAlison Wang imx_iomux_v3_setup_multiple_pads( 2638c653124SAlison Wang esdhc1_pads, ARRAY_SIZE(esdhc1_pads)); 2648c653124SAlison Wang 2654a1c7b13SFabio Estevam return fsl_esdhc_initialize(bis, &esdhc_cfg[0]); 2668c653124SAlison Wang } 2678c653124SAlison Wang #endif 2688c653124SAlison Wang 2698c653124SAlison Wang static void clock_init(void) 2708c653124SAlison Wang { 2718c653124SAlison Wang struct ccm_reg *ccm = (struct ccm_reg *)CCM_BASE_ADDR; 2728c653124SAlison Wang struct anadig_reg *anadig = (struct anadig_reg *)ANADIG_BASE_ADDR; 2738c653124SAlison Wang 2748c653124SAlison Wang clrsetbits_le32(&ccm->ccgr0, CCM_REG_CTRL_MASK, 2758c653124SAlison Wang CCM_CCGR0_UART1_CTRL_MASK); 2768c653124SAlison Wang clrsetbits_le32(&ccm->ccgr1, CCM_REG_CTRL_MASK, 2778c653124SAlison Wang CCM_CCGR1_PIT_CTRL_MASK | CCM_CCGR1_WDOGA5_CTRL_MASK); 2788c653124SAlison Wang clrsetbits_le32(&ccm->ccgr2, CCM_REG_CTRL_MASK, 2798c653124SAlison Wang CCM_CCGR2_IOMUXC_CTRL_MASK | CCM_CCGR2_PORTA_CTRL_MASK | 2808c653124SAlison Wang CCM_CCGR2_PORTB_CTRL_MASK | CCM_CCGR2_PORTC_CTRL_MASK | 281cb6d04d6SChao Fu CCM_CCGR2_PORTD_CTRL_MASK | CCM_CCGR2_PORTE_CTRL_MASK | 282cb6d04d6SChao Fu CCM_CCGR2_QSPI0_CTRL_MASK); 2838c653124SAlison Wang clrsetbits_le32(&ccm->ccgr3, CCM_REG_CTRL_MASK, 2848b4f9afaSStefan Agner CCM_CCGR3_ANADIG_CTRL_MASK | CCM_CCGR3_SCSC_CTRL_MASK); 2858c653124SAlison Wang clrsetbits_le32(&ccm->ccgr4, CCM_REG_CTRL_MASK, 2868c653124SAlison Wang CCM_CCGR4_WKUP_CTRL_MASK | CCM_CCGR4_CCM_CTRL_MASK | 2871221b3d7SAlison Wang CCM_CCGR4_GPC_CTRL_MASK | CCM_CCGR4_I2C0_CTRL_MASK); 2888c653124SAlison Wang clrsetbits_le32(&ccm->ccgr6, CCM_REG_CTRL_MASK, 2898c653124SAlison Wang CCM_CCGR6_OCOTP_CTRL_MASK | CCM_CCGR6_DDRMC_CTRL_MASK); 2908c653124SAlison Wang clrsetbits_le32(&ccm->ccgr7, CCM_REG_CTRL_MASK, 2918c653124SAlison Wang CCM_CCGR7_SDHC1_CTRL_MASK); 2928c653124SAlison Wang clrsetbits_le32(&ccm->ccgr9, CCM_REG_CTRL_MASK, 2938c653124SAlison Wang CCM_CCGR9_FEC0_CTRL_MASK | CCM_CCGR9_FEC1_CTRL_MASK); 294d6d07a9bSStefan Agner clrsetbits_le32(&ccm->ccgr10, CCM_REG_CTRL_MASK, 295d6d07a9bSStefan Agner CCM_CCGR10_NFC_CTRL_MASK); 2968c653124SAlison Wang 2978c653124SAlison Wang clrsetbits_le32(&anadig->pll2_ctrl, ANADIG_PLL2_CTRL_POWERDOWN, 2988c653124SAlison Wang ANADIG_PLL2_CTRL_ENABLE | ANADIG_PLL2_CTRL_DIV_SELECT); 2998c653124SAlison Wang clrsetbits_le32(&anadig->pll1_ctrl, ANADIG_PLL1_CTRL_POWERDOWN, 3008c653124SAlison Wang ANADIG_PLL1_CTRL_ENABLE | ANADIG_PLL1_CTRL_DIV_SELECT); 3018c653124SAlison Wang 3028c653124SAlison Wang clrsetbits_le32(&ccm->ccr, CCM_CCR_OSCNT_MASK, 3038c653124SAlison Wang CCM_CCR_FIRC_EN | CCM_CCR_OSCNT(5)); 3048c653124SAlison Wang clrsetbits_le32(&ccm->ccsr, CCM_REG_CTRL_MASK, 3058c653124SAlison Wang CCM_CCSR_PLL1_PFD_CLK_SEL(3) | CCM_CCSR_PLL2_PFD4_EN | 3068c653124SAlison Wang CCM_CCSR_PLL2_PFD3_EN | CCM_CCSR_PLL2_PFD2_EN | 3078c653124SAlison Wang CCM_CCSR_PLL2_PFD1_EN | CCM_CCSR_PLL1_PFD4_EN | 3088c653124SAlison Wang CCM_CCSR_PLL1_PFD3_EN | CCM_CCSR_PLL1_PFD2_EN | 3098c653124SAlison Wang CCM_CCSR_PLL1_PFD1_EN | CCM_CCSR_DDRC_CLK_SEL(1) | 3108c653124SAlison Wang CCM_CCSR_FAST_CLK_SEL(1) | CCM_CCSR_SYS_CLK_SEL(4)); 3118c653124SAlison Wang clrsetbits_le32(&ccm->cacrr, CCM_REG_CTRL_MASK, 3128c653124SAlison Wang CCM_CACRR_IPG_CLK_DIV(1) | CCM_CACRR_BUS_CLK_DIV(2) | 3138c653124SAlison Wang CCM_CACRR_ARM_CLK_DIV(0)); 3148c653124SAlison Wang clrsetbits_le32(&ccm->cscmr1, CCM_REG_CTRL_MASK, 315d6d07a9bSStefan Agner CCM_CSCMR1_ESDHC1_CLK_SEL(3) | CCM_CSCMR1_QSPI0_CLK_SEL(3) | 316d6d07a9bSStefan Agner CCM_CSCMR1_NFC_CLK_SEL(0)); 3178c653124SAlison Wang clrsetbits_le32(&ccm->cscdr1, CCM_REG_CTRL_MASK, 3188c653124SAlison Wang CCM_CSCDR1_RMII_CLK_EN); 3198c653124SAlison Wang clrsetbits_le32(&ccm->cscdr2, CCM_REG_CTRL_MASK, 320d6d07a9bSStefan Agner CCM_CSCDR2_ESDHC1_EN | CCM_CSCDR2_ESDHC1_CLK_DIV(0) | 321d6d07a9bSStefan Agner CCM_CSCDR2_NFC_EN); 322cb6d04d6SChao Fu clrsetbits_le32(&ccm->cscdr3, CCM_REG_CTRL_MASK, 323cb6d04d6SChao Fu CCM_CSCDR3_QSPI0_EN | CCM_CSCDR3_QSPI0_DIV(1) | 324d6d07a9bSStefan Agner CCM_CSCDR3_QSPI0_X2_DIV(1) | CCM_CSCDR3_QSPI0_X4_DIV(3) | 325d6d07a9bSStefan Agner CCM_CSCDR3_NFC_PRE_DIV(5)); 3268c653124SAlison Wang clrsetbits_le32(&ccm->cscmr2, CCM_REG_CTRL_MASK, 3278c653124SAlison Wang CCM_CSCMR2_RMII_CLK_SEL(0)); 3288c653124SAlison Wang } 3298c653124SAlison Wang 3308c653124SAlison Wang static void mscm_init(void) 3318c653124SAlison Wang { 3328c653124SAlison Wang struct mscm_ir *mscmir = (struct mscm_ir *)MSCM_IR_BASE_ADDR; 3338c653124SAlison Wang int i; 3348c653124SAlison Wang 3358c653124SAlison Wang for (i = 0; i < MSCM_IRSPRC_NUM; i++) 3368c653124SAlison Wang writew(MSCM_IRSPRC_CP0_EN, &mscmir->irsprc[i]); 3378c653124SAlison Wang } 3388c653124SAlison Wang 3398c653124SAlison Wang int board_phy_config(struct phy_device *phydev) 3408c653124SAlison Wang { 3418c653124SAlison Wang if (phydev->drv->config) 3428c653124SAlison Wang phydev->drv->config(phydev); 3438c653124SAlison Wang 3448c653124SAlison Wang return 0; 3458c653124SAlison Wang } 3468c653124SAlison Wang 3478c653124SAlison Wang int board_early_init_f(void) 3488c653124SAlison Wang { 3498c653124SAlison Wang clock_init(); 3508c653124SAlison Wang mscm_init(); 3518c653124SAlison Wang 3528c653124SAlison Wang setup_iomux_uart(); 3538c653124SAlison Wang setup_iomux_enet(); 3541221b3d7SAlison Wang setup_iomux_i2c(); 355cb6d04d6SChao Fu setup_iomux_qspi(); 356d6d07a9bSStefan Agner #ifdef CONFIG_NAND_VF610_NFC 357d6d07a9bSStefan Agner setup_iomux_nfc(); 358d6d07a9bSStefan Agner #endif 3598c653124SAlison Wang 3608c653124SAlison Wang return 0; 3618c653124SAlison Wang } 3628c653124SAlison Wang 3638c653124SAlison Wang int board_init(void) 3648c653124SAlison Wang { 3658b4f9afaSStefan Agner struct scsc_reg *scsc = (struct scsc_reg *)SCSC_BASE_ADDR; 3668b4f9afaSStefan Agner 3678c653124SAlison Wang /* address of boot parameters */ 3688c653124SAlison Wang gd->bd->bi_boot_params = PHYS_SDRAM + 0x100; 3698c653124SAlison Wang 3708b4f9afaSStefan Agner /* 3718b4f9afaSStefan Agner * Enable external 32K Oscillator 3728b4f9afaSStefan Agner * 3738b4f9afaSStefan Agner * The internal clock experiences significant drift 3748b4f9afaSStefan Agner * so we must use the external oscillator in order 3758b4f9afaSStefan Agner * to maintain correct time in the hwclock 3768b4f9afaSStefan Agner */ 3778b4f9afaSStefan Agner setbits_le32(&scsc->sosc_ctr, SCSC_SOSC_CTR_SOSC_EN); 3788b4f9afaSStefan Agner 3798c653124SAlison Wang return 0; 3808c653124SAlison Wang } 3818c653124SAlison Wang 3828c653124SAlison Wang int checkboard(void) 3838c653124SAlison Wang { 3848c653124SAlison Wang puts("Board: vf610twr\n"); 3858c653124SAlison Wang 3868c653124SAlison Wang return 0; 3878c653124SAlison Wang } 388