1 /* 2 * Copyright 2014 Freescale Semiconductor, Inc. 3 * 4 * SPDX-License-Identifier: GPL-2.0+ 5 */ 6 7 #include <common.h> 8 #include <asm/mmu.h> 9 10 struct fsl_e_tlb_entry tlb_table[] = { 11 /* TLB 0 - for temp stack in cache */ 12 SET_TLB_ENTRY(0, CONFIG_SYS_INIT_RAM_ADDR, 13 CONFIG_SYS_INIT_RAM_ADDR_PHYS, 14 MAS3_SX|MAS3_SW|MAS3_SR, 0, 15 0, 0, BOOKE_PAGESZ_4K, 0), 16 SET_TLB_ENTRY(0, CONFIG_SYS_INIT_RAM_ADDR + 4 * 1024, 17 CONFIG_SYS_INIT_RAM_ADDR_PHYS + 4 * 1024, 18 MAS3_SX|MAS3_SW|MAS3_SR, 0, 19 0, 0, BOOKE_PAGESZ_4K, 0), 20 SET_TLB_ENTRY(0, CONFIG_SYS_INIT_RAM_ADDR + 8 * 1024, 21 CONFIG_SYS_INIT_RAM_ADDR_PHYS + 8 * 1024, 22 MAS3_SX|MAS3_SW|MAS3_SR, 0, 23 0, 0, BOOKE_PAGESZ_4K, 0), 24 SET_TLB_ENTRY(0, CONFIG_SYS_INIT_RAM_ADDR + 12 * 1024, 25 CONFIG_SYS_INIT_RAM_ADDR_PHYS + 12 * 1024, 26 MAS3_SX|MAS3_SW|MAS3_SR, 0, 27 0, 0, BOOKE_PAGESZ_4K, 0), 28 29 /* TLB 1 */ 30 /* *I*** - Covers boot page */ 31 #if defined(CONFIG_SYS_RAMBOOT) && defined(CONFIG_SYS_INIT_L3_ADDR) 32 /* 33 * *I*G - L3SRAM. When L3 is used as 512K SRAM */ 34 SET_TLB_ENTRY(1, CONFIG_SYS_INIT_L3_ADDR, CONFIG_SYS_INIT_L3_ADDR, 35 MAS3_SX|MAS3_SW|MAS3_SR, MAS2_I|MAS2_G, 36 0, 0, BOOKE_PAGESZ_512K, 1), 37 #else 38 SET_TLB_ENTRY(1, 0xfffff000, 0xfffff000, 39 MAS3_SX|MAS3_SW|MAS3_SR, MAS2_I|MAS2_G, 40 0, 0, BOOKE_PAGESZ_4K, 1), 41 #endif 42 43 /* *I*G* - CCSRBAR */ 44 SET_TLB_ENTRY(1, CONFIG_SYS_CCSRBAR, CONFIG_SYS_CCSRBAR_PHYS, 45 MAS3_SX|MAS3_SW|MAS3_SR, MAS2_I|MAS2_G, 46 0, 1, BOOKE_PAGESZ_16M, 1), 47 48 /* *I*G* - Flash, localbus */ 49 /* This will be changed to *I*G* after relocation to RAM. */ 50 SET_TLB_ENTRY(1, CONFIG_SYS_FLASH_BASE, CONFIG_SYS_FLASH_BASE_PHYS, 51 MAS3_SX|MAS3_SR, MAS2_W|MAS2_G, 52 0, 2, BOOKE_PAGESZ_256M, 1), 53 54 #ifndef CONFIG_SPL_BUILD 55 /* *I*G* - PCI */ 56 SET_TLB_ENTRY(1, CONFIG_SYS_PCIE1_MEM_VIRT, CONFIG_SYS_PCIE1_MEM_PHYS, 57 MAS3_SX|MAS3_SW|MAS3_SR, MAS2_I|MAS2_G, 58 0, 3, BOOKE_PAGESZ_1G, 1), 59 60 /* *I*G* - PCI */ 61 SET_TLB_ENTRY(1, CONFIG_SYS_PCIE1_MEM_VIRT + 0x40000000, 62 CONFIG_SYS_PCIE1_MEM_PHYS + 0x40000000, 63 MAS3_SX|MAS3_SW|MAS3_SR, MAS2_I|MAS2_G, 64 0, 4, BOOKE_PAGESZ_256M, 1), 65 66 SET_TLB_ENTRY(1, CONFIG_SYS_PCIE1_MEM_VIRT + 0x50000000, 67 CONFIG_SYS_PCIE1_MEM_PHYS + 0x50000000, 68 MAS3_SX|MAS3_SW|MAS3_SR, MAS2_I|MAS2_G, 69 0, 5, BOOKE_PAGESZ_256M, 1), 70 71 /* *I*G* - PCI I/O */ 72 SET_TLB_ENTRY(1, CONFIG_SYS_PCIE1_IO_VIRT, CONFIG_SYS_PCIE1_IO_PHYS, 73 MAS3_SX|MAS3_SW|MAS3_SR, MAS2_I|MAS2_G, 74 0, 6, BOOKE_PAGESZ_256K, 1), 75 76 /* Bman/Qman */ 77 #ifdef CONFIG_SYS_BMAN_MEM_PHYS 78 SET_TLB_ENTRY(1, CONFIG_SYS_BMAN_MEM_BASE, CONFIG_SYS_BMAN_MEM_PHYS, 79 MAS3_SX|MAS3_SW|MAS3_SR, 0, 80 0, 9, BOOKE_PAGESZ_16M, 1), 81 SET_TLB_ENTRY(1, CONFIG_SYS_BMAN_MEM_BASE + 0x01000000, 82 CONFIG_SYS_BMAN_MEM_PHYS + 0x01000000, 83 MAS3_SX|MAS3_SW|MAS3_SR, MAS2_I|MAS2_G, 84 0, 10, BOOKE_PAGESZ_16M, 1), 85 #endif 86 #ifdef CONFIG_SYS_QMAN_MEM_PHYS 87 SET_TLB_ENTRY(1, CONFIG_SYS_QMAN_MEM_BASE, CONFIG_SYS_QMAN_MEM_PHYS, 88 MAS3_SX|MAS3_SW|MAS3_SR, 0, 89 0, 11, BOOKE_PAGESZ_16M, 1), 90 SET_TLB_ENTRY(1, CONFIG_SYS_QMAN_MEM_BASE + 0x01000000, 91 CONFIG_SYS_QMAN_MEM_PHYS + 0x01000000, 92 MAS3_SX|MAS3_SW|MAS3_SR, MAS2_I|MAS2_G, 93 0, 12, BOOKE_PAGESZ_16M, 1), 94 #endif 95 #endif 96 97 #ifdef CONFIG_SYS_DCSRBAR_PHYS 98 SET_TLB_ENTRY(1, CONFIG_SYS_DCSRBAR, CONFIG_SYS_DCSRBAR_PHYS, 99 MAS3_SX|MAS3_SW|MAS3_SR, MAS2_I|MAS2_G, 100 0, 13, BOOKE_PAGESZ_32M, 1), 101 #endif 102 #ifdef CONFIG_SYS_NAND_BASE 103 /* 104 * *I*G - NAND 105 * entry 14 and 15 has been used hard coded, they will be disabled 106 * in cpu_init_f, so we use entry 16 for nand. 107 */ 108 SET_TLB_ENTRY(1, CONFIG_SYS_NAND_BASE, CONFIG_SYS_NAND_BASE_PHYS, 109 MAS3_SX|MAS3_SW|MAS3_SR, MAS2_I|MAS2_G, 110 0, 16, BOOKE_PAGESZ_64K, 1), 111 #endif 112 #ifdef CONFIG_SYS_CPLD_BASE 113 SET_TLB_ENTRY(1, CONFIG_SYS_CPLD_BASE, CONFIG_SYS_CPLD_BASE_PHYS, 114 MAS3_SW|MAS3_SW|MAS3_SR, MAS2_I|MAS2_G, 115 0, 17, BOOKE_PAGESZ_4K, 1), 116 #endif 117 #if defined(CONFIG_RAMBOOT_PBL) && !defined(CONFIG_SPL_BUILD) 118 SET_TLB_ENTRY(1, CONFIG_SYS_DDR_SDRAM_BASE, CONFIG_SYS_DDR_SDRAM_BASE, 119 MAS3_SX|MAS3_SW|MAS3_SR, MAS2_M, 120 0, 18, BOOKE_PAGESZ_2G, 1) 121 #endif 122 }; 123 124 int num_tlb_entries = ARRAY_SIZE(tlb_table); 125