1*0b2e13d9SChunhe Lan /* 2*0b2e13d9SChunhe Lan * Copyright 2014 Freescale Semiconductor, Inc. 3*0b2e13d9SChunhe Lan * 4*0b2e13d9SChunhe Lan * SPDX-License-Identifier: GPL-2.0+ 5*0b2e13d9SChunhe Lan */ 6*0b2e13d9SChunhe Lan 7*0b2e13d9SChunhe Lan #include <common.h> 8*0b2e13d9SChunhe Lan #include <asm/mmu.h> 9*0b2e13d9SChunhe Lan 10*0b2e13d9SChunhe Lan struct fsl_e_tlb_entry tlb_table[] = { 11*0b2e13d9SChunhe Lan /* TLB 0 - for temp stack in cache */ 12*0b2e13d9SChunhe Lan SET_TLB_ENTRY(0, CONFIG_SYS_INIT_RAM_ADDR, 13*0b2e13d9SChunhe Lan CONFIG_SYS_INIT_RAM_ADDR_PHYS, 14*0b2e13d9SChunhe Lan MAS3_SX|MAS3_SW|MAS3_SR, 0, 15*0b2e13d9SChunhe Lan 0, 0, BOOKE_PAGESZ_4K, 0), 16*0b2e13d9SChunhe Lan SET_TLB_ENTRY(0, CONFIG_SYS_INIT_RAM_ADDR + 4 * 1024, 17*0b2e13d9SChunhe Lan CONFIG_SYS_INIT_RAM_ADDR_PHYS + 4 * 1024, 18*0b2e13d9SChunhe Lan MAS3_SX|MAS3_SW|MAS3_SR, 0, 19*0b2e13d9SChunhe Lan 0, 0, BOOKE_PAGESZ_4K, 0), 20*0b2e13d9SChunhe Lan SET_TLB_ENTRY(0, CONFIG_SYS_INIT_RAM_ADDR + 8 * 1024, 21*0b2e13d9SChunhe Lan CONFIG_SYS_INIT_RAM_ADDR_PHYS + 8 * 1024, 22*0b2e13d9SChunhe Lan MAS3_SX|MAS3_SW|MAS3_SR, 0, 23*0b2e13d9SChunhe Lan 0, 0, BOOKE_PAGESZ_4K, 0), 24*0b2e13d9SChunhe Lan SET_TLB_ENTRY(0, CONFIG_SYS_INIT_RAM_ADDR + 12 * 1024, 25*0b2e13d9SChunhe Lan CONFIG_SYS_INIT_RAM_ADDR_PHYS + 12 * 1024, 26*0b2e13d9SChunhe Lan MAS3_SX|MAS3_SW|MAS3_SR, 0, 27*0b2e13d9SChunhe Lan 0, 0, BOOKE_PAGESZ_4K, 0), 28*0b2e13d9SChunhe Lan 29*0b2e13d9SChunhe Lan /* TLB 1 */ 30*0b2e13d9SChunhe Lan /* *I*** - Covers boot page */ 31*0b2e13d9SChunhe Lan #if defined(CONFIG_SYS_RAMBOOT) && defined(CONFIG_SYS_INIT_L3_ADDR) 32*0b2e13d9SChunhe Lan /* 33*0b2e13d9SChunhe Lan * *I*G - L3SRAM. When L3 is used as 512K SRAM */ 34*0b2e13d9SChunhe Lan SET_TLB_ENTRY(1, CONFIG_SYS_INIT_L3_ADDR, CONFIG_SYS_INIT_L3_ADDR, 35*0b2e13d9SChunhe Lan MAS3_SX|MAS3_SW|MAS3_SR, MAS2_I|MAS2_G, 36*0b2e13d9SChunhe Lan 0, 0, BOOKE_PAGESZ_512K, 1), 37*0b2e13d9SChunhe Lan #else 38*0b2e13d9SChunhe Lan SET_TLB_ENTRY(1, 0xfffff000, 0xfffff000, 39*0b2e13d9SChunhe Lan MAS3_SX|MAS3_SW|MAS3_SR, MAS2_I|MAS2_G, 40*0b2e13d9SChunhe Lan 0, 0, BOOKE_PAGESZ_4K, 1), 41*0b2e13d9SChunhe Lan #endif 42*0b2e13d9SChunhe Lan 43*0b2e13d9SChunhe Lan /* *I*G* - CCSRBAR */ 44*0b2e13d9SChunhe Lan SET_TLB_ENTRY(1, CONFIG_SYS_CCSRBAR, CONFIG_SYS_CCSRBAR_PHYS, 45*0b2e13d9SChunhe Lan MAS3_SX|MAS3_SW|MAS3_SR, MAS2_I|MAS2_G, 46*0b2e13d9SChunhe Lan 0, 1, BOOKE_PAGESZ_16M, 1), 47*0b2e13d9SChunhe Lan 48*0b2e13d9SChunhe Lan /* *I*G* - Flash, localbus */ 49*0b2e13d9SChunhe Lan /* This will be changed to *I*G* after relocation to RAM. */ 50*0b2e13d9SChunhe Lan SET_TLB_ENTRY(1, CONFIG_SYS_FLASH_BASE, CONFIG_SYS_FLASH_BASE_PHYS, 51*0b2e13d9SChunhe Lan MAS3_SX|MAS3_SR, MAS2_W|MAS2_G, 52*0b2e13d9SChunhe Lan 0, 2, BOOKE_PAGESZ_256M, 1), 53*0b2e13d9SChunhe Lan 54*0b2e13d9SChunhe Lan /* *I*G* - PCI */ 55*0b2e13d9SChunhe Lan SET_TLB_ENTRY(1, CONFIG_SYS_PCIE1_MEM_VIRT, CONFIG_SYS_PCIE1_MEM_PHYS, 56*0b2e13d9SChunhe Lan MAS3_SX|MAS3_SW|MAS3_SR, MAS2_I|MAS2_G, 57*0b2e13d9SChunhe Lan 0, 3, BOOKE_PAGESZ_1G, 1), 58*0b2e13d9SChunhe Lan 59*0b2e13d9SChunhe Lan /* *I*G* - PCI */ 60*0b2e13d9SChunhe Lan SET_TLB_ENTRY(1, CONFIG_SYS_PCIE1_MEM_VIRT + 0x40000000, 61*0b2e13d9SChunhe Lan CONFIG_SYS_PCIE1_MEM_PHYS + 0x40000000, 62*0b2e13d9SChunhe Lan MAS3_SX|MAS3_SW|MAS3_SR, MAS2_I|MAS2_G, 63*0b2e13d9SChunhe Lan 0, 4, BOOKE_PAGESZ_256M, 1), 64*0b2e13d9SChunhe Lan 65*0b2e13d9SChunhe Lan SET_TLB_ENTRY(1, CONFIG_SYS_PCIE1_MEM_VIRT + 0x50000000, 66*0b2e13d9SChunhe Lan CONFIG_SYS_PCIE1_MEM_PHYS + 0x50000000, 67*0b2e13d9SChunhe Lan MAS3_SX|MAS3_SW|MAS3_SR, MAS2_I|MAS2_G, 68*0b2e13d9SChunhe Lan 0, 5, BOOKE_PAGESZ_256M, 1), 69*0b2e13d9SChunhe Lan 70*0b2e13d9SChunhe Lan /* *I*G* - PCI I/O */ 71*0b2e13d9SChunhe Lan SET_TLB_ENTRY(1, CONFIG_SYS_PCIE1_IO_VIRT, CONFIG_SYS_PCIE1_IO_PHYS, 72*0b2e13d9SChunhe Lan MAS3_SX|MAS3_SW|MAS3_SR, MAS2_I|MAS2_G, 73*0b2e13d9SChunhe Lan 0, 6, BOOKE_PAGESZ_256K, 1), 74*0b2e13d9SChunhe Lan 75*0b2e13d9SChunhe Lan /* Bman/Qman */ 76*0b2e13d9SChunhe Lan #ifdef CONFIG_SYS_BMAN_MEM_PHYS 77*0b2e13d9SChunhe Lan SET_TLB_ENTRY(1, CONFIG_SYS_BMAN_MEM_BASE, CONFIG_SYS_BMAN_MEM_PHYS, 78*0b2e13d9SChunhe Lan MAS3_SX|MAS3_SW|MAS3_SR, 0, 79*0b2e13d9SChunhe Lan 0, 9, BOOKE_PAGESZ_16M, 1), 80*0b2e13d9SChunhe Lan SET_TLB_ENTRY(1, CONFIG_SYS_BMAN_MEM_BASE + 0x01000000, 81*0b2e13d9SChunhe Lan CONFIG_SYS_BMAN_MEM_PHYS + 0x01000000, 82*0b2e13d9SChunhe Lan MAS3_SX|MAS3_SW|MAS3_SR, MAS2_I|MAS2_G, 83*0b2e13d9SChunhe Lan 0, 10, BOOKE_PAGESZ_16M, 1), 84*0b2e13d9SChunhe Lan #endif 85*0b2e13d9SChunhe Lan #ifdef CONFIG_SYS_QMAN_MEM_PHYS 86*0b2e13d9SChunhe Lan SET_TLB_ENTRY(1, CONFIG_SYS_QMAN_MEM_BASE, CONFIG_SYS_QMAN_MEM_PHYS, 87*0b2e13d9SChunhe Lan MAS3_SX|MAS3_SW|MAS3_SR, 0, 88*0b2e13d9SChunhe Lan 0, 11, BOOKE_PAGESZ_16M, 1), 89*0b2e13d9SChunhe Lan SET_TLB_ENTRY(1, CONFIG_SYS_QMAN_MEM_BASE + 0x01000000, 90*0b2e13d9SChunhe Lan CONFIG_SYS_QMAN_MEM_PHYS + 0x01000000, 91*0b2e13d9SChunhe Lan MAS3_SX|MAS3_SW|MAS3_SR, MAS2_I|MAS2_G, 92*0b2e13d9SChunhe Lan 0, 12, BOOKE_PAGESZ_16M, 1), 93*0b2e13d9SChunhe Lan #endif 94*0b2e13d9SChunhe Lan #ifdef CONFIG_SYS_DCSRBAR_PHYS 95*0b2e13d9SChunhe Lan SET_TLB_ENTRY(1, CONFIG_SYS_DCSRBAR, CONFIG_SYS_DCSRBAR_PHYS, 96*0b2e13d9SChunhe Lan MAS3_SX|MAS3_SW|MAS3_SR, MAS2_I|MAS2_G, 97*0b2e13d9SChunhe Lan 0, 13, BOOKE_PAGESZ_32M, 1), 98*0b2e13d9SChunhe Lan #endif 99*0b2e13d9SChunhe Lan #ifdef CONFIG_SYS_NAND_BASE 100*0b2e13d9SChunhe Lan /* 101*0b2e13d9SChunhe Lan * *I*G - NAND 102*0b2e13d9SChunhe Lan * entry 14 and 15 has been used hard coded, they will be disabled 103*0b2e13d9SChunhe Lan * in cpu_init_f, so we use entry 16 for nand. 104*0b2e13d9SChunhe Lan */ 105*0b2e13d9SChunhe Lan SET_TLB_ENTRY(1, CONFIG_SYS_NAND_BASE, CONFIG_SYS_NAND_BASE_PHYS, 106*0b2e13d9SChunhe Lan MAS3_SX|MAS3_SW|MAS3_SR, MAS2_I|MAS2_G, 107*0b2e13d9SChunhe Lan 0, 16, BOOKE_PAGESZ_64K, 1), 108*0b2e13d9SChunhe Lan #endif 109*0b2e13d9SChunhe Lan }; 110*0b2e13d9SChunhe Lan 111*0b2e13d9SChunhe Lan int num_tlb_entries = ARRAY_SIZE(tlb_table); 112