1 // SPDX-License-Identifier: GPL-2.0+ 2 /* 3 * Copyright 2014 Freescale Semiconductor, Inc. 4 * 5 * Chunhe Lan <Chunhe.Lan@freescale.com> 6 */ 7 8 #include <common.h> 9 #include <command.h> 10 #include <netdev.h> 11 #include <asm/mmu.h> 12 #include <asm/processor.h> 13 #include <asm/cache.h> 14 #include <asm/immap_85xx.h> 15 #include <asm/fsl_law.h> 16 #include <fsl_ddr_sdram.h> 17 #include <asm/fsl_serdes.h> 18 #include <asm/fsl_portals.h> 19 #include <asm/fsl_liodn.h> 20 #include <malloc.h> 21 #include <fm_eth.h> 22 #include <fsl_mdio.h> 23 #include <miiphy.h> 24 #include <phy.h> 25 #include <fsl_dtsec.h> 26 #include <asm/fsl_serdes.h> 27 #include <hwconfig.h> 28 29 #include "../common/fman.h" 30 #include "t4rdb.h" 31 32 void fdt_fixup_board_enet(void *fdt) 33 { 34 return; 35 } 36 37 int board_eth_init(bd_t *bis) 38 { 39 #if defined(CONFIG_FMAN_ENET) 40 int i, interface; 41 struct memac_mdio_info dtsec_mdio_info; 42 struct memac_mdio_info tgec_mdio_info; 43 struct mii_dev *dev; 44 ccsr_gur_t *gur = (void *)(CONFIG_SYS_MPC85xx_GUTS_ADDR); 45 u32 srds_prtcl_s1, srds_prtcl_s2; 46 47 srds_prtcl_s1 = in_be32(&gur->rcwsr[4]) & 48 FSL_CORENET2_RCWSR4_SRDS1_PRTCL; 49 srds_prtcl_s1 >>= FSL_CORENET2_RCWSR4_SRDS1_PRTCL_SHIFT; 50 srds_prtcl_s2 = in_be32(&gur->rcwsr[4]) & 51 FSL_CORENET2_RCWSR4_SRDS2_PRTCL; 52 srds_prtcl_s2 >>= FSL_CORENET2_RCWSR4_SRDS2_PRTCL_SHIFT; 53 54 dtsec_mdio_info.regs = 55 (struct memac_mdio_controller *)CONFIG_SYS_FM2_DTSEC_MDIO_ADDR; 56 57 dtsec_mdio_info.name = DEFAULT_FM_MDIO_NAME; 58 59 /* Register the 1G MDIO bus */ 60 fm_memac_mdio_init(bis, &dtsec_mdio_info); 61 62 tgec_mdio_info.regs = 63 (struct memac_mdio_controller *)CONFIG_SYS_FM2_TGEC_MDIO_ADDR; 64 tgec_mdio_info.name = DEFAULT_FM_TGEC_MDIO_NAME; 65 66 /* Register the 10G MDIO bus */ 67 fm_memac_mdio_init(bis, &tgec_mdio_info); 68 69 if ((srds_prtcl_s1 == 28) || (srds_prtcl_s1 == 27)) { 70 /* SGMII */ 71 fm_info_set_phy_address(FM1_DTSEC1, SGMII_PHY_ADDR1); 72 fm_info_set_phy_address(FM1_DTSEC2, SGMII_PHY_ADDR2); 73 fm_info_set_phy_address(FM1_DTSEC3, SGMII_PHY_ADDR3); 74 fm_info_set_phy_address(FM1_DTSEC4, SGMII_PHY_ADDR4); 75 } else { 76 puts("Invalid SerDes1 protocol for T4240RDB\n"); 77 } 78 79 fm_disable_port(FM1_DTSEC5); 80 fm_disable_port(FM1_DTSEC6); 81 82 for (i = FM1_DTSEC1; i < FM1_DTSEC1 + CONFIG_SYS_NUM_FM1_DTSEC; i++) { 83 interface = fm_info_get_enet_if(i); 84 switch (interface) { 85 case PHY_INTERFACE_MODE_SGMII: 86 dev = miiphy_get_dev_by_name(DEFAULT_FM_MDIO_NAME); 87 fm_info_set_mdio(i, dev); 88 break; 89 default: 90 break; 91 } 92 } 93 94 for (i = FM1_10GEC1; i < FM1_10GEC1 + CONFIG_SYS_NUM_FM1_10GEC; i++) { 95 switch (fm_info_get_enet_if(i)) { 96 case PHY_INTERFACE_MODE_XGMII: 97 dev = miiphy_get_dev_by_name(DEFAULT_FM_TGEC_MDIO_NAME); 98 fm_info_set_mdio(i, dev); 99 break; 100 default: 101 break; 102 } 103 } 104 105 #if (CONFIG_SYS_NUM_FMAN == 2) 106 if ((srds_prtcl_s2 == 56) || (srds_prtcl_s2 == 55)) { 107 /* SGMII && XFI */ 108 fm_info_set_phy_address(FM2_DTSEC1, SGMII_PHY_ADDR5); 109 fm_info_set_phy_address(FM2_DTSEC2, SGMII_PHY_ADDR6); 110 fm_info_set_phy_address(FM2_DTSEC3, SGMII_PHY_ADDR7); 111 fm_info_set_phy_address(FM2_DTSEC4, SGMII_PHY_ADDR8); 112 fm_info_set_phy_address(FM1_10GEC1, FM1_10GEC1_PHY_ADDR); 113 fm_info_set_phy_address(FM1_10GEC2, FM1_10GEC2_PHY_ADDR); 114 fm_info_set_phy_address(FM2_10GEC1, FM2_10GEC2_PHY_ADDR); 115 fm_info_set_phy_address(FM2_10GEC2, FM2_10GEC1_PHY_ADDR); 116 } else { 117 puts("Invalid SerDes2 protocol for T4240RDB\n"); 118 } 119 120 fm_disable_port(FM2_DTSEC5); 121 fm_disable_port(FM2_DTSEC6); 122 for (i = FM2_DTSEC1; i < FM2_DTSEC1 + CONFIG_SYS_NUM_FM2_DTSEC; i++) { 123 interface = fm_info_get_enet_if(i); 124 switch (interface) { 125 case PHY_INTERFACE_MODE_SGMII: 126 dev = miiphy_get_dev_by_name(DEFAULT_FM_MDIO_NAME); 127 fm_info_set_mdio(i, dev); 128 break; 129 default: 130 break; 131 } 132 } 133 134 for (i = FM2_10GEC1; i < FM2_10GEC1 + CONFIG_SYS_NUM_FM2_10GEC; i++) { 135 switch (fm_info_get_enet_if(i)) { 136 case PHY_INTERFACE_MODE_XGMII: 137 dev = miiphy_get_dev_by_name(DEFAULT_FM_TGEC_MDIO_NAME); 138 fm_info_set_mdio(i, dev); 139 break; 140 default: 141 break; 142 } 143 } 144 #endif /* CONFIG_SYS_NUM_FMAN */ 145 146 cpu_eth_init(bis); 147 #endif /* CONFIG_FMAN_ENET */ 148 149 return pci_eth_init(bis); 150 } 151