xref: /openbmc/u-boot/board/freescale/t4rdb/ddr.h (revision ef64e782)
1 /* SPDX-License-Identifier: GPL-2.0+ */
2 /*
3  * Copyright 2014 Freescale Semiconductor, Inc.
4  */
5 
6 #ifndef __DDR_H__
7 #define __DDR_H__
8 struct board_specific_parameters {
9 	u32 n_ranks;
10 	u32 datarate_mhz_high;
11 	u32 rank_gb;
12 	u32 clk_adjust;
13 	u32 wrlvl_start;
14 	u32 wrlvl_ctl_2;
15 	u32 wrlvl_ctl_3;
16 };
17 
18 /*
19  * These tables contain all valid speeds we want to override with board
20  * specific parameters. datarate_mhz_high values need to be in ascending order
21  * for each n_ranks group.
22  */
23 static const struct board_specific_parameters udimm0[] = {
24 	/*
25 	 * memory controller 0
26 	 *   num|  hi| rank|  clk| wrlvl |   wrlvl   |  wrlvl
27 	 * ranks| mhz| GB  |adjst| start |   ctl2    |  ctl3
28 	 */
29 	{2,  1350, 4,  8,     8, 0x0809090b, 0x0c0c0d0a},
30 	{2,  1350, 0, 10,     7, 0x0709090b, 0x0c0c0d09},
31 	{2,  1666, 4,  8,     8, 0x080a0a0d, 0x0d10100b},
32 	{2,  1666, 0, 10,     7, 0x080a0a0c, 0x0d0d0e0a},
33 	{2,  1900, 0,  8,     8, 0x090a0b0e, 0x0f11120c},
34 	{2,  2140, 0,  8,     8, 0x090a0b0e, 0x0f11120c},
35 	{1,  1350, 0, 10,     8, 0x0809090b, 0x0c0c0d0a},
36 	{1,  1700, 0, 10,     8, 0x080a0a0c, 0x0c0d0e0a},
37 	{1,  1900, 0,  8,     8, 0x080a0a0c, 0x0e0e0f0a},
38 	{1,  2140, 0,  8,     8, 0x090a0b0c, 0x0e0f100b},
39 	{}
40 };
41 
42 static const struct board_specific_parameters rdimm0[] = {
43 	/*
44 	 * memory controller 0
45 	 *   num|  hi| rank|  clk| wrlvl |   wrlvl   |  wrlvl
46 	 * ranks| mhz| GB  |adjst| start |   ctl2    |  ctl3
47 	 */
48 	{4,  1350, 0, 10,     9, 0x08070605, 0x06070806},
49 	{4,  1666, 0, 10,    11, 0x0a080706, 0x07090906},
50 	{4,  2140, 0, 10,    12, 0x0b090807, 0x080a0b07},
51 	{2,  1350, 0, 10,     9, 0x08070605, 0x06070806},
52 	{2,  1666, 0, 10,    11, 0x0a090806, 0x08090a06},
53 	{2,  2140, 0, 10,    12, 0x0b090807, 0x080a0b07},
54 	{1,  1350, 0, 10,     9, 0x08070605, 0x06070806},
55 	{1,  1666, 0, 10,    11, 0x0a090806, 0x08090a06},
56 	{1,  2140, 0,  8,    12, 0x0b090807, 0x080a0b07},
57 	{}
58 };
59 
60 /*
61  * The three slots have slightly different timing. The center values are good
62  * for all slots. We use identical speed tables for them. In future use, if
63  * DIMMs require separated tables, make more entries as needed.
64  */
65 static const struct board_specific_parameters *udimms[] = {
66 	udimm0,
67 };
68 
69 /*
70  * The three slots have slightly different timing. See comments above.
71  */
72 static const struct board_specific_parameters *rdimms[] = {
73 	rdimm0,
74 };
75 
76 
77 #endif
78