1 /** 2 * Copyright 2014 Freescale Semiconductor 3 * 4 * Author: Chunhe Lan <Chunhe.Lan@freescale.com> 5 * 6 * SPDX-License-Identifier: GPL-2.0+ 7 * 8 * This file provides support for the ngPIXIS, a board-specific FPGA used on 9 * some Freescale reference boards. 10 */ 11 12 /* 13 * CPLD register set. Feel free to add board-specific #ifdefs where necessary. 14 */ 15 struct cpld_data { 16 u8 chip_id1; /* 0x00 - CPLD Chip ID1 Register */ 17 u8 chip_id2; /* 0x01 - CPLD Chip ID2 Register */ 18 u8 sw_maj_ver; /* 0x02 - CPLD Code Major Version Register */ 19 u8 sw_min_ver; /* 0x03 - CPLD Code Minor Version Register */ 20 u8 hw_ver; /* 0x04 - PCBA Version Register */ 21 u8 software_on; /* 0x05 - Override Physical Switch Enable Register */ 22 u8 cfg_rcw_src; /* 0x06 - RCW Source Location Control Register */ 23 u8 res0; /* 0x07 - not used */ 24 u8 vbank; /* 0x08 - Flash Bank Selection Control Register */ 25 u8 sw1_sysclk; /* 0x09 - SW1 Status Read Back Register */ 26 u8 sw2_status; /* 0x0a - SW2 Status Read Back Register */ 27 u8 sw3_status; /* 0x0b - SW3 Status Read Back Register */ 28 u8 sw4_status; /* 0x0c - SW4 Status Read Back Register */ 29 u8 sys_reset; /* 0x0d - Reset System With Reserving Registers Value*/ 30 u8 global_reset;/* 0x0e - Reset System With Default Registers Value */ 31 u8 res1; /* 0x0f - not used */ 32 }; 33 34 #define CPLD_BANK_SEL_MASK 0x07 35 #define CPLD_BANK_SEL_EN 0x04 36 #define CPLD_SYSTEM_RESET 0x01 37 #define CPLD_SELECT_BANK0 0x00 38 #define CPLD_SELECT_BANK4 0x04 39 #define CPLD_DEFAULT_BANK 0x01 40 41 /* Pointer to the CPLD register set */ 42 43 u8 cpld_read(unsigned int reg); 44 void cpld_write(unsigned int reg, u8 value); 45 46 #define CPLD_READ(reg) cpld_read(offsetof(struct cpld_data, reg)) 47 #define CPLD_WRITE(reg, value) \ 48 cpld_write(offsetof(struct cpld_data, reg), value) 49 50