1*83d290c5STom Rini // SPDX-License-Identifier: GPL-2.0+ 2ab06b236SChunhe Lan /** 3ab06b236SChunhe Lan * Copyright 2014 Freescale Semiconductor 4ab06b236SChunhe Lan * 5ab06b236SChunhe Lan * Author: Chunhe Lan <Chunhe.Lan@freescale.com> 6ab06b236SChunhe Lan * 7ab06b236SChunhe Lan * This file provides support for the board-specific CPLD used on some Freescale 8ab06b236SChunhe Lan * reference boards. 9ab06b236SChunhe Lan * 10ab06b236SChunhe Lan * The following macros need to be defined: 11ab06b236SChunhe Lan * 12ab06b236SChunhe Lan * CONFIG_SYS_CPLD_BASE - The virtual address of the base of the 13ab06b236SChunhe Lan * CPLD register map 14ab06b236SChunhe Lan * 15ab06b236SChunhe Lan */ 16ab06b236SChunhe Lan 17ab06b236SChunhe Lan #include <common.h> 18ab06b236SChunhe Lan #include <command.h> 19ab06b236SChunhe Lan #include <asm/io.h> 20ab06b236SChunhe Lan 21ab06b236SChunhe Lan #include "cpld.h" 22ab06b236SChunhe Lan 23ab06b236SChunhe Lan u8 cpld_read(unsigned int reg) 24ab06b236SChunhe Lan { 25ab06b236SChunhe Lan void *p = (void *)CONFIG_SYS_CPLD_BASE; 26ab06b236SChunhe Lan 27ab06b236SChunhe Lan return in_8(p + reg); 28ab06b236SChunhe Lan } 29ab06b236SChunhe Lan 30ab06b236SChunhe Lan void cpld_write(unsigned int reg, u8 value) 31ab06b236SChunhe Lan { 32ab06b236SChunhe Lan void *p = (void *)CONFIG_SYS_CPLD_BASE; 33ab06b236SChunhe Lan 34ab06b236SChunhe Lan out_8(p + reg, value); 35ab06b236SChunhe Lan } 36ab06b236SChunhe Lan 37ab06b236SChunhe Lan /** 38ab06b236SChunhe Lan * Set the boot bank to the alternate bank 39ab06b236SChunhe Lan */ 40ab06b236SChunhe Lan void cpld_set_altbank(void) 41ab06b236SChunhe Lan { 42ab06b236SChunhe Lan u8 val, curbank, altbank, override; 43ab06b236SChunhe Lan 44ab06b236SChunhe Lan val = CPLD_READ(vbank); 45ab06b236SChunhe Lan curbank = val & CPLD_BANK_SEL_MASK; 46ab06b236SChunhe Lan 47ab06b236SChunhe Lan switch (curbank) { 48ab06b236SChunhe Lan case CPLD_SELECT_BANK0: 49ab06b236SChunhe Lan case CPLD_SELECT_BANK4: 50f57709abSShaohui Xie altbank = CPLD_SELECT_BANK4; 51ab06b236SChunhe Lan CPLD_WRITE(vbank, altbank); 52ab06b236SChunhe Lan override = CPLD_READ(software_on); 53ab06b236SChunhe Lan CPLD_WRITE(software_on, override | CPLD_BANK_SEL_EN); 54ab06b236SChunhe Lan CPLD_WRITE(sys_reset, CPLD_SYSTEM_RESET); 55ab06b236SChunhe Lan break; 56ab06b236SChunhe Lan default: 57ab06b236SChunhe Lan printf("CPLD Altbank Fail: Invalid value!\n"); 58ab06b236SChunhe Lan return; 59ab06b236SChunhe Lan } 60ab06b236SChunhe Lan } 61ab06b236SChunhe Lan 62ab06b236SChunhe Lan /** 63ab06b236SChunhe Lan * Set the boot bank to the default bank 64ab06b236SChunhe Lan */ 65ab06b236SChunhe Lan void cpld_set_defbank(void) 66ab06b236SChunhe Lan { 67ab06b236SChunhe Lan u8 val; 68ab06b236SChunhe Lan 69ab06b236SChunhe Lan val = CPLD_DEFAULT_BANK; 70ab06b236SChunhe Lan 71ab06b236SChunhe Lan CPLD_WRITE(global_reset, val); 72ab06b236SChunhe Lan } 73ab06b236SChunhe Lan 74ab06b236SChunhe Lan #ifdef DEBUG 75ab06b236SChunhe Lan static void cpld_dump_regs(void) 76ab06b236SChunhe Lan { 77ab06b236SChunhe Lan printf("chip_id1 = 0x%02x\n", CPLD_READ(chip_id1)); 78ab06b236SChunhe Lan printf("chip_id2 = 0x%02x\n", CPLD_READ(chip_id2)); 79ab06b236SChunhe Lan printf("sw_maj_ver = 0x%02x\n", CPLD_READ(sw_maj_ver)); 80ab06b236SChunhe Lan printf("sw_min_ver = 0x%02x\n", CPLD_READ(sw_min_ver)); 81ab06b236SChunhe Lan printf("hw_ver = 0x%02x\n", CPLD_READ(hw_ver)); 82ab06b236SChunhe Lan printf("software_on = 0x%02x\n", CPLD_READ(software_on)); 83ab06b236SChunhe Lan printf("cfg_rcw_src = 0x%02x\n", CPLD_READ(cfg_rcw_src)); 84ab06b236SChunhe Lan printf("res0 = 0x%02x\n", CPLD_READ(res0)); 85ab06b236SChunhe Lan printf("vbank = 0x%02x\n", CPLD_READ(vbank)); 86ab06b236SChunhe Lan printf("sw1_sysclk = 0x%02x\n", CPLD_READ(sw1_sysclk)); 87ab06b236SChunhe Lan printf("sw2_status = 0x%02x\n", CPLD_READ(sw2_status)); 88ab06b236SChunhe Lan printf("sw3_status = 0x%02x\n", CPLD_READ(sw3_status)); 89ab06b236SChunhe Lan printf("sw4_status = 0x%02x\n", CPLD_READ(sw4_status)); 90ab06b236SChunhe Lan printf("sys_reset = 0x%02x\n", CPLD_READ(sys_reset)); 91ab06b236SChunhe Lan printf("global_reset = 0x%02x\n", CPLD_READ(global_reset)); 92ab06b236SChunhe Lan printf("res1 = 0x%02x\n", CPLD_READ(res1)); 93ab06b236SChunhe Lan putc('\n'); 94ab06b236SChunhe Lan } 95ab06b236SChunhe Lan #endif 96ab06b236SChunhe Lan 97ab06b236SChunhe Lan #ifndef CONFIG_SPL_BUILD 98ab06b236SChunhe Lan int do_cpld(cmd_tbl_t *cmdtp, int flag, int argc, char * const argv[]) 99ab06b236SChunhe Lan { 100ab06b236SChunhe Lan int rc = 0; 101ab06b236SChunhe Lan 102ab06b236SChunhe Lan if (argc <= 1) 103ab06b236SChunhe Lan return cmd_usage(cmdtp); 104ab06b236SChunhe Lan 105ab06b236SChunhe Lan if (strcmp(argv[1], "reset") == 0) { 106ab06b236SChunhe Lan if (strcmp(argv[2], "altbank") == 0) 107ab06b236SChunhe Lan cpld_set_altbank(); 108ab06b236SChunhe Lan else 109ab06b236SChunhe Lan cpld_set_defbank(); 110ab06b236SChunhe Lan #ifdef DEBUG 111ab06b236SChunhe Lan } else if (strcmp(argv[1], "dump") == 0) { 112ab06b236SChunhe Lan cpld_dump_regs(); 113ab06b236SChunhe Lan #endif 114ab06b236SChunhe Lan } else 115ab06b236SChunhe Lan rc = cmd_usage(cmdtp); 116ab06b236SChunhe Lan 117ab06b236SChunhe Lan return rc; 118ab06b236SChunhe Lan } 119ab06b236SChunhe Lan 120ab06b236SChunhe Lan U_BOOT_CMD( 121ab06b236SChunhe Lan cpld, CONFIG_SYS_MAXARGS, 1, do_cpld, 122ab06b236SChunhe Lan "Reset the board or alternate bank", 123ab06b236SChunhe Lan "reset - reset to default bank\n" 124ab06b236SChunhe Lan "cpld reset altbank - reset to alternate bank\n" 125ab06b236SChunhe Lan #ifdef DEBUG 126ab06b236SChunhe Lan "cpld dump - display the CPLD registers\n" 127ab06b236SChunhe Lan #endif 128ab06b236SChunhe Lan ); 129ab06b236SChunhe Lan #endif 130