1 /* 2 * Copyright 2008-2012 Freescale Semiconductor, Inc. 3 * 4 * (C) Copyright 2000 5 * Wolfgang Denk, DENX Software Engineering, wd@denx.de. 6 * 7 * See file CREDITS for list of people who contributed to this 8 * project. 9 * 10 * This program is free software; you can redistribute it and/or 11 * modify it under the terms of the GNU General Public License as 12 * published by the Free Software Foundation; either version 2 of 13 * the License, or (at your option) any later version. 14 * 15 * This program is distributed in the hope that it will be useful, 16 * but WITHOUT ANY WARRANTY; without even the implied warranty of 17 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the 18 * GNU General Public License for more details. 19 * 20 * You should have received a copy of the GNU General Public License 21 * along with this program; if not, write to the Free Software 22 * Foundation, Inc., 59 Temple Place, Suite 330, Boston, 23 * MA 02111-1307 USA 24 */ 25 26 #include <common.h> 27 #include <asm/mmu.h> 28 29 struct fsl_e_tlb_entry tlb_table[] = { 30 /* TLB 0 - for temp stack in cache */ 31 SET_TLB_ENTRY(0, CONFIG_SYS_INIT_RAM_ADDR, 32 CONFIG_SYS_INIT_RAM_ADDR_PHYS, 33 MAS3_SX|MAS3_SW|MAS3_SR, 0, 34 0, 0, BOOKE_PAGESZ_4K, 0), 35 SET_TLB_ENTRY(0, CONFIG_SYS_INIT_RAM_ADDR + 4 * 1024, 36 CONFIG_SYS_INIT_RAM_ADDR_PHYS + 4 * 1024, 37 MAS3_SX|MAS3_SW|MAS3_SR, 0, 38 0, 0, BOOKE_PAGESZ_4K, 0), 39 SET_TLB_ENTRY(0, CONFIG_SYS_INIT_RAM_ADDR + 8 * 1024, 40 CONFIG_SYS_INIT_RAM_ADDR_PHYS + 8 * 1024, 41 MAS3_SX|MAS3_SW|MAS3_SR, 0, 42 0, 0, BOOKE_PAGESZ_4K, 0), 43 SET_TLB_ENTRY(0, CONFIG_SYS_INIT_RAM_ADDR + 12 * 1024, 44 CONFIG_SYS_INIT_RAM_ADDR_PHYS + 12 * 1024, 45 MAS3_SX|MAS3_SW|MAS3_SR, 0, 46 0, 0, BOOKE_PAGESZ_4K, 0), 47 48 /* TLB 1 */ 49 /* *I*** - Covers boot page */ 50 #if defined(CONFIG_SYS_RAMBOOT) && defined(CONFIG_SYS_INIT_L3_ADDR) 51 /* 52 * *I*G - L3SRAM. When L3 is used as 1M SRAM, the address of the 53 * SRAM is at 0xfff00000, it covered the 0xfffff000. 54 */ 55 SET_TLB_ENTRY(1, CONFIG_SYS_INIT_L3_ADDR, CONFIG_SYS_INIT_L3_ADDR, 56 MAS3_SX|MAS3_SW|MAS3_SR, MAS2_I|MAS2_G, 57 0, 0, BOOKE_PAGESZ_1M, 1), 58 #elif defined(CONFIG_SRIO_PCIE_BOOT_SLAVE) 59 /* 60 * SRIO_PCIE_BOOT-SLAVE. When slave boot, the address of the 61 * space is at 0xfff00000, it covered the 0xfffff000. 62 */ 63 SET_TLB_ENTRY(1, CONFIG_SYS_SRIO_PCIE_BOOT_SLAVE_ADDR, 64 CONFIG_SYS_SRIO_PCIE_BOOT_SLAVE_ADDR_PHYS, 65 MAS3_SX|MAS3_SW|MAS3_SR, MAS2_W|MAS2_G, 66 0, 0, BOOKE_PAGESZ_1M, 1), 67 #else 68 SET_TLB_ENTRY(1, 0xfffff000, 0xfffff000, 69 MAS3_SX|MAS3_SW|MAS3_SR, MAS2_I|MAS2_G, 70 0, 0, BOOKE_PAGESZ_4K, 1), 71 #endif 72 73 /* *I*G* - CCSRBAR */ 74 SET_TLB_ENTRY(1, CONFIG_SYS_CCSRBAR, CONFIG_SYS_CCSRBAR_PHYS, 75 MAS3_SX|MAS3_SW|MAS3_SR, MAS2_I|MAS2_G, 76 0, 1, BOOKE_PAGESZ_16M, 1), 77 78 /* *I*G* - Flash, localbus */ 79 /* This will be changed to *I*G* after relocation to RAM. */ 80 SET_TLB_ENTRY(1, CONFIG_SYS_FLASH_BASE, CONFIG_SYS_FLASH_BASE_PHYS, 81 MAS3_SX|MAS3_SR, MAS2_W|MAS2_G, 82 0, 2, BOOKE_PAGESZ_256M, 1), 83 84 /* *I*G* - PCI */ 85 SET_TLB_ENTRY(1, CONFIG_SYS_PCIE1_MEM_VIRT, CONFIG_SYS_PCIE1_MEM_PHYS, 86 MAS3_SX|MAS3_SW|MAS3_SR, MAS2_I|MAS2_G, 87 0, 3, BOOKE_PAGESZ_1G, 1), 88 89 /* *I*G* - PCI */ 90 SET_TLB_ENTRY(1, CONFIG_SYS_PCIE1_MEM_VIRT + 0x40000000, 91 CONFIG_SYS_PCIE1_MEM_PHYS + 0x40000000, 92 MAS3_SX|MAS3_SW|MAS3_SR, MAS2_I|MAS2_G, 93 0, 4, BOOKE_PAGESZ_256M, 1), 94 95 SET_TLB_ENTRY(1, CONFIG_SYS_PCIE1_MEM_VIRT + 0x50000000, 96 CONFIG_SYS_PCIE1_MEM_PHYS + 0x50000000, 97 MAS3_SX|MAS3_SW|MAS3_SR, MAS2_I|MAS2_G, 98 0, 5, BOOKE_PAGESZ_256M, 1), 99 100 /* *I*G* - PCI I/O */ 101 SET_TLB_ENTRY(1, CONFIG_SYS_PCIE1_IO_VIRT, CONFIG_SYS_PCIE1_IO_PHYS, 102 MAS3_SX|MAS3_SW|MAS3_SR, MAS2_I|MAS2_G, 103 0, 6, BOOKE_PAGESZ_256K, 1), 104 105 /* Bman/Qman */ 106 #ifdef CONFIG_SYS_BMAN_MEM_PHYS 107 SET_TLB_ENTRY(1, CONFIG_SYS_BMAN_MEM_BASE, CONFIG_SYS_BMAN_MEM_PHYS, 108 MAS3_SX|MAS3_SW|MAS3_SR, 0, 109 0, 9, BOOKE_PAGESZ_16M, 1), 110 SET_TLB_ENTRY(1, CONFIG_SYS_BMAN_MEM_BASE + 0x01000000, 111 CONFIG_SYS_BMAN_MEM_PHYS + 0x01000000, 112 MAS3_SX|MAS3_SW|MAS3_SR, MAS2_I|MAS2_G, 113 0, 10, BOOKE_PAGESZ_16M, 1), 114 #endif 115 #ifdef CONFIG_SYS_QMAN_MEM_PHYS 116 SET_TLB_ENTRY(1, CONFIG_SYS_QMAN_MEM_BASE, CONFIG_SYS_QMAN_MEM_PHYS, 117 MAS3_SX|MAS3_SW|MAS3_SR, 0, 118 0, 11, BOOKE_PAGESZ_16M, 1), 119 SET_TLB_ENTRY(1, CONFIG_SYS_QMAN_MEM_BASE + 0x01000000, 120 CONFIG_SYS_QMAN_MEM_PHYS + 0x01000000, 121 MAS3_SX|MAS3_SW|MAS3_SR, MAS2_I|MAS2_G, 122 0, 12, BOOKE_PAGESZ_16M, 1), 123 #endif 124 #ifdef CONFIG_SYS_DCSRBAR_PHYS 125 SET_TLB_ENTRY(1, CONFIG_SYS_DCSRBAR, CONFIG_SYS_DCSRBAR_PHYS, 126 MAS3_SX|MAS3_SW|MAS3_SR, MAS2_I|MAS2_G, 127 0, 13, BOOKE_PAGESZ_32M, 1), 128 #endif 129 #ifdef CONFIG_SYS_NAND_BASE 130 /* 131 * *I*G - NAND 132 * entry 14 and 15 has been used hard coded, they will be disabled 133 * in cpu_init_f, so we use entry 16 for nand. 134 */ 135 SET_TLB_ENTRY(1, CONFIG_SYS_NAND_BASE, CONFIG_SYS_NAND_BASE_PHYS, 136 MAS3_SX|MAS3_SW|MAS3_SR, MAS2_I|MAS2_G, 137 0, 16, BOOKE_PAGESZ_64K, 1), 138 #endif 139 SET_TLB_ENTRY(1, QIXIS_BASE, QIXIS_BASE_PHYS, 140 MAS3_SX|MAS3_SW|MAS3_SR, MAS2_I|MAS2_G, 141 0, 17, BOOKE_PAGESZ_4K, 1), 142 #ifdef CONFIG_SRIO_PCIE_BOOT_SLAVE 143 /* 144 * SRIO_PCIE_BOOT-SLAVE. 1M space from 0xffe00000 for 145 * fetching ucode and ENV from master 146 */ 147 SET_TLB_ENTRY(1, CONFIG_SYS_SRIO_PCIE_BOOT_UCODE_ENV_ADDR, 148 CONFIG_SYS_SRIO_PCIE_BOOT_UCODE_ENV_ADDR_PHYS, 149 MAS3_SX|MAS3_SW|MAS3_SR, MAS2_G, 150 0, 18, BOOKE_PAGESZ_1M, 1), 151 #endif 152 153 }; 154 155 int num_tlb_entries = ARRAY_SIZE(tlb_table); 156