1 /* 2 * Copyright 2008-2012 Freescale Semiconductor, Inc. 3 * 4 * (C) Copyright 2000 5 * Wolfgang Denk, DENX Software Engineering, wd@denx.de. 6 * 7 * See file CREDITS for list of people who contributed to this 8 * project. 9 * 10 * This program is free software; you can redistribute it and/or 11 * modify it under the terms of the GNU General Public License as 12 * published by the Free Software Foundation; either version 2 of 13 * the License, or (at your option) any later version. 14 * 15 * This program is distributed in the hope that it will be useful, 16 * but WITHOUT ANY WARRANTY; without even the implied warranty of 17 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the 18 * GNU General Public License for more details. 19 * 20 * You should have received a copy of the GNU General Public License 21 * along with this program; if not, write to the Free Software 22 * Foundation, Inc., 59 Temple Place, Suite 330, Boston, 23 * MA 02111-1307 USA 24 */ 25 26 #include <common.h> 27 #include <asm/mmu.h> 28 29 struct fsl_e_tlb_entry tlb_table[] = { 30 /* TLB 0 - for temp stack in cache */ 31 SET_TLB_ENTRY(0, CONFIG_SYS_INIT_RAM_ADDR, 32 CONFIG_SYS_INIT_RAM_ADDR_PHYS, 33 MAS3_SX|MAS3_SW|MAS3_SR, 0, 34 0, 0, BOOKE_PAGESZ_4K, 0), 35 SET_TLB_ENTRY(0, CONFIG_SYS_INIT_RAM_ADDR + 4 * 1024, 36 CONFIG_SYS_INIT_RAM_ADDR_PHYS + 4 * 1024, 37 MAS3_SX|MAS3_SW|MAS3_SR, 0, 38 0, 0, BOOKE_PAGESZ_4K, 0), 39 SET_TLB_ENTRY(0, CONFIG_SYS_INIT_RAM_ADDR + 8 * 1024, 40 CONFIG_SYS_INIT_RAM_ADDR_PHYS + 8 * 1024, 41 MAS3_SX|MAS3_SW|MAS3_SR, 0, 42 0, 0, BOOKE_PAGESZ_4K, 0), 43 SET_TLB_ENTRY(0, CONFIG_SYS_INIT_RAM_ADDR + 12 * 1024, 44 CONFIG_SYS_INIT_RAM_ADDR_PHYS + 12 * 1024, 45 MAS3_SX|MAS3_SW|MAS3_SR, 0, 46 0, 0, BOOKE_PAGESZ_4K, 0), 47 48 /* TLB 1 */ 49 /* *I*** - Covers boot page */ 50 #if defined(CONFIG_SYS_RAMBOOT) && defined(CONFIG_SYS_INIT_L3_ADDR) 51 /* 52 * *I*G - L3SRAM. When L3 is used as 1M SRAM, the address of the 53 * SRAM is at 0xfff00000, it covered the 0xfffff000. 54 */ 55 SET_TLB_ENTRY(1, CONFIG_SYS_INIT_L3_ADDR, CONFIG_SYS_INIT_L3_ADDR, 56 MAS3_SX|MAS3_SW|MAS3_SR, MAS2_I|MAS2_G, 57 0, 0, BOOKE_PAGESZ_1M, 1), 58 #else 59 SET_TLB_ENTRY(1, 0xfffff000, 0xfffff000, 60 MAS3_SX|MAS3_SW|MAS3_SR, MAS2_I|MAS2_G, 61 0, 0, BOOKE_PAGESZ_4K, 1), 62 #endif 63 64 /* *I*G* - CCSRBAR */ 65 SET_TLB_ENTRY(1, CONFIG_SYS_CCSRBAR, CONFIG_SYS_CCSRBAR_PHYS, 66 MAS3_SX|MAS3_SW|MAS3_SR, MAS2_I|MAS2_G, 67 0, 1, BOOKE_PAGESZ_16M, 1), 68 69 /* *I*G* - Flash, localbus */ 70 /* This will be changed to *I*G* after relocation to RAM. */ 71 SET_TLB_ENTRY(1, CONFIG_SYS_FLASH_BASE, CONFIG_SYS_FLASH_BASE_PHYS, 72 MAS3_SX|MAS3_SR, MAS2_W|MAS2_G, 73 0, 2, BOOKE_PAGESZ_256M, 1), 74 75 /* *I*G* - PCI */ 76 SET_TLB_ENTRY(1, CONFIG_SYS_PCIE1_MEM_VIRT, CONFIG_SYS_PCIE1_MEM_PHYS, 77 MAS3_SX|MAS3_SW|MAS3_SR, MAS2_I|MAS2_G, 78 0, 3, BOOKE_PAGESZ_1G, 1), 79 80 /* *I*G* - PCI */ 81 SET_TLB_ENTRY(1, CONFIG_SYS_PCIE1_MEM_VIRT + 0x40000000, 82 CONFIG_SYS_PCIE1_MEM_PHYS + 0x40000000, 83 MAS3_SX|MAS3_SW|MAS3_SR, MAS2_I|MAS2_G, 84 0, 4, BOOKE_PAGESZ_256M, 1), 85 86 SET_TLB_ENTRY(1, CONFIG_SYS_PCIE1_MEM_VIRT + 0x50000000, 87 CONFIG_SYS_PCIE1_MEM_PHYS + 0x50000000, 88 MAS3_SX|MAS3_SW|MAS3_SR, MAS2_I|MAS2_G, 89 0, 5, BOOKE_PAGESZ_256M, 1), 90 91 /* *I*G* - PCI I/O */ 92 SET_TLB_ENTRY(1, CONFIG_SYS_PCIE1_IO_VIRT, CONFIG_SYS_PCIE1_IO_PHYS, 93 MAS3_SX|MAS3_SW|MAS3_SR, MAS2_I|MAS2_G, 94 0, 6, BOOKE_PAGESZ_256K, 1), 95 96 /* Bman/Qman */ 97 #ifdef CONFIG_SYS_BMAN_MEM_PHYS 98 SET_TLB_ENTRY(1, CONFIG_SYS_BMAN_MEM_BASE, CONFIG_SYS_BMAN_MEM_PHYS, 99 MAS3_SX|MAS3_SW|MAS3_SR, 0, 100 0, 9, BOOKE_PAGESZ_16M, 1), 101 SET_TLB_ENTRY(1, CONFIG_SYS_BMAN_MEM_BASE + 0x01000000, 102 CONFIG_SYS_BMAN_MEM_PHYS + 0x01000000, 103 MAS3_SX|MAS3_SW|MAS3_SR, MAS2_I|MAS2_G, 104 0, 10, BOOKE_PAGESZ_16M, 1), 105 #endif 106 #ifdef CONFIG_SYS_QMAN_MEM_PHYS 107 SET_TLB_ENTRY(1, CONFIG_SYS_QMAN_MEM_BASE, CONFIG_SYS_QMAN_MEM_PHYS, 108 MAS3_SX|MAS3_SW|MAS3_SR, 0, 109 0, 11, BOOKE_PAGESZ_16M, 1), 110 SET_TLB_ENTRY(1, CONFIG_SYS_QMAN_MEM_BASE + 0x01000000, 111 CONFIG_SYS_QMAN_MEM_PHYS + 0x01000000, 112 MAS3_SX|MAS3_SW|MAS3_SR, MAS2_I|MAS2_G, 113 0, 12, BOOKE_PAGESZ_16M, 1), 114 #endif 115 #ifdef CONFIG_SYS_DCSRBAR_PHYS 116 SET_TLB_ENTRY(1, CONFIG_SYS_DCSRBAR, CONFIG_SYS_DCSRBAR_PHYS, 117 MAS3_SX|MAS3_SW|MAS3_SR, MAS2_I|MAS2_G, 118 0, 13, BOOKE_PAGESZ_4M, 1), 119 #endif 120 #ifdef CONFIG_SYS_NAND_BASE 121 /* 122 * *I*G - NAND 123 * entry 14 and 15 has been used hard coded, they will be disabled 124 * in cpu_init_f, so we use entry 16 for nand. 125 */ 126 SET_TLB_ENTRY(1, CONFIG_SYS_NAND_BASE, CONFIG_SYS_NAND_BASE_PHYS, 127 MAS3_SX|MAS3_SW|MAS3_SR, MAS2_I|MAS2_G, 128 0, 16, BOOKE_PAGESZ_64K, 1), 129 #endif 130 SET_TLB_ENTRY(1, QIXIS_BASE, QIXIS_BASE_PHYS, 131 MAS3_SX|MAS3_SW|MAS3_SR, MAS2_I|MAS2_G, 132 0, 17, BOOKE_PAGESZ_4K, 1), 133 134 }; 135 136 int num_tlb_entries = ARRAY_SIZE(tlb_table); 137