1*ee52b188SYork Sun /* 2*ee52b188SYork Sun * Copyright 2008-2012 Freescale Semiconductor, Inc. 3*ee52b188SYork Sun * 4*ee52b188SYork Sun * (C) Copyright 2000 5*ee52b188SYork Sun * Wolfgang Denk, DENX Software Engineering, wd@denx.de. 6*ee52b188SYork Sun * 7*ee52b188SYork Sun * See file CREDITS for list of people who contributed to this 8*ee52b188SYork Sun * project. 9*ee52b188SYork Sun * 10*ee52b188SYork Sun * This program is free software; you can redistribute it and/or 11*ee52b188SYork Sun * modify it under the terms of the GNU General Public License as 12*ee52b188SYork Sun * published by the Free Software Foundation; either version 2 of 13*ee52b188SYork Sun * the License, or (at your option) any later version. 14*ee52b188SYork Sun * 15*ee52b188SYork Sun * This program is distributed in the hope that it will be useful, 16*ee52b188SYork Sun * but WITHOUT ANY WARRANTY; without even the implied warranty of 17*ee52b188SYork Sun * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the 18*ee52b188SYork Sun * GNU General Public License for more details. 19*ee52b188SYork Sun * 20*ee52b188SYork Sun * You should have received a copy of the GNU General Public License 21*ee52b188SYork Sun * along with this program; if not, write to the Free Software 22*ee52b188SYork Sun * Foundation, Inc., 59 Temple Place, Suite 330, Boston, 23*ee52b188SYork Sun * MA 02111-1307 USA 24*ee52b188SYork Sun */ 25*ee52b188SYork Sun 26*ee52b188SYork Sun #include <common.h> 27*ee52b188SYork Sun #include <asm/mmu.h> 28*ee52b188SYork Sun 29*ee52b188SYork Sun struct fsl_e_tlb_entry tlb_table[] = { 30*ee52b188SYork Sun /* TLB 0 - for temp stack in cache */ 31*ee52b188SYork Sun SET_TLB_ENTRY(0, CONFIG_SYS_INIT_RAM_ADDR, 32*ee52b188SYork Sun CONFIG_SYS_INIT_RAM_ADDR_PHYS, 33*ee52b188SYork Sun MAS3_SX|MAS3_SW|MAS3_SR, 0, 34*ee52b188SYork Sun 0, 0, BOOKE_PAGESZ_4K, 0), 35*ee52b188SYork Sun SET_TLB_ENTRY(0, CONFIG_SYS_INIT_RAM_ADDR + 4 * 1024, 36*ee52b188SYork Sun CONFIG_SYS_INIT_RAM_ADDR_PHYS + 4 * 1024, 37*ee52b188SYork Sun MAS3_SX|MAS3_SW|MAS3_SR, 0, 38*ee52b188SYork Sun 0, 0, BOOKE_PAGESZ_4K, 0), 39*ee52b188SYork Sun SET_TLB_ENTRY(0, CONFIG_SYS_INIT_RAM_ADDR + 8 * 1024, 40*ee52b188SYork Sun CONFIG_SYS_INIT_RAM_ADDR_PHYS + 8 * 1024, 41*ee52b188SYork Sun MAS3_SX|MAS3_SW|MAS3_SR, 0, 42*ee52b188SYork Sun 0, 0, BOOKE_PAGESZ_4K, 0), 43*ee52b188SYork Sun SET_TLB_ENTRY(0, CONFIG_SYS_INIT_RAM_ADDR + 12 * 1024, 44*ee52b188SYork Sun CONFIG_SYS_INIT_RAM_ADDR_PHYS + 12 * 1024, 45*ee52b188SYork Sun MAS3_SX|MAS3_SW|MAS3_SR, 0, 46*ee52b188SYork Sun 0, 0, BOOKE_PAGESZ_4K, 0), 47*ee52b188SYork Sun 48*ee52b188SYork Sun /* TLB 1 */ 49*ee52b188SYork Sun /* *I*** - Covers boot page */ 50*ee52b188SYork Sun #if defined(CONFIG_SYS_RAMBOOT) && defined(CONFIG_SYS_INIT_L3_ADDR) 51*ee52b188SYork Sun /* 52*ee52b188SYork Sun * *I*G - L3SRAM. When L3 is used as 1M SRAM, the address of the 53*ee52b188SYork Sun * SRAM is at 0xfff00000, it covered the 0xfffff000. 54*ee52b188SYork Sun */ 55*ee52b188SYork Sun SET_TLB_ENTRY(1, CONFIG_SYS_INIT_L3_ADDR, CONFIG_SYS_INIT_L3_ADDR, 56*ee52b188SYork Sun MAS3_SX|MAS3_SW|MAS3_SR, MAS2_I|MAS2_G, 57*ee52b188SYork Sun 0, 0, BOOKE_PAGESZ_1M, 1), 58*ee52b188SYork Sun #else 59*ee52b188SYork Sun SET_TLB_ENTRY(1, 0xfffff000, 0xfffff000, 60*ee52b188SYork Sun MAS3_SX|MAS3_SW|MAS3_SR, MAS2_I|MAS2_G, 61*ee52b188SYork Sun 0, 0, BOOKE_PAGESZ_4K, 1), 62*ee52b188SYork Sun #endif 63*ee52b188SYork Sun 64*ee52b188SYork Sun /* *I*G* - CCSRBAR */ 65*ee52b188SYork Sun SET_TLB_ENTRY(1, CONFIG_SYS_CCSRBAR, CONFIG_SYS_CCSRBAR_PHYS, 66*ee52b188SYork Sun MAS3_SX|MAS3_SW|MAS3_SR, MAS2_I|MAS2_G, 67*ee52b188SYork Sun 0, 1, BOOKE_PAGESZ_16M, 1), 68*ee52b188SYork Sun 69*ee52b188SYork Sun /* *I*G* - Flash, localbus */ 70*ee52b188SYork Sun /* This will be changed to *I*G* after relocation to RAM. */ 71*ee52b188SYork Sun SET_TLB_ENTRY(1, CONFIG_SYS_FLASH_BASE, CONFIG_SYS_FLASH_BASE_PHYS, 72*ee52b188SYork Sun MAS3_SX|MAS3_SR, MAS2_W|MAS2_G, 73*ee52b188SYork Sun 0, 2, BOOKE_PAGESZ_256M, 1), 74*ee52b188SYork Sun 75*ee52b188SYork Sun /* *I*G* - PCI */ 76*ee52b188SYork Sun SET_TLB_ENTRY(1, CONFIG_SYS_PCIE1_MEM_VIRT, CONFIG_SYS_PCIE1_MEM_PHYS, 77*ee52b188SYork Sun MAS3_SX|MAS3_SW|MAS3_SR, MAS2_I|MAS2_G, 78*ee52b188SYork Sun 0, 3, BOOKE_PAGESZ_1G, 1), 79*ee52b188SYork Sun 80*ee52b188SYork Sun /* *I*G* - PCI */ 81*ee52b188SYork Sun SET_TLB_ENTRY(1, CONFIG_SYS_PCIE1_MEM_VIRT + 0x40000000, 82*ee52b188SYork Sun CONFIG_SYS_PCIE1_MEM_PHYS + 0x40000000, 83*ee52b188SYork Sun MAS3_SX|MAS3_SW|MAS3_SR, MAS2_I|MAS2_G, 84*ee52b188SYork Sun 0, 4, BOOKE_PAGESZ_256M, 1), 85*ee52b188SYork Sun 86*ee52b188SYork Sun SET_TLB_ENTRY(1, CONFIG_SYS_PCIE1_MEM_VIRT + 0x50000000, 87*ee52b188SYork Sun CONFIG_SYS_PCIE1_MEM_PHYS + 0x50000000, 88*ee52b188SYork Sun MAS3_SX|MAS3_SW|MAS3_SR, MAS2_I|MAS2_G, 89*ee52b188SYork Sun 0, 5, BOOKE_PAGESZ_256M, 1), 90*ee52b188SYork Sun 91*ee52b188SYork Sun /* *I*G* - PCI I/O */ 92*ee52b188SYork Sun SET_TLB_ENTRY(1, CONFIG_SYS_PCIE1_IO_VIRT, CONFIG_SYS_PCIE1_IO_PHYS, 93*ee52b188SYork Sun MAS3_SX|MAS3_SW|MAS3_SR, MAS2_I|MAS2_G, 94*ee52b188SYork Sun 0, 6, BOOKE_PAGESZ_256K, 1), 95*ee52b188SYork Sun 96*ee52b188SYork Sun /* Bman/Qman */ 97*ee52b188SYork Sun #ifdef CONFIG_SYS_BMAN_MEM_PHYS 98*ee52b188SYork Sun SET_TLB_ENTRY(1, CONFIG_SYS_BMAN_MEM_BASE, CONFIG_SYS_BMAN_MEM_PHYS, 99*ee52b188SYork Sun MAS3_SX|MAS3_SW|MAS3_SR, 0, 100*ee52b188SYork Sun 0, 9, BOOKE_PAGESZ_16M, 1), 101*ee52b188SYork Sun SET_TLB_ENTRY(1, CONFIG_SYS_BMAN_MEM_BASE + 0x01000000, 102*ee52b188SYork Sun CONFIG_SYS_BMAN_MEM_PHYS + 0x01000000, 103*ee52b188SYork Sun MAS3_SX|MAS3_SW|MAS3_SR, MAS2_I|MAS2_G, 104*ee52b188SYork Sun 0, 10, BOOKE_PAGESZ_16M, 1), 105*ee52b188SYork Sun #endif 106*ee52b188SYork Sun #ifdef CONFIG_SYS_QMAN_MEM_PHYS 107*ee52b188SYork Sun SET_TLB_ENTRY(1, CONFIG_SYS_QMAN_MEM_BASE, CONFIG_SYS_QMAN_MEM_PHYS, 108*ee52b188SYork Sun MAS3_SX|MAS3_SW|MAS3_SR, 0, 109*ee52b188SYork Sun 0, 11, BOOKE_PAGESZ_16M, 1), 110*ee52b188SYork Sun SET_TLB_ENTRY(1, CONFIG_SYS_QMAN_MEM_BASE + 0x01000000, 111*ee52b188SYork Sun CONFIG_SYS_QMAN_MEM_PHYS + 0x01000000, 112*ee52b188SYork Sun MAS3_SX|MAS3_SW|MAS3_SR, MAS2_I|MAS2_G, 113*ee52b188SYork Sun 0, 12, BOOKE_PAGESZ_16M, 1), 114*ee52b188SYork Sun #endif 115*ee52b188SYork Sun #ifdef CONFIG_SYS_DCSRBAR_PHYS 116*ee52b188SYork Sun SET_TLB_ENTRY(1, CONFIG_SYS_DCSRBAR, CONFIG_SYS_DCSRBAR_PHYS, 117*ee52b188SYork Sun MAS3_SX|MAS3_SW|MAS3_SR, MAS2_I|MAS2_G, 118*ee52b188SYork Sun 0, 13, BOOKE_PAGESZ_4M, 1), 119*ee52b188SYork Sun #endif 120*ee52b188SYork Sun #ifdef CONFIG_SYS_NAND_BASE 121*ee52b188SYork Sun /* 122*ee52b188SYork Sun * *I*G - NAND 123*ee52b188SYork Sun * entry 14 and 15 has been used hard coded, they will be disabled 124*ee52b188SYork Sun * in cpu_init_f, so we use entry 16 for nand. 125*ee52b188SYork Sun */ 126*ee52b188SYork Sun SET_TLB_ENTRY(1, CONFIG_SYS_NAND_BASE, CONFIG_SYS_NAND_BASE_PHYS, 127*ee52b188SYork Sun MAS3_SX|MAS3_SW|MAS3_SR, MAS2_I|MAS2_G, 128*ee52b188SYork Sun 0, 16, BOOKE_PAGESZ_1M, 1), 129*ee52b188SYork Sun #endif 130*ee52b188SYork Sun SET_TLB_ENTRY(1, QIXIS_BASE, QIXIS_BASE_PHYS, 131*ee52b188SYork Sun MAS3_SX|MAS3_SW|MAS3_SR, MAS2_I|MAS2_G, 132*ee52b188SYork Sun 0, 17, BOOKE_PAGESZ_4K, 1), 133*ee52b188SYork Sun 134*ee52b188SYork Sun }; 135*ee52b188SYork Sun 136*ee52b188SYork Sun int num_tlb_entries = ARRAY_SIZE(tlb_table); 137