1ee52b188SYork Sun /* 2ee52b188SYork Sun * Copyright 2008-2012 Freescale Semiconductor, Inc. 3ee52b188SYork Sun * 4ee52b188SYork Sun * (C) Copyright 2000 5ee52b188SYork Sun * Wolfgang Denk, DENX Software Engineering, wd@denx.de. 6ee52b188SYork Sun * 71a459660SWolfgang Denk * SPDX-License-Identifier: GPL-2.0+ 8ee52b188SYork Sun */ 9ee52b188SYork Sun 10ee52b188SYork Sun #include <common.h> 11ee52b188SYork Sun #include <asm/mmu.h> 12ee52b188SYork Sun 13ee52b188SYork Sun struct fsl_e_tlb_entry tlb_table[] = { 14ee52b188SYork Sun /* TLB 0 - for temp stack in cache */ 15ee52b188SYork Sun SET_TLB_ENTRY(0, CONFIG_SYS_INIT_RAM_ADDR, 16ee52b188SYork Sun CONFIG_SYS_INIT_RAM_ADDR_PHYS, 17ee52b188SYork Sun MAS3_SX|MAS3_SW|MAS3_SR, 0, 18ee52b188SYork Sun 0, 0, BOOKE_PAGESZ_4K, 0), 19ee52b188SYork Sun SET_TLB_ENTRY(0, CONFIG_SYS_INIT_RAM_ADDR + 4 * 1024, 20ee52b188SYork Sun CONFIG_SYS_INIT_RAM_ADDR_PHYS + 4 * 1024, 21ee52b188SYork Sun MAS3_SX|MAS3_SW|MAS3_SR, 0, 22ee52b188SYork Sun 0, 0, BOOKE_PAGESZ_4K, 0), 23ee52b188SYork Sun SET_TLB_ENTRY(0, CONFIG_SYS_INIT_RAM_ADDR + 8 * 1024, 24ee52b188SYork Sun CONFIG_SYS_INIT_RAM_ADDR_PHYS + 8 * 1024, 25ee52b188SYork Sun MAS3_SX|MAS3_SW|MAS3_SR, 0, 26ee52b188SYork Sun 0, 0, BOOKE_PAGESZ_4K, 0), 27ee52b188SYork Sun SET_TLB_ENTRY(0, CONFIG_SYS_INIT_RAM_ADDR + 12 * 1024, 28ee52b188SYork Sun CONFIG_SYS_INIT_RAM_ADDR_PHYS + 12 * 1024, 29ee52b188SYork Sun MAS3_SX|MAS3_SW|MAS3_SR, 0, 30ee52b188SYork Sun 0, 0, BOOKE_PAGESZ_4K, 0), 31ee52b188SYork Sun 32ee52b188SYork Sun /* TLB 1 */ 33ee52b188SYork Sun /* *I*** - Covers boot page */ 34ee52b188SYork Sun #if defined(CONFIG_SYS_RAMBOOT) && defined(CONFIG_SYS_INIT_L3_ADDR) 35ee52b188SYork Sun /* 36ee52b188SYork Sun * *I*G - L3SRAM. When L3 is used as 1M SRAM, the address of the 37ee52b188SYork Sun * SRAM is at 0xfff00000, it covered the 0xfffff000. 38ee52b188SYork Sun */ 39ee52b188SYork Sun SET_TLB_ENTRY(1, CONFIG_SYS_INIT_L3_ADDR, CONFIG_SYS_INIT_L3_ADDR, 40ee52b188SYork Sun MAS3_SX|MAS3_SW|MAS3_SR, MAS2_I|MAS2_G, 41ee52b188SYork Sun 0, 0, BOOKE_PAGESZ_1M, 1), 4269fdf900SLiu Gang #elif defined(CONFIG_SRIO_PCIE_BOOT_SLAVE) 4369fdf900SLiu Gang /* 4469fdf900SLiu Gang * SRIO_PCIE_BOOT-SLAVE. When slave boot, the address of the 4569fdf900SLiu Gang * space is at 0xfff00000, it covered the 0xfffff000. 4669fdf900SLiu Gang */ 4769fdf900SLiu Gang SET_TLB_ENTRY(1, CONFIG_SYS_SRIO_PCIE_BOOT_SLAVE_ADDR, 4869fdf900SLiu Gang CONFIG_SYS_SRIO_PCIE_BOOT_SLAVE_ADDR_PHYS, 4969fdf900SLiu Gang MAS3_SX|MAS3_SW|MAS3_SR, MAS2_W|MAS2_G, 5069fdf900SLiu Gang 0, 0, BOOKE_PAGESZ_1M, 1), 51ee52b188SYork Sun #else 52ee52b188SYork Sun SET_TLB_ENTRY(1, 0xfffff000, 0xfffff000, 53ee52b188SYork Sun MAS3_SX|MAS3_SW|MAS3_SR, MAS2_I|MAS2_G, 54ee52b188SYork Sun 0, 0, BOOKE_PAGESZ_4K, 1), 55ee52b188SYork Sun #endif 56ee52b188SYork Sun 57ee52b188SYork Sun /* *I*G* - CCSRBAR */ 58ee52b188SYork Sun SET_TLB_ENTRY(1, CONFIG_SYS_CCSRBAR, CONFIG_SYS_CCSRBAR_PHYS, 59ee52b188SYork Sun MAS3_SX|MAS3_SW|MAS3_SR, MAS2_I|MAS2_G, 60ee52b188SYork Sun 0, 1, BOOKE_PAGESZ_16M, 1), 61ee52b188SYork Sun 62ee52b188SYork Sun /* *I*G* - Flash, localbus */ 63ee52b188SYork Sun /* This will be changed to *I*G* after relocation to RAM. */ 64ee52b188SYork Sun SET_TLB_ENTRY(1, CONFIG_SYS_FLASH_BASE, CONFIG_SYS_FLASH_BASE_PHYS, 65ee52b188SYork Sun MAS3_SX|MAS3_SR, MAS2_W|MAS2_G, 66ee52b188SYork Sun 0, 2, BOOKE_PAGESZ_256M, 1), 67*b6036993SShaohui Xie #ifndef CONFIG_SPL_BUILD 68ee52b188SYork Sun /* *I*G* - PCI */ 69ee52b188SYork Sun SET_TLB_ENTRY(1, CONFIG_SYS_PCIE1_MEM_VIRT, CONFIG_SYS_PCIE1_MEM_PHYS, 70ee52b188SYork Sun MAS3_SX|MAS3_SW|MAS3_SR, MAS2_I|MAS2_G, 71ee52b188SYork Sun 0, 3, BOOKE_PAGESZ_1G, 1), 72ee52b188SYork Sun 73ee52b188SYork Sun /* *I*G* - PCI */ 74ee52b188SYork Sun SET_TLB_ENTRY(1, CONFIG_SYS_PCIE1_MEM_VIRT + 0x40000000, 75ee52b188SYork Sun CONFIG_SYS_PCIE1_MEM_PHYS + 0x40000000, 76ee52b188SYork Sun MAS3_SX|MAS3_SW|MAS3_SR, MAS2_I|MAS2_G, 77ee52b188SYork Sun 0, 4, BOOKE_PAGESZ_256M, 1), 78ee52b188SYork Sun 79ee52b188SYork Sun SET_TLB_ENTRY(1, CONFIG_SYS_PCIE1_MEM_VIRT + 0x50000000, 80ee52b188SYork Sun CONFIG_SYS_PCIE1_MEM_PHYS + 0x50000000, 81ee52b188SYork Sun MAS3_SX|MAS3_SW|MAS3_SR, MAS2_I|MAS2_G, 82ee52b188SYork Sun 0, 5, BOOKE_PAGESZ_256M, 1), 83ee52b188SYork Sun 84ee52b188SYork Sun /* *I*G* - PCI I/O */ 85ee52b188SYork Sun SET_TLB_ENTRY(1, CONFIG_SYS_PCIE1_IO_VIRT, CONFIG_SYS_PCIE1_IO_PHYS, 86ee52b188SYork Sun MAS3_SX|MAS3_SW|MAS3_SR, MAS2_I|MAS2_G, 87ee52b188SYork Sun 0, 6, BOOKE_PAGESZ_256K, 1), 88ee52b188SYork Sun 89ee52b188SYork Sun /* Bman/Qman */ 90ee52b188SYork Sun #ifdef CONFIG_SYS_BMAN_MEM_PHYS 91ee52b188SYork Sun SET_TLB_ENTRY(1, CONFIG_SYS_BMAN_MEM_BASE, CONFIG_SYS_BMAN_MEM_PHYS, 92ee52b188SYork Sun MAS3_SX|MAS3_SW|MAS3_SR, 0, 93ee52b188SYork Sun 0, 9, BOOKE_PAGESZ_16M, 1), 94ee52b188SYork Sun SET_TLB_ENTRY(1, CONFIG_SYS_BMAN_MEM_BASE + 0x01000000, 95ee52b188SYork Sun CONFIG_SYS_BMAN_MEM_PHYS + 0x01000000, 96ee52b188SYork Sun MAS3_SX|MAS3_SW|MAS3_SR, MAS2_I|MAS2_G, 97ee52b188SYork Sun 0, 10, BOOKE_PAGESZ_16M, 1), 98ee52b188SYork Sun #endif 99ee52b188SYork Sun #ifdef CONFIG_SYS_QMAN_MEM_PHYS 100ee52b188SYork Sun SET_TLB_ENTRY(1, CONFIG_SYS_QMAN_MEM_BASE, CONFIG_SYS_QMAN_MEM_PHYS, 101ee52b188SYork Sun MAS3_SX|MAS3_SW|MAS3_SR, 0, 102ee52b188SYork Sun 0, 11, BOOKE_PAGESZ_16M, 1), 103ee52b188SYork Sun SET_TLB_ENTRY(1, CONFIG_SYS_QMAN_MEM_BASE + 0x01000000, 104ee52b188SYork Sun CONFIG_SYS_QMAN_MEM_PHYS + 0x01000000, 105ee52b188SYork Sun MAS3_SX|MAS3_SW|MAS3_SR, MAS2_I|MAS2_G, 106ee52b188SYork Sun 0, 12, BOOKE_PAGESZ_16M, 1), 107ee52b188SYork Sun #endif 108*b6036993SShaohui Xie #endif 109ee52b188SYork Sun #ifdef CONFIG_SYS_DCSRBAR_PHYS 110ee52b188SYork Sun SET_TLB_ENTRY(1, CONFIG_SYS_DCSRBAR, CONFIG_SYS_DCSRBAR_PHYS, 111ee52b188SYork Sun MAS3_SX|MAS3_SW|MAS3_SR, MAS2_I|MAS2_G, 11249e946cbSStephen George 0, 13, BOOKE_PAGESZ_32M, 1), 113ee52b188SYork Sun #endif 114ee52b188SYork Sun #ifdef CONFIG_SYS_NAND_BASE 115ee52b188SYork Sun /* 116ee52b188SYork Sun * *I*G - NAND 117ee52b188SYork Sun * entry 14 and 15 has been used hard coded, they will be disabled 118ee52b188SYork Sun * in cpu_init_f, so we use entry 16 for nand. 119ee52b188SYork Sun */ 120ee52b188SYork Sun SET_TLB_ENTRY(1, CONFIG_SYS_NAND_BASE, CONFIG_SYS_NAND_BASE_PHYS, 121ee52b188SYork Sun MAS3_SX|MAS3_SW|MAS3_SR, MAS2_I|MAS2_G, 122ac13eb5dSPrabhakar Kushwaha 0, 16, BOOKE_PAGESZ_64K, 1), 123ee52b188SYork Sun #endif 1241cb19fbbSYork Sun #ifdef QIXIS_BASE_PHYS 125ee52b188SYork Sun SET_TLB_ENTRY(1, QIXIS_BASE, QIXIS_BASE_PHYS, 126ee52b188SYork Sun MAS3_SX|MAS3_SW|MAS3_SR, MAS2_I|MAS2_G, 127ee52b188SYork Sun 0, 17, BOOKE_PAGESZ_4K, 1), 1281cb19fbbSYork Sun #endif 12969fdf900SLiu Gang #ifdef CONFIG_SRIO_PCIE_BOOT_SLAVE 13069fdf900SLiu Gang /* 13169fdf900SLiu Gang * SRIO_PCIE_BOOT-SLAVE. 1M space from 0xffe00000 for 13269fdf900SLiu Gang * fetching ucode and ENV from master 13369fdf900SLiu Gang */ 13469fdf900SLiu Gang SET_TLB_ENTRY(1, CONFIG_SYS_SRIO_PCIE_BOOT_UCODE_ENV_ADDR, 13569fdf900SLiu Gang CONFIG_SYS_SRIO_PCIE_BOOT_UCODE_ENV_ADDR_PHYS, 13669fdf900SLiu Gang MAS3_SX|MAS3_SW|MAS3_SR, MAS2_G, 13769fdf900SLiu Gang 0, 18, BOOKE_PAGESZ_1M, 1), 13869fdf900SLiu Gang #endif 139ee52b188SYork Sun 140*b6036993SShaohui Xie #if defined(CONFIG_RAMBOOT_PBL) && !defined(CONFIG_SPL_BUILD) 141*b6036993SShaohui Xie SET_TLB_ENTRY(1, CONFIG_SYS_DDR_SDRAM_BASE, CONFIG_SYS_DDR_SDRAM_BASE, 142*b6036993SShaohui Xie MAS3_SX|MAS3_SW|MAS3_SR, 0, 143*b6036993SShaohui Xie 0, 19, BOOKE_PAGESZ_2G, 1) 144*b6036993SShaohui Xie #endif 145ee52b188SYork Sun }; 146ee52b188SYork Sun 147ee52b188SYork Sun int num_tlb_entries = ARRAY_SIZE(tlb_table); 148