1ee52b188SYork Sun /* 2ee52b188SYork Sun * Copyright 2008-2012 Freescale Semiconductor, Inc. 3ee52b188SYork Sun * 4ee52b188SYork Sun * (C) Copyright 2000 5ee52b188SYork Sun * Wolfgang Denk, DENX Software Engineering, wd@denx.de. 6ee52b188SYork Sun * 7ee52b188SYork Sun * See file CREDITS for list of people who contributed to this 8ee52b188SYork Sun * project. 9ee52b188SYork Sun * 10ee52b188SYork Sun * This program is free software; you can redistribute it and/or 11ee52b188SYork Sun * modify it under the terms of the GNU General Public License as 12ee52b188SYork Sun * published by the Free Software Foundation; either version 2 of 13ee52b188SYork Sun * the License, or (at your option) any later version. 14ee52b188SYork Sun * 15ee52b188SYork Sun * This program is distributed in the hope that it will be useful, 16ee52b188SYork Sun * but WITHOUT ANY WARRANTY; without even the implied warranty of 17ee52b188SYork Sun * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the 18ee52b188SYork Sun * GNU General Public License for more details. 19ee52b188SYork Sun * 20ee52b188SYork Sun * You should have received a copy of the GNU General Public License 21ee52b188SYork Sun * along with this program; if not, write to the Free Software 22ee52b188SYork Sun * Foundation, Inc., 59 Temple Place, Suite 330, Boston, 23ee52b188SYork Sun * MA 02111-1307 USA 24ee52b188SYork Sun */ 25ee52b188SYork Sun 26ee52b188SYork Sun #include <common.h> 27ee52b188SYork Sun #include <asm/mmu.h> 28ee52b188SYork Sun 29ee52b188SYork Sun struct fsl_e_tlb_entry tlb_table[] = { 30ee52b188SYork Sun /* TLB 0 - for temp stack in cache */ 31ee52b188SYork Sun SET_TLB_ENTRY(0, CONFIG_SYS_INIT_RAM_ADDR, 32ee52b188SYork Sun CONFIG_SYS_INIT_RAM_ADDR_PHYS, 33ee52b188SYork Sun MAS3_SX|MAS3_SW|MAS3_SR, 0, 34ee52b188SYork Sun 0, 0, BOOKE_PAGESZ_4K, 0), 35ee52b188SYork Sun SET_TLB_ENTRY(0, CONFIG_SYS_INIT_RAM_ADDR + 4 * 1024, 36ee52b188SYork Sun CONFIG_SYS_INIT_RAM_ADDR_PHYS + 4 * 1024, 37ee52b188SYork Sun MAS3_SX|MAS3_SW|MAS3_SR, 0, 38ee52b188SYork Sun 0, 0, BOOKE_PAGESZ_4K, 0), 39ee52b188SYork Sun SET_TLB_ENTRY(0, CONFIG_SYS_INIT_RAM_ADDR + 8 * 1024, 40ee52b188SYork Sun CONFIG_SYS_INIT_RAM_ADDR_PHYS + 8 * 1024, 41ee52b188SYork Sun MAS3_SX|MAS3_SW|MAS3_SR, 0, 42ee52b188SYork Sun 0, 0, BOOKE_PAGESZ_4K, 0), 43ee52b188SYork Sun SET_TLB_ENTRY(0, CONFIG_SYS_INIT_RAM_ADDR + 12 * 1024, 44ee52b188SYork Sun CONFIG_SYS_INIT_RAM_ADDR_PHYS + 12 * 1024, 45ee52b188SYork Sun MAS3_SX|MAS3_SW|MAS3_SR, 0, 46ee52b188SYork Sun 0, 0, BOOKE_PAGESZ_4K, 0), 47ee52b188SYork Sun 48ee52b188SYork Sun /* TLB 1 */ 49ee52b188SYork Sun /* *I*** - Covers boot page */ 50ee52b188SYork Sun #if defined(CONFIG_SYS_RAMBOOT) && defined(CONFIG_SYS_INIT_L3_ADDR) 51ee52b188SYork Sun /* 52ee52b188SYork Sun * *I*G - L3SRAM. When L3 is used as 1M SRAM, the address of the 53ee52b188SYork Sun * SRAM is at 0xfff00000, it covered the 0xfffff000. 54ee52b188SYork Sun */ 55ee52b188SYork Sun SET_TLB_ENTRY(1, CONFIG_SYS_INIT_L3_ADDR, CONFIG_SYS_INIT_L3_ADDR, 56ee52b188SYork Sun MAS3_SX|MAS3_SW|MAS3_SR, MAS2_I|MAS2_G, 57ee52b188SYork Sun 0, 0, BOOKE_PAGESZ_1M, 1), 58ee52b188SYork Sun #else 59ee52b188SYork Sun SET_TLB_ENTRY(1, 0xfffff000, 0xfffff000, 60ee52b188SYork Sun MAS3_SX|MAS3_SW|MAS3_SR, MAS2_I|MAS2_G, 61ee52b188SYork Sun 0, 0, BOOKE_PAGESZ_4K, 1), 62ee52b188SYork Sun #endif 63ee52b188SYork Sun 64ee52b188SYork Sun /* *I*G* - CCSRBAR */ 65ee52b188SYork Sun SET_TLB_ENTRY(1, CONFIG_SYS_CCSRBAR, CONFIG_SYS_CCSRBAR_PHYS, 66ee52b188SYork Sun MAS3_SX|MAS3_SW|MAS3_SR, MAS2_I|MAS2_G, 67ee52b188SYork Sun 0, 1, BOOKE_PAGESZ_16M, 1), 68ee52b188SYork Sun 69ee52b188SYork Sun /* *I*G* - Flash, localbus */ 70ee52b188SYork Sun /* This will be changed to *I*G* after relocation to RAM. */ 71ee52b188SYork Sun SET_TLB_ENTRY(1, CONFIG_SYS_FLASH_BASE, CONFIG_SYS_FLASH_BASE_PHYS, 72ee52b188SYork Sun MAS3_SX|MAS3_SR, MAS2_W|MAS2_G, 73ee52b188SYork Sun 0, 2, BOOKE_PAGESZ_256M, 1), 74ee52b188SYork Sun 75ee52b188SYork Sun /* *I*G* - PCI */ 76ee52b188SYork Sun SET_TLB_ENTRY(1, CONFIG_SYS_PCIE1_MEM_VIRT, CONFIG_SYS_PCIE1_MEM_PHYS, 77ee52b188SYork Sun MAS3_SX|MAS3_SW|MAS3_SR, MAS2_I|MAS2_G, 78ee52b188SYork Sun 0, 3, BOOKE_PAGESZ_1G, 1), 79ee52b188SYork Sun 80ee52b188SYork Sun /* *I*G* - PCI */ 81ee52b188SYork Sun SET_TLB_ENTRY(1, CONFIG_SYS_PCIE1_MEM_VIRT + 0x40000000, 82ee52b188SYork Sun CONFIG_SYS_PCIE1_MEM_PHYS + 0x40000000, 83ee52b188SYork Sun MAS3_SX|MAS3_SW|MAS3_SR, MAS2_I|MAS2_G, 84ee52b188SYork Sun 0, 4, BOOKE_PAGESZ_256M, 1), 85ee52b188SYork Sun 86ee52b188SYork Sun SET_TLB_ENTRY(1, CONFIG_SYS_PCIE1_MEM_VIRT + 0x50000000, 87ee52b188SYork Sun CONFIG_SYS_PCIE1_MEM_PHYS + 0x50000000, 88ee52b188SYork Sun MAS3_SX|MAS3_SW|MAS3_SR, MAS2_I|MAS2_G, 89ee52b188SYork Sun 0, 5, BOOKE_PAGESZ_256M, 1), 90ee52b188SYork Sun 91ee52b188SYork Sun /* *I*G* - PCI I/O */ 92ee52b188SYork Sun SET_TLB_ENTRY(1, CONFIG_SYS_PCIE1_IO_VIRT, CONFIG_SYS_PCIE1_IO_PHYS, 93ee52b188SYork Sun MAS3_SX|MAS3_SW|MAS3_SR, MAS2_I|MAS2_G, 94ee52b188SYork Sun 0, 6, BOOKE_PAGESZ_256K, 1), 95ee52b188SYork Sun 96ee52b188SYork Sun /* Bman/Qman */ 97ee52b188SYork Sun #ifdef CONFIG_SYS_BMAN_MEM_PHYS 98ee52b188SYork Sun SET_TLB_ENTRY(1, CONFIG_SYS_BMAN_MEM_BASE, CONFIG_SYS_BMAN_MEM_PHYS, 99ee52b188SYork Sun MAS3_SX|MAS3_SW|MAS3_SR, 0, 100ee52b188SYork Sun 0, 9, BOOKE_PAGESZ_16M, 1), 101ee52b188SYork Sun SET_TLB_ENTRY(1, CONFIG_SYS_BMAN_MEM_BASE + 0x01000000, 102ee52b188SYork Sun CONFIG_SYS_BMAN_MEM_PHYS + 0x01000000, 103ee52b188SYork Sun MAS3_SX|MAS3_SW|MAS3_SR, MAS2_I|MAS2_G, 104ee52b188SYork Sun 0, 10, BOOKE_PAGESZ_16M, 1), 105ee52b188SYork Sun #endif 106ee52b188SYork Sun #ifdef CONFIG_SYS_QMAN_MEM_PHYS 107ee52b188SYork Sun SET_TLB_ENTRY(1, CONFIG_SYS_QMAN_MEM_BASE, CONFIG_SYS_QMAN_MEM_PHYS, 108ee52b188SYork Sun MAS3_SX|MAS3_SW|MAS3_SR, 0, 109ee52b188SYork Sun 0, 11, BOOKE_PAGESZ_16M, 1), 110ee52b188SYork Sun SET_TLB_ENTRY(1, CONFIG_SYS_QMAN_MEM_BASE + 0x01000000, 111ee52b188SYork Sun CONFIG_SYS_QMAN_MEM_PHYS + 0x01000000, 112ee52b188SYork Sun MAS3_SX|MAS3_SW|MAS3_SR, MAS2_I|MAS2_G, 113ee52b188SYork Sun 0, 12, BOOKE_PAGESZ_16M, 1), 114ee52b188SYork Sun #endif 115ee52b188SYork Sun #ifdef CONFIG_SYS_DCSRBAR_PHYS 116ee52b188SYork Sun SET_TLB_ENTRY(1, CONFIG_SYS_DCSRBAR, CONFIG_SYS_DCSRBAR_PHYS, 117ee52b188SYork Sun MAS3_SX|MAS3_SW|MAS3_SR, MAS2_I|MAS2_G, 118*49e946cbSStephen George 0, 13, BOOKE_PAGESZ_32M, 1), 119ee52b188SYork Sun #endif 120ee52b188SYork Sun #ifdef CONFIG_SYS_NAND_BASE 121ee52b188SYork Sun /* 122ee52b188SYork Sun * *I*G - NAND 123ee52b188SYork Sun * entry 14 and 15 has been used hard coded, they will be disabled 124ee52b188SYork Sun * in cpu_init_f, so we use entry 16 for nand. 125ee52b188SYork Sun */ 126ee52b188SYork Sun SET_TLB_ENTRY(1, CONFIG_SYS_NAND_BASE, CONFIG_SYS_NAND_BASE_PHYS, 127ee52b188SYork Sun MAS3_SX|MAS3_SW|MAS3_SR, MAS2_I|MAS2_G, 128ac13eb5dSPrabhakar Kushwaha 0, 16, BOOKE_PAGESZ_64K, 1), 129ee52b188SYork Sun #endif 130ee52b188SYork Sun SET_TLB_ENTRY(1, QIXIS_BASE, QIXIS_BASE_PHYS, 131ee52b188SYork Sun MAS3_SX|MAS3_SW|MAS3_SR, MAS2_I|MAS2_G, 132ee52b188SYork Sun 0, 17, BOOKE_PAGESZ_4K, 1), 133ee52b188SYork Sun 134ee52b188SYork Sun }; 135ee52b188SYork Sun 136ee52b188SYork Sun int num_tlb_entries = ARRAY_SIZE(tlb_table); 137