1 /* 2 * Copyright 2009-2012 Freescale Semiconductor, Inc. 3 * 4 * SPDX-License-Identifier: GPL-2.0+ 5 */ 6 7 #include <common.h> 8 #include <command.h> 9 #include <i2c.h> 10 #include <netdev.h> 11 #include <linux/compiler.h> 12 #include <asm/mmu.h> 13 #include <asm/processor.h> 14 #include <asm/cache.h> 15 #include <asm/immap_85xx.h> 16 #include <asm/fsl_law.h> 17 #include <asm/fsl_serdes.h> 18 #include <asm/fsl_portals.h> 19 #include <asm/fsl_liodn.h> 20 #include <fm_eth.h> 21 22 #include "../common/qixis.h" 23 #include "../common/vsc3316_3308.h" 24 #include "t4qds.h" 25 #include "t4240qds_qixis.h" 26 27 DECLARE_GLOBAL_DATA_PTR; 28 29 static int8_t vsc3316_fsm1_tx[8][2] = { {0, 0}, {1, 1}, {6, 6}, {7, 7}, 30 {8, 8}, {9, 9}, {14, 14}, {15, 15} }; 31 32 static int8_t vsc3316_fsm2_tx[8][2] = { {2, 2}, {3, 3}, {4, 4}, {5, 5}, 33 {10, 10}, {11, 11}, {12, 12}, {13, 13} }; 34 35 static int8_t vsc3316_fsm1_rx[8][2] = { {2, 12}, {3, 13}, {4, 5}, {5, 4}, 36 {10, 11}, {11, 10}, {12, 2}, {13, 3} }; 37 38 static int8_t vsc3316_fsm2_rx[8][2] = { {0, 15}, {1, 14}, {6, 7}, {7, 6}, 39 {8, 9}, {9, 8}, {14, 1}, {15, 0} }; 40 41 int checkboard(void) 42 { 43 char buf[64]; 44 u8 sw; 45 struct cpu_type *cpu = gd->arch.cpu; 46 unsigned int i; 47 48 printf("Board: %sQDS, ", cpu->name); 49 printf("Sys ID: 0x%02x, Sys Ver: 0x%02x, ", 50 QIXIS_READ(id), QIXIS_READ(arch)); 51 52 sw = QIXIS_READ(brdcfg[0]); 53 sw = (sw & QIXIS_LBMAP_MASK) >> QIXIS_LBMAP_SHIFT; 54 55 if (sw < 0x8) 56 printf("vBank: %d\n", sw); 57 else if (sw == 0x8) 58 puts("Promjet\n"); 59 else if (sw == 0x9) 60 puts("NAND\n"); 61 else 62 printf("invalid setting of SW%u\n", QIXIS_LBMAP_SWITCH); 63 64 printf("FPGA: v%d (%s), build %d", 65 (int)QIXIS_READ(scver), qixis_read_tag(buf), 66 (int)qixis_read_minor()); 67 /* the timestamp string contains "\n" at the end */ 68 printf(" on %s", qixis_read_time(buf)); 69 70 /* 71 * Display the actual SERDES reference clocks as configured by the 72 * dip switches on the board. Note that the SWx registers could 73 * technically be set to force the reference clocks to match the 74 * values that the SERDES expects (or vice versa). For now, however, 75 * we just display both values and hope the user notices when they 76 * don't match. 77 */ 78 puts("SERDES Reference Clocks: "); 79 sw = QIXIS_READ(brdcfg[2]); 80 for (i = 0; i < MAX_SERDES; i++) { 81 static const char * const freq[] = { 82 "100", "125", "156.25", "161.1328125"}; 83 unsigned int clock = (sw >> (6 - 2 * i)) & 3; 84 85 printf("SERDES%u=%sMHz ", i+1, freq[clock]); 86 } 87 puts("\n"); 88 89 return 0; 90 } 91 92 int select_i2c_ch_pca9547(u8 ch) 93 { 94 int ret; 95 96 ret = i2c_write(I2C_MUX_PCA_ADDR_PRI, 0, 1, &ch, 1); 97 if (ret) { 98 puts("PCA: failed to select proper channel\n"); 99 return ret; 100 } 101 102 return 0; 103 } 104 105 /* 106 * read_voltage from sensor on I2C bus 107 * We use average of 4 readings, waiting for 532us befor another reading 108 */ 109 #define NUM_READINGS 4 /* prefer to be power of 2 for efficiency */ 110 #define WAIT_FOR_ADC 532 /* wait for 532 microseconds for ADC */ 111 112 static inline int read_voltage(void) 113 { 114 int i, ret, voltage_read = 0; 115 u16 vol_mon; 116 117 for (i = 0; i < NUM_READINGS; i++) { 118 ret = i2c_read(I2C_VOL_MONITOR_ADDR, 119 I2C_VOL_MONITOR_BUS_V_OFFSET, 1, (void *)&vol_mon, 2); 120 if (ret) { 121 printf("VID: failed to read core voltage\n"); 122 return ret; 123 } 124 if (vol_mon & I2C_VOL_MONITOR_BUS_V_OVF) { 125 printf("VID: Core voltage sensor error\n"); 126 return -1; 127 } 128 debug("VID: bus voltage reads 0x%04x\n", vol_mon); 129 /* LSB = 4mv */ 130 voltage_read += (vol_mon >> I2C_VOL_MONITOR_BUS_V_SHIFT) * 4; 131 udelay(WAIT_FOR_ADC); 132 } 133 /* calculate the average */ 134 voltage_read /= NUM_READINGS; 135 136 return voltage_read; 137 } 138 139 /* 140 * We need to calculate how long before the voltage starts to drop or increase 141 * It returns with the loop count. Each loop takes several readings (532us) 142 */ 143 static inline int wait_for_voltage_change(int vdd_last) 144 { 145 int timeout, vdd_current; 146 147 vdd_current = read_voltage(); 148 /* wait until voltage starts to drop */ 149 for (timeout = 0; abs(vdd_last - vdd_current) <= 4 && 150 timeout < 100; timeout++) { 151 vdd_current = read_voltage(); 152 } 153 if (timeout >= 100) { 154 printf("VID: Voltage adjustment timeout\n"); 155 return -1; 156 } 157 return timeout; 158 } 159 160 /* 161 * argument 'wait' is the time we know the voltage difference can be measured 162 * this function keeps reading the voltage until it is stable 163 */ 164 static inline int wait_for_voltage_stable(int wait) 165 { 166 int timeout, vdd_current, vdd_last; 167 168 vdd_last = read_voltage(); 169 udelay(wait * NUM_READINGS * WAIT_FOR_ADC); 170 /* wait until voltage is stable */ 171 vdd_current = read_voltage(); 172 for (timeout = 0; abs(vdd_last - vdd_current) >= 4 && 173 timeout < 100; timeout++) { 174 vdd_last = vdd_current; 175 udelay(wait * NUM_READINGS * WAIT_FOR_ADC); 176 vdd_current = read_voltage(); 177 } 178 if (timeout >= 100) { 179 printf("VID: Voltage adjustment timeout\n"); 180 return -1; 181 } 182 183 return vdd_current; 184 } 185 186 static inline int set_voltage(u8 vid) 187 { 188 int wait, vdd_last; 189 190 vdd_last = read_voltage(); 191 QIXIS_WRITE(brdcfg[6], vid); 192 wait = wait_for_voltage_change(vdd_last); 193 if (wait < 0) 194 return -1; 195 debug("VID: Waited %d us\n", wait * NUM_READINGS * WAIT_FOR_ADC); 196 wait = wait ? wait : 1; 197 198 vdd_last = wait_for_voltage_stable(wait); 199 if (vdd_last < 0) 200 return -1; 201 debug("VID: Current voltage is %d mV\n", vdd_last); 202 203 return vdd_last; 204 } 205 206 207 static int adjust_vdd(ulong vdd_override) 208 { 209 int re_enable = disable_interrupts(); 210 ccsr_gur_t __iomem *gur = 211 (void __iomem *)(CONFIG_SYS_MPC85xx_GUTS_ADDR); 212 u32 fusesr; 213 u8 vid, vid_current; 214 int vdd_target, vdd_current, vdd_last; 215 int ret; 216 unsigned long vdd_string_override; 217 char *vdd_string; 218 static const uint16_t vdd[32] = { 219 0, /* unused */ 220 9875, /* 0.9875V */ 221 9750, 222 9625, 223 9500, 224 9375, 225 9250, 226 9125, 227 9000, 228 8875, 229 8750, 230 8625, 231 8500, 232 8375, 233 8250, 234 8125, 235 10000, /* 1.0000V */ 236 10125, 237 10250, 238 10375, 239 10500, 240 10625, 241 10750, 242 10875, 243 11000, 244 0, /* reserved */ 245 }; 246 struct vdd_drive { 247 u8 vid; 248 unsigned voltage; 249 }; 250 251 ret = select_i2c_ch_pca9547(I2C_MUX_CH_VOL_MONITOR); 252 if (ret) { 253 debug("VID: I2c failed to switch channel\n"); 254 ret = -1; 255 goto exit; 256 } 257 258 /* get the voltage ID from fuse status register */ 259 fusesr = in_be32(&gur->dcfg_fusesr); 260 vid = (fusesr >> FSL_CORENET_DCFG_FUSESR_VID_SHIFT) & 261 FSL_CORENET_DCFG_FUSESR_VID_MASK; 262 if (vid == FSL_CORENET_DCFG_FUSESR_VID_MASK) { 263 vid = (fusesr >> FSL_CORENET_DCFG_FUSESR_ALTVID_SHIFT) & 264 FSL_CORENET_DCFG_FUSESR_ALTVID_MASK; 265 } 266 vdd_target = vdd[vid]; 267 268 /* check override variable for overriding VDD */ 269 vdd_string = getenv("t4240qds_vdd_mv"); 270 if (vdd_override == 0 && vdd_string && 271 !strict_strtoul(vdd_string, 10, &vdd_string_override)) 272 vdd_override = vdd_string_override; 273 if (vdd_override >= 819 && vdd_override <= 1212) { 274 vdd_target = vdd_override * 10; /* convert to 1/10 mV */ 275 debug("VDD override is %lu\n", vdd_override); 276 } else if (vdd_override != 0) { 277 printf("Invalid value.\n"); 278 } 279 280 if (vdd_target == 0) { 281 debug("VID: VID not used\n"); 282 ret = 0; 283 goto exit; 284 } else { 285 /* round up and divice by 10 to get a value in mV */ 286 vdd_target = DIV_ROUND_UP(vdd_target, 10); 287 debug("VID: vid = %d mV\n", vdd_target); 288 } 289 290 /* 291 * Check current board VID setting 292 * Voltage regulator support output to 6.250mv step 293 * The highes voltage allowed for this board is (vid=0x40) 1.21250V 294 * the lowest is (vid=0x7f) 0.81875V 295 */ 296 vid_current = QIXIS_READ(brdcfg[6]); 297 vdd_current = 121250 - (vid_current - 0x40) * 625; 298 debug("VID: Current vid setting is (0x%x) %d mV\n", 299 vid_current, vdd_current/100); 300 301 /* 302 * Read voltage monitor to check real voltage. 303 * Voltage monitor LSB is 4mv. 304 */ 305 vdd_last = read_voltage(); 306 if (vdd_last < 0) { 307 printf("VID: Could not read voltage sensor abort VID adjustment\n"); 308 ret = -1; 309 goto exit; 310 } 311 debug("VID: Core voltage is at %d mV\n", vdd_last); 312 /* 313 * Adjust voltage to at or 8mV above target. 314 * Each step of adjustment is 6.25mV. 315 * Stepping down too fast may cause over current. 316 */ 317 while (vdd_last > 0 && vid_current < 0x80 && 318 vdd_last > (vdd_target + 8)) { 319 vid_current++; 320 vdd_last = set_voltage(vid_current); 321 } 322 /* 323 * Check if we need to step up 324 * This happens when board voltage switch was set too low 325 */ 326 while (vdd_last > 0 && vid_current >= 0x40 && 327 vdd_last < vdd_target + 2) { 328 vid_current--; 329 vdd_last = set_voltage(vid_current); 330 } 331 if (vdd_last > 0) 332 printf("VID: Core voltage %d mV\n", vdd_last); 333 else 334 ret = -1; 335 336 exit: 337 if (re_enable) 338 enable_interrupts(); 339 return ret; 340 } 341 342 /* Configure Crossbar switches for Front-Side SerDes Ports */ 343 int config_frontside_crossbar_vsc3316(void) 344 { 345 ccsr_gur_t *gur = (void *)(CONFIG_SYS_MPC85xx_GUTS_ADDR); 346 u32 srds_prtcl_s1, srds_prtcl_s2; 347 int ret; 348 349 ret = select_i2c_ch_pca9547(I2C_MUX_CH_VSC3316_FS); 350 if (ret) 351 return ret; 352 353 srds_prtcl_s1 = in_be32(&gur->rcwsr[4]) & 354 FSL_CORENET2_RCWSR4_SRDS1_PRTCL; 355 srds_prtcl_s1 >>= FSL_CORENET2_RCWSR4_SRDS1_PRTCL_SHIFT; 356 switch (srds_prtcl_s1) { 357 case 37: 358 case 38: 359 /* swap first lane and third lane on slot1 */ 360 vsc3316_fsm1_tx[0][1] = 14; 361 vsc3316_fsm1_tx[6][1] = 0; 362 vsc3316_fsm1_rx[1][1] = 2; 363 vsc3316_fsm1_rx[6][1] = 13; 364 case 39: 365 case 40: 366 case 45: 367 case 46: 368 case 47: 369 case 48: 370 /* swap first lane and third lane on slot2 */ 371 vsc3316_fsm1_tx[2][1] = 8; 372 vsc3316_fsm1_tx[4][1] = 6; 373 vsc3316_fsm1_rx[2][1] = 10; 374 vsc3316_fsm1_rx[5][1] = 5; 375 default: 376 ret = vsc3316_config(VSC3316_FSM_TX_ADDR, vsc3316_fsm1_tx, 8); 377 if (ret) 378 return ret; 379 ret = vsc3316_config(VSC3316_FSM_RX_ADDR, vsc3316_fsm1_rx, 8); 380 if (ret) 381 return ret; 382 break; 383 } 384 385 srds_prtcl_s2 = in_be32(&gur->rcwsr[4]) & 386 FSL_CORENET2_RCWSR4_SRDS2_PRTCL; 387 srds_prtcl_s2 >>= FSL_CORENET2_RCWSR4_SRDS2_PRTCL_SHIFT; 388 switch (srds_prtcl_s2) { 389 case 37: 390 case 38: 391 /* swap first lane and third lane on slot3 */ 392 vsc3316_fsm2_tx[2][1] = 11; 393 vsc3316_fsm2_tx[5][1] = 4; 394 vsc3316_fsm2_rx[2][1] = 9; 395 vsc3316_fsm2_rx[4][1] = 7; 396 case 39: 397 case 40: 398 case 45: 399 case 46: 400 case 47: 401 case 48: 402 case 49: 403 case 50: 404 case 51: 405 case 52: 406 case 53: 407 case 54: 408 /* swap first lane and third lane on slot4 */ 409 vsc3316_fsm2_tx[6][1] = 3; 410 vsc3316_fsm2_tx[1][1] = 12; 411 vsc3316_fsm2_rx[0][1] = 1; 412 vsc3316_fsm2_rx[6][1] = 15; 413 default: 414 ret = vsc3316_config(VSC3316_FSM_TX_ADDR, vsc3316_fsm2_tx, 8); 415 if (ret) 416 return ret; 417 ret = vsc3316_config(VSC3316_FSM_RX_ADDR, vsc3316_fsm2_rx, 8); 418 if (ret) 419 return ret; 420 break; 421 } 422 423 return 0; 424 } 425 426 int config_backside_crossbar_mux(void) 427 { 428 ccsr_gur_t *gur = (void *)(CONFIG_SYS_MPC85xx_GUTS_ADDR); 429 u32 srds_prtcl_s3, srds_prtcl_s4; 430 u8 brdcfg; 431 432 srds_prtcl_s3 = in_be32(&gur->rcwsr[4]) & 433 FSL_CORENET2_RCWSR4_SRDS3_PRTCL; 434 srds_prtcl_s3 >>= FSL_CORENET2_RCWSR4_SRDS3_PRTCL_SHIFT; 435 switch (srds_prtcl_s3) { 436 case 0: 437 /* SerDes3 is not enabled */ 438 break; 439 case 1: 440 case 2: 441 case 9: 442 case 10: 443 /* SD3(0:7) => SLOT5(0:7) */ 444 brdcfg = QIXIS_READ(brdcfg[12]); 445 brdcfg &= ~BRDCFG12_SD3MX_MASK; 446 brdcfg |= BRDCFG12_SD3MX_SLOT5; 447 QIXIS_WRITE(brdcfg[12], brdcfg); 448 break; 449 case 3: 450 case 4: 451 case 5: 452 case 6: 453 case 7: 454 case 8: 455 case 11: 456 case 12: 457 case 13: 458 case 14: 459 case 15: 460 case 16: 461 case 17: 462 case 18: 463 case 19: 464 case 20: 465 /* SD3(4:7) => SLOT6(0:3) */ 466 brdcfg = QIXIS_READ(brdcfg[12]); 467 brdcfg &= ~BRDCFG12_SD3MX_MASK; 468 brdcfg |= BRDCFG12_SD3MX_SLOT6; 469 QIXIS_WRITE(brdcfg[12], brdcfg); 470 break; 471 default: 472 printf("WARNING: unsupported for SerDes3 Protocol %d\n", 473 srds_prtcl_s3); 474 return -1; 475 } 476 477 srds_prtcl_s4 = in_be32(&gur->rcwsr[4]) & 478 FSL_CORENET2_RCWSR4_SRDS4_PRTCL; 479 srds_prtcl_s4 >>= FSL_CORENET2_RCWSR4_SRDS4_PRTCL_SHIFT; 480 switch (srds_prtcl_s4) { 481 case 0: 482 /* SerDes4 is not enabled */ 483 break; 484 case 1: 485 case 2: 486 /* 10b, SD4(0:7) => SLOT7(0:7) */ 487 brdcfg = QIXIS_READ(brdcfg[12]); 488 brdcfg &= ~BRDCFG12_SD4MX_MASK; 489 brdcfg |= BRDCFG12_SD4MX_SLOT7; 490 QIXIS_WRITE(brdcfg[12], brdcfg); 491 break; 492 case 3: 493 case 4: 494 case 5: 495 case 6: 496 case 7: 497 case 8: 498 /* x1b, SD4(4:7) => SLOT8(0:3) */ 499 brdcfg = QIXIS_READ(brdcfg[12]); 500 brdcfg &= ~BRDCFG12_SD4MX_MASK; 501 brdcfg |= BRDCFG12_SD4MX_SLOT8; 502 QIXIS_WRITE(brdcfg[12], brdcfg); 503 break; 504 case 9: 505 case 10: 506 case 11: 507 case 12: 508 case 13: 509 case 14: 510 case 15: 511 case 16: 512 case 18: 513 /* 00b, SD4(4:5) => AURORA, SD4(6:7) => SATA */ 514 brdcfg = QIXIS_READ(brdcfg[12]); 515 brdcfg &= ~BRDCFG12_SD4MX_MASK; 516 brdcfg |= BRDCFG12_SD4MX_AURO_SATA; 517 QIXIS_WRITE(brdcfg[12], brdcfg); 518 break; 519 default: 520 printf("WARNING: unsupported for SerDes4 Protocol %d\n", 521 srds_prtcl_s4); 522 return -1; 523 } 524 525 return 0; 526 } 527 528 int board_early_init_r(void) 529 { 530 const unsigned int flashbase = CONFIG_SYS_FLASH_BASE; 531 int flash_esel = find_tlb_idx((void *)flashbase, 1); 532 533 /* 534 * Remap Boot flash + PROMJET region to caching-inhibited 535 * so that flash can be erased properly. 536 */ 537 538 /* Flush d-cache and invalidate i-cache of any FLASH data */ 539 flush_dcache(); 540 invalidate_icache(); 541 542 if (flash_esel == -1) { 543 /* very unlikely unless something is messed up */ 544 puts("Error: Could not find TLB for FLASH BASE\n"); 545 flash_esel = 2; /* give our best effort to continue */ 546 } else { 547 /* invalidate existing TLB entry for flash + promjet */ 548 disable_tlb(flash_esel); 549 } 550 551 set_tlb(1, flashbase, CONFIG_SYS_FLASH_BASE_PHYS, 552 MAS3_SX|MAS3_SW|MAS3_SR, MAS2_I|MAS2_G, 553 0, flash_esel, BOOKE_PAGESZ_256M, 1); 554 555 set_liodns(); 556 #ifdef CONFIG_SYS_DPAA_QBMAN 557 setup_portals(); 558 #endif 559 560 /* Disable remote I2C connection to qixis fpga */ 561 QIXIS_WRITE(brdcfg[5], QIXIS_READ(brdcfg[5]) & ~BRDCFG5_IRE); 562 563 /* 564 * Adjust core voltage according to voltage ID 565 * This function changes I2C mux to channel 2. 566 */ 567 if (adjust_vdd(0)) 568 printf("Warning: Adjusting core voltage failed.\n"); 569 570 /* Configure board SERDES ports crossbar */ 571 config_frontside_crossbar_vsc3316(); 572 config_backside_crossbar_mux(); 573 select_i2c_ch_pca9547(I2C_MUX_CH_DEFAULT); 574 575 return 0; 576 } 577 578 unsigned long get_board_sys_clk(void) 579 { 580 u8 sysclk_conf = QIXIS_READ(brdcfg[1]); 581 #ifdef CONFIG_FSL_QIXIS_CLOCK_MEASUREMENT 582 /* use accurate clock measurement */ 583 int freq = QIXIS_READ(clk_freq[0]) << 8 | QIXIS_READ(clk_freq[1]); 584 int base = QIXIS_READ(clk_base[0]) << 8 | QIXIS_READ(clk_base[1]); 585 u32 val; 586 587 val = freq * base; 588 if (val) { 589 debug("SYS Clock measurement is: %d\n", val); 590 return val; 591 } else { 592 printf("Warning: SYS clock measurement is invalid, using value from brdcfg1.\n"); 593 } 594 #endif 595 596 switch (sysclk_conf & 0x0F) { 597 case QIXIS_SYSCLK_83: 598 return 83333333; 599 case QIXIS_SYSCLK_100: 600 return 100000000; 601 case QIXIS_SYSCLK_125: 602 return 125000000; 603 case QIXIS_SYSCLK_133: 604 return 133333333; 605 case QIXIS_SYSCLK_150: 606 return 150000000; 607 case QIXIS_SYSCLK_160: 608 return 160000000; 609 case QIXIS_SYSCLK_166: 610 return 166666666; 611 } 612 return 66666666; 613 } 614 615 unsigned long get_board_ddr_clk(void) 616 { 617 u8 ddrclk_conf = QIXIS_READ(brdcfg[1]); 618 #ifdef CONFIG_FSL_QIXIS_CLOCK_MEASUREMENT 619 /* use accurate clock measurement */ 620 int freq = QIXIS_READ(clk_freq[2]) << 8 | QIXIS_READ(clk_freq[3]); 621 int base = QIXIS_READ(clk_base[0]) << 8 | QIXIS_READ(clk_base[1]); 622 u32 val; 623 624 val = freq * base; 625 if (val) { 626 debug("DDR Clock measurement is: %d\n", val); 627 return val; 628 } else { 629 printf("Warning: DDR clock measurement is invalid, using value from brdcfg1.\n"); 630 } 631 #endif 632 633 switch ((ddrclk_conf & 0x30) >> 4) { 634 case QIXIS_DDRCLK_100: 635 return 100000000; 636 case QIXIS_DDRCLK_125: 637 return 125000000; 638 case QIXIS_DDRCLK_133: 639 return 133333333; 640 } 641 return 66666666; 642 } 643 644 int misc_init_r(void) 645 { 646 u8 sw; 647 void *srds_base = (void *)CONFIG_SYS_FSL_CORENET_SERDES_ADDR; 648 serdes_corenet_t *srds_regs; 649 u32 actual[MAX_SERDES]; 650 u32 pllcr0, expected; 651 unsigned int i; 652 653 sw = QIXIS_READ(brdcfg[2]); 654 for (i = 0; i < MAX_SERDES; i++) { 655 unsigned int clock = (sw >> (6 - 2 * i)) & 3; 656 switch (clock) { 657 case 0: 658 actual[i] = SRDS_PLLCR0_RFCK_SEL_100; 659 break; 660 case 1: 661 actual[i] = SRDS_PLLCR0_RFCK_SEL_125; 662 break; 663 case 2: 664 actual[i] = SRDS_PLLCR0_RFCK_SEL_156_25; 665 break; 666 case 3: 667 actual[i] = SRDS_PLLCR0_RFCK_SEL_161_13; 668 break; 669 } 670 } 671 672 for (i = 0; i < MAX_SERDES; i++) { 673 srds_regs = srds_base + i * 0x1000; 674 pllcr0 = srds_regs->bank[0].pllcr0; 675 expected = pllcr0 & SRDS_PLLCR0_RFCK_SEL_MASK; 676 if (expected != actual[i]) { 677 printf("Warning: SERDES%u expects reference clock %sMHz, but actual is %sMHz\n", 678 i + 1, serdes_clock_to_string(expected), 679 serdes_clock_to_string(actual[i])); 680 } 681 } 682 683 return 0; 684 } 685 686 int ft_board_setup(void *blob, bd_t *bd) 687 { 688 phys_addr_t base; 689 phys_size_t size; 690 691 ft_cpu_setup(blob, bd); 692 693 base = getenv_bootm_low(); 694 size = getenv_bootm_size(); 695 696 fdt_fixup_memory(blob, (u64)base, (u64)size); 697 698 #ifdef CONFIG_PCI 699 pci_of_setup(blob, bd); 700 #endif 701 702 fdt_fixup_liodn(blob); 703 fdt_fixup_dr_usb(blob, bd); 704 705 #ifdef CONFIG_SYS_DPAA_FMAN 706 fdt_fixup_fman_ethernet(blob); 707 fdt_fixup_board_enet(blob); 708 #endif 709 710 return 0; 711 } 712 713 /* 714 * This function is called by bdinfo to print detail board information. 715 * As an exmaple for future board, we organize the messages into 716 * several sections. If applicable, the message is in the format of 717 * <name> = <value> 718 * It should aligned with normal output of bdinfo command. 719 * 720 * Voltage: Core, DDR and another configurable voltages 721 * Clock : Critical clocks which are not printed already 722 * RCW : RCW source if not printed already 723 * Misc : Other important information not in above catagories 724 */ 725 void board_detail(void) 726 { 727 int i; 728 u8 brdcfg[16], dutcfg[16], rst_ctl; 729 int vdd, rcwsrc; 730 static const char * const clk[] = {"66.67", "100", "125", "133.33"}; 731 732 for (i = 0; i < 16; i++) { 733 brdcfg[i] = qixis_read(offsetof(struct qixis, brdcfg[0]) + i); 734 dutcfg[i] = qixis_read(offsetof(struct qixis, dutcfg[0]) + i); 735 } 736 737 /* Voltage secion */ 738 if (!select_i2c_ch_pca9547(I2C_MUX_CH_VOL_MONITOR)) { 739 vdd = read_voltage(); 740 if (vdd > 0) 741 printf("Core voltage= %d mV\n", vdd); 742 select_i2c_ch_pca9547(I2C_MUX_CH_DEFAULT); 743 } 744 745 printf("XVDD = 1.%d V\n", ((brdcfg[8] & 0xf) - 4) * 5 + 25); 746 747 /* clock section */ 748 printf("SYSCLK = %s MHz\nDDRCLK = %s MHz\n", 749 clk[(brdcfg[11] >> 2) & 0x3], clk[brdcfg[11] & 3]); 750 751 /* RCW section */ 752 rcwsrc = (dutcfg[0] << 1) + (dutcfg[1] & 1); 753 puts("RCW source = "); 754 switch (rcwsrc) { 755 case 0x017: 756 case 0x01f: 757 puts("8-bit NOR\n"); 758 break; 759 case 0x027: 760 case 0x02F: 761 puts("16-bit NOR\n"); 762 break; 763 case 0x040: 764 puts("SDHC/eMMC\n"); 765 break; 766 case 0x044: 767 puts("SPI 16-bit addressing\n"); 768 break; 769 case 0x045: 770 puts("SPI 24-bit addressing\n"); 771 break; 772 case 0x048: 773 puts("I2C normal addressing\n"); 774 break; 775 case 0x049: 776 puts("I2C extended addressing\n"); 777 break; 778 case 0x108: 779 case 0x109: 780 case 0x10a: 781 case 0x10b: 782 puts("8-bit NAND, 2KB\n"); 783 break; 784 default: 785 if ((rcwsrc >= 0x080) && (rcwsrc <= 0x09f)) 786 puts("Hard-coded RCW\n"); 787 else if ((rcwsrc >= 0x110) && (rcwsrc <= 0x11f)) 788 puts("8-bit NAND, 4KB\n"); 789 else 790 puts("unknown\n"); 791 break; 792 } 793 794 /* Misc section */ 795 rst_ctl = QIXIS_READ(rst_ctl); 796 puts("HRESET_REQ = "); 797 switch (rst_ctl & 0x30) { 798 case 0x00: 799 puts("Ignored\n"); 800 break; 801 case 0x10: 802 puts("Assert HRESET\n"); 803 break; 804 case 0x30: 805 puts("Reset system\n"); 806 break; 807 default: 808 puts("N/A\n"); 809 break; 810 } 811 } 812 813 /* 814 * Reverse engineering switch settings. 815 * Some bits cannot be figured out. They will be displayed as 816 * underscore in binary format. mask[] has those bits. 817 * Some bits are calculated differently than the actual switches 818 * if booting with overriding by FPGA. 819 */ 820 void qixis_dump_switch(void) 821 { 822 int i; 823 u8 sw[9]; 824 825 /* 826 * Any bit with 1 means that bit cannot be reverse engineered. 827 * It will be displayed as _ in binary format. 828 */ 829 static const u8 mask[] = {0, 0, 0, 0, 0, 0x1, 0xcf, 0x3f, 0x1f}; 830 char buf[10]; 831 u8 brdcfg[16], dutcfg[16]; 832 833 for (i = 0; i < 16; i++) { 834 brdcfg[i] = qixis_read(offsetof(struct qixis, brdcfg[0]) + i); 835 dutcfg[i] = qixis_read(offsetof(struct qixis, dutcfg[0]) + i); 836 } 837 838 sw[0] = dutcfg[0]; 839 sw[1] = (dutcfg[1] << 0x07) | 840 ((dutcfg[12] & 0xC0) >> 1) | 841 ((dutcfg[11] & 0xE0) >> 3) | 842 ((dutcfg[6] & 0x80) >> 6) | 843 ((dutcfg[1] & 0x80) >> 7); 844 sw[2] = ((brdcfg[1] & 0x0f) << 4) | 845 ((brdcfg[1] & 0x30) >> 2) | 846 ((brdcfg[1] & 0x40) >> 5) | 847 ((brdcfg[1] & 0x80) >> 7); 848 sw[3] = brdcfg[2]; 849 sw[4] = ((dutcfg[2] & 0x01) << 7) | 850 ((dutcfg[2] & 0x06) << 4) | 851 ((~QIXIS_READ(present)) & 0x10) | 852 ((brdcfg[3] & 0x80) >> 4) | 853 ((brdcfg[3] & 0x01) << 2) | 854 ((brdcfg[6] == 0x62) ? 3 : 855 ((brdcfg[6] == 0x5a) ? 2 : 856 ((brdcfg[6] == 0x5e) ? 1 : 0))); 857 sw[5] = ((brdcfg[0] & 0x0f) << 4) | 858 ((QIXIS_READ(rst_ctl) & 0x30) >> 2) | 859 ((brdcfg[0] & 0x40) >> 5); 860 sw[6] = (brdcfg[11] & 0x20) | 861 ((brdcfg[5] & 0x02) << 3); 862 sw[7] = (((~QIXIS_READ(rst_ctl)) & 0x40) << 1) | 863 ((brdcfg[5] & 0x10) << 2); 864 sw[8] = ((brdcfg[12] & 0x08) << 4) | 865 ((brdcfg[12] & 0x03) << 5); 866 867 puts("DIP switch (reverse-engineering)\n"); 868 for (i = 0; i < 9; i++) { 869 printf("SW%d = 0b%s (0x%02x)\n", 870 i + 1, byte_to_binary_mask(sw[i], mask[i], buf), sw[i]); 871 } 872 } 873 874 static int do_vdd_adjust(cmd_tbl_t *cmdtp, 875 int flag, int argc, 876 char * const argv[]) 877 { 878 ulong override; 879 880 if (argc < 2) 881 return CMD_RET_USAGE; 882 if (!strict_strtoul(argv[1], 10, &override)) 883 adjust_vdd(override); /* the value is checked by callee */ 884 else 885 return CMD_RET_USAGE; 886 887 return 0; 888 } 889 890 U_BOOT_CMD( 891 vdd_override, 2, 0, do_vdd_adjust, 892 "Override VDD", 893 "- override with the voltage specified in mV, eg. 1050" 894 ); 895