1 /* SPDX-License-Identifier: GPL-2.0+ */ 2 /* 3 * Copyright 2013 Freescale Semiconductor, Inc. 4 */ 5 6 #ifndef __DDR_H__ 7 #define __DDR_H__ 8 struct board_specific_parameters { 9 u32 n_ranks; 10 u32 datarate_mhz_high; 11 u32 rank_gb; 12 u32 clk_adjust; 13 u32 wrlvl_start; 14 u32 wrlvl_ctl_2; 15 u32 wrlvl_ctl_3; 16 u32 cpo; 17 u32 write_data_delay; 18 u32 force_2t; 19 }; 20 21 /* 22 * These tables contain all valid speeds we want to override with board 23 * specific parameters. datarate_mhz_high values need to be in ascending order 24 * for each n_ranks group. 25 */ 26 27 static const struct board_specific_parameters udimm0[] = { 28 /* 29 * memory controller 0 30 * num| hi| rank| clk| wrlvl | wrlvl | wrlvl | cpo |wrdata|2T 31 * ranks| mhz| GB |adjst| start | ctl2 | ctl3 | |delay | 32 */ 33 {2, 1350, 4, 8, 8, 0x0809090b, 0x0c0c0d0a, 0xff, 2, 0}, 34 {2, 1350, 0, 10, 7, 0x0709090b, 0x0c0c0d09, 0xff, 2, 0}, 35 {2, 1666, 4, 8, 8, 0x080a0a0d, 0x0d10100b, 0xff, 2, 0}, 36 {2, 1666, 0, 10, 7, 0x080a0a0c, 0x0d0d0e0a, 0xff, 2, 0}, 37 {2, 1900, 0, 8, 8, 0x090a0b0e, 0x0f11120c, 0xff, 2, 0}, 38 {2, 2140, 0, 8, 8, 0x090a0b0e, 0x0f11120c, 0xff, 2, 0}, 39 {1, 1350, 0, 10, 8, 0x0809090b, 0x0c0c0d0a, 0xff, 2, 0}, 40 {1, 1700, 0, 10, 8, 0x080a0a0c, 0x0c0d0e0a, 0xff, 2, 0}, 41 {1, 1900, 0, 8, 8, 0x080a0a0c, 0x0e0e0f0a, 0xff, 2, 0}, 42 {1, 2140, 0, 8, 8, 0x090a0b0c, 0x0e0f100b, 0xff, 2, 0}, 43 {} 44 }; 45 46 static const struct board_specific_parameters rdimm0[] = { 47 /* 48 * memory controller 0 49 * num| hi| rank| clk| wrlvl | wrlvl | wrlvl | cpo |wrdata|2T 50 * ranks| mhz| GB |adjst| start | ctl2 | ctl3 | |delay | 51 */ 52 {4, 1350, 0, 10, 9, 0x08070605, 0x06070806, 0xff, 2, 0}, 53 {4, 1666, 0, 10, 11, 0x0a080706, 0x07090906, 0xff, 2, 0}, 54 {4, 2140, 0, 10, 12, 0x0b090807, 0x080a0b07, 0xff, 2, 0}, 55 {2, 1350, 0, 10, 9, 0x08070605, 0x06070806, 0xff, 2, 0}, 56 {2, 1666, 0, 10, 11, 0x0a090806, 0x08090a06, 0xff, 2, 0}, 57 {2, 2140, 0, 10, 12, 0x0b090807, 0x080a0b07, 0xff, 2, 0}, 58 {1, 1350, 0, 10, 9, 0x08070605, 0x06070806, 0xff, 2, 0}, 59 {1, 1666, 0, 10, 11, 0x0a090806, 0x08090a06, 0xff, 2, 0}, 60 {1, 2140, 0, 8, 12, 0x0b090807, 0x080a0b07, 0xff, 2, 0}, 61 {} 62 }; 63 64 /* 65 * The three slots have slightly different timing. The center values are good 66 * for all slots. We use identical speed tables for them. In future use, if 67 * DIMMs require separated tables, make more entries as needed. 68 */ 69 static const struct board_specific_parameters *udimms[] = { 70 udimm0, 71 }; 72 73 /* 74 * The three slots have slightly different timing. See comments above. 75 */ 76 static const struct board_specific_parameters *rdimms[] = { 77 rdimm0, 78 }; 79 80 81 #endif 82