1 /* 2 * Copyright 2012 Freescale Semiconductor, Inc. 3 * 4 * This program is free software; you can redistribute it and/or 5 * modify it under the terms of the GNU General Public License 6 * Version 2 or later as published by the Free Software Foundation. 7 */ 8 9 #include <common.h> 10 #include <i2c.h> 11 #include <hwconfig.h> 12 #include <asm/mmu.h> 13 #include <fsl_ddr_sdram.h> 14 #include <fsl_ddr_dimm_params.h> 15 #include <asm/fsl_law.h> 16 #include "ddr.h" 17 18 DECLARE_GLOBAL_DATA_PTR; 19 20 void fsl_ddr_board_options(memctl_options_t *popts, 21 dimm_params_t *pdimm, 22 unsigned int ctrl_num) 23 { 24 const struct board_specific_parameters *pbsp, *pbsp_highest = NULL; 25 ulong ddr_freq; 26 27 if (ctrl_num > 2) { 28 printf("Not supported controller number %d\n", ctrl_num); 29 return; 30 } 31 if (!pdimm->n_ranks) 32 return; 33 34 /* 35 * we use identical timing for all slots. If needed, change the code 36 * to pbsp = rdimms[ctrl_num] or pbsp = udimms[ctrl_num]; 37 */ 38 if (popts->registered_dimm_en) 39 pbsp = rdimms[0]; 40 else 41 pbsp = udimms[0]; 42 43 44 /* Get clk_adjust, cpo, write_data_delay,2T, according to the board ddr 45 * freqency and n_banks specified in board_specific_parameters table. 46 */ 47 ddr_freq = get_ddr_freq(0) / 1000000; 48 while (pbsp->datarate_mhz_high) { 49 if (pbsp->n_ranks == pdimm->n_ranks && 50 (pdimm->rank_density >> 30) >= pbsp->rank_gb) { 51 if (ddr_freq <= pbsp->datarate_mhz_high) { 52 popts->cpo_override = pbsp->cpo; 53 popts->write_data_delay = 54 pbsp->write_data_delay; 55 popts->clk_adjust = pbsp->clk_adjust; 56 popts->wrlvl_start = pbsp->wrlvl_start; 57 popts->wrlvl_ctl_2 = pbsp->wrlvl_ctl_2; 58 popts->wrlvl_ctl_3 = pbsp->wrlvl_ctl_3; 59 popts->twot_en = pbsp->force_2t; 60 goto found; 61 } 62 pbsp_highest = pbsp; 63 } 64 pbsp++; 65 } 66 67 if (pbsp_highest) { 68 printf("Error: board specific timing not found " 69 "for data rate %lu MT/s\n" 70 "Trying to use the highest speed (%u) parameters\n", 71 ddr_freq, pbsp_highest->datarate_mhz_high); 72 popts->cpo_override = pbsp_highest->cpo; 73 popts->write_data_delay = pbsp_highest->write_data_delay; 74 popts->clk_adjust = pbsp_highest->clk_adjust; 75 popts->wrlvl_start = pbsp_highest->wrlvl_start; 76 popts->wrlvl_ctl_2 = pbsp->wrlvl_ctl_2; 77 popts->wrlvl_ctl_3 = pbsp->wrlvl_ctl_3; 78 popts->twot_en = pbsp_highest->force_2t; 79 } else { 80 panic("DIMM is not supported by this board"); 81 } 82 found: 83 debug("Found timing match: n_ranks %d, data rate %d, rank_gb %d\n" 84 "\tclk_adjust %d, wrlvl_start %d, wrlvl_ctrl_2 0x%x, " 85 "wrlvl_ctrl_3 0x%x\n", 86 pbsp->n_ranks, pbsp->datarate_mhz_high, pbsp->rank_gb, 87 pbsp->clk_adjust, pbsp->wrlvl_start, pbsp->wrlvl_ctl_2, 88 pbsp->wrlvl_ctl_3); 89 90 /* 91 * Factors to consider for half-strength driver enable: 92 * - number of DIMMs installed 93 */ 94 popts->half_strength_driver_enable = 0; 95 /* 96 * Write leveling override 97 */ 98 popts->wrlvl_override = 1; 99 popts->wrlvl_sample = 0xf; 100 101 /* 102 * Rtt and Rtt_WR override 103 */ 104 popts->rtt_override = 0; 105 106 /* Enable ZQ calibration */ 107 popts->zq_en = 1; 108 109 /* DHC_EN =1, ODT = 75 Ohm */ 110 popts->ddr_cdr1 = DDR_CDR1_DHC_EN | DDR_CDR1_ODT(DDR_CDR_ODT_75ohm); 111 popts->ddr_cdr2 = DDR_CDR2_ODT(DDR_CDR_ODT_75ohm); 112 } 113 114 phys_size_t initdram(int board_type) 115 { 116 phys_size_t dram_size; 117 118 puts("Initializing....using SPD\n"); 119 120 #if defined(CONFIG_SPL_BUILD) || !defined(CONFIG_RAMBOOT_PBL) 121 dram_size = fsl_ddr_sdram(); 122 123 dram_size = setup_ddr_tlbs(dram_size / 0x100000); 124 dram_size *= 0x100000; 125 126 #else 127 /* DDR has been initialised by first stage boot loader */ 128 dram_size = fsl_ddr_sdram_size(); 129 #endif 130 return dram_size; 131 } 132