1 // SPDX-License-Identifier: GPL-2.0+ 2 /* 3 * Copyright 2008-2014 Freescale Semiconductor, Inc. 4 * 5 * (C) Copyright 2000 6 * Wolfgang Denk, DENX Software Engineering, wd@denx.de. 7 */ 8 9 #include <common.h> 10 #include <asm/mmu.h> 11 12 struct fsl_e_tlb_entry tlb_table[] = { 13 /* TLB 0 - for temp stack in cache */ 14 SET_TLB_ENTRY(0, CONFIG_SYS_INIT_RAM_ADDR, 15 CONFIG_SYS_INIT_RAM_ADDR_PHYS, 16 MAS3_SX|MAS3_SW|MAS3_SR, 0, 17 0, 0, BOOKE_PAGESZ_4K, 0), 18 SET_TLB_ENTRY(0, CONFIG_SYS_INIT_RAM_ADDR + 4 * 1024, 19 CONFIG_SYS_INIT_RAM_ADDR_PHYS + 4 * 1024, 20 MAS3_SX|MAS3_SW|MAS3_SR, 0, 21 0, 0, BOOKE_PAGESZ_4K, 0), 22 SET_TLB_ENTRY(0, CONFIG_SYS_INIT_RAM_ADDR + 8 * 1024, 23 CONFIG_SYS_INIT_RAM_ADDR_PHYS + 8 * 1024, 24 MAS3_SX|MAS3_SW|MAS3_SR, 0, 25 0, 0, BOOKE_PAGESZ_4K, 0), 26 SET_TLB_ENTRY(0, CONFIG_SYS_INIT_RAM_ADDR + 12 * 1024, 27 CONFIG_SYS_INIT_RAM_ADDR_PHYS + 12 * 1024, 28 MAS3_SX|MAS3_SW|MAS3_SR, 0, 29 0, 0, BOOKE_PAGESZ_4K, 0), 30 31 /* TLB 1 */ 32 /* *I*** - Covers boot page */ 33 #if defined(CONFIG_SYS_RAMBOOT) && defined(CONFIG_SYS_INIT_L3_ADDR) 34 /* 35 * *I*G - L3SRAM. When L3 is used as 1M SRAM, the address of the 36 * SRAM is at 0xfff00000, it covered the 0xfffff000. 37 */ 38 SET_TLB_ENTRY(1, CONFIG_SYS_INIT_L3_ADDR, CONFIG_SYS_INIT_L3_ADDR, 39 MAS3_SX|MAS3_SW|MAS3_SR, MAS2_I|MAS2_G, 40 0, 0, BOOKE_PAGESZ_1M, 1), 41 #elif defined(CONFIG_SRIO_PCIE_BOOT_SLAVE) 42 /* 43 * SRIO_PCIE_BOOT-SLAVE. When slave boot, the address of the 44 * space is at 0xfff00000, it covered the 0xfffff000. 45 */ 46 SET_TLB_ENTRY(1, CONFIG_SYS_SRIO_PCIE_BOOT_SLAVE_ADDR, 47 CONFIG_SYS_SRIO_PCIE_BOOT_SLAVE_ADDR_PHYS, 48 MAS3_SX|MAS3_SW|MAS3_SR, MAS2_W|MAS2_G, 49 0, 0, BOOKE_PAGESZ_1M, 1), 50 #else 51 SET_TLB_ENTRY(1, 0xfffff000, 0xfffff000, 52 MAS3_SX|MAS3_SW|MAS3_SR, MAS2_I|MAS2_G, 53 0, 0, BOOKE_PAGESZ_4K, 1), 54 #endif 55 56 /* *I*G* - CCSRBAR */ 57 SET_TLB_ENTRY(1, CONFIG_SYS_CCSRBAR, CONFIG_SYS_CCSRBAR_PHYS, 58 MAS3_SX|MAS3_SW|MAS3_SR, MAS2_I|MAS2_G, 59 0, 1, BOOKE_PAGESZ_16M, 1), 60 61 /* *I*G* - Flash, localbus */ 62 /* This will be changed to *I*G* after relocation to RAM. */ 63 SET_TLB_ENTRY(1, CONFIG_SYS_FLASH_BASE, CONFIG_SYS_FLASH_BASE_PHYS, 64 MAS3_SX|MAS3_SR, MAS2_W|MAS2_G, 65 0, 2, BOOKE_PAGESZ_256M, 1), 66 67 #ifndef CONFIG_SPL_BUILD 68 /* *I*G* - PCIe 1, 0x80000000 */ 69 SET_TLB_ENTRY(1, CONFIG_SYS_PCIE1_MEM_VIRT, CONFIG_SYS_PCIE1_MEM_PHYS, 70 MAS3_SX|MAS3_SW|MAS3_SR, MAS2_I|MAS2_G, 71 0, 3, BOOKE_PAGESZ_512M, 1), 72 73 /* *I*G* - PCIe 2, 0xa0000000 */ 74 SET_TLB_ENTRY(1, CONFIG_SYS_PCIE2_MEM_VIRT, CONFIG_SYS_PCIE2_MEM_PHYS, 75 MAS3_SX|MAS3_SW|MAS3_SR, MAS2_I|MAS2_G, 76 0, 4, BOOKE_PAGESZ_256M, 1), 77 78 /* *I*G* - PCIe 3, 0xb0000000 */ 79 SET_TLB_ENTRY(1, CONFIG_SYS_PCIE3_MEM_VIRT, CONFIG_SYS_PCIE3_MEM_PHYS, 80 MAS3_SX|MAS3_SW|MAS3_SR, MAS2_I|MAS2_G, 81 0, 5, BOOKE_PAGESZ_256M, 1), 82 83 84 /* *I*G* - PCIe 4, 0xc0000000 */ 85 SET_TLB_ENTRY(1, CONFIG_SYS_PCIE4_MEM_VIRT, CONFIG_SYS_PCIE4_MEM_PHYS, 86 MAS3_SX|MAS3_SW|MAS3_SR, MAS2_I|MAS2_G, 87 0, 6, BOOKE_PAGESZ_256M, 1), 88 89 /* *I*G* - PCI I/O */ 90 SET_TLB_ENTRY(1, CONFIG_SYS_PCIE1_IO_VIRT, CONFIG_SYS_PCIE1_IO_PHYS, 91 MAS3_SX|MAS3_SW|MAS3_SR, MAS2_I|MAS2_G, 92 0, 7, BOOKE_PAGESZ_256K, 1), 93 94 /* Bman/Qman */ 95 #ifdef CONFIG_SYS_BMAN_MEM_PHYS 96 SET_TLB_ENTRY(1, CONFIG_SYS_BMAN_MEM_BASE, CONFIG_SYS_BMAN_MEM_PHYS, 97 MAS3_SX|MAS3_SW|MAS3_SR, 0, 98 0, 9, BOOKE_PAGESZ_16M, 1), 99 SET_TLB_ENTRY(1, CONFIG_SYS_BMAN_MEM_BASE + 0x01000000, 100 CONFIG_SYS_BMAN_MEM_PHYS + 0x01000000, 101 MAS3_SX|MAS3_SW|MAS3_SR, MAS2_I|MAS2_G, 102 0, 10, BOOKE_PAGESZ_16M, 1), 103 #endif 104 #ifdef CONFIG_SYS_QMAN_MEM_PHYS 105 SET_TLB_ENTRY(1, CONFIG_SYS_QMAN_MEM_BASE, CONFIG_SYS_QMAN_MEM_PHYS, 106 MAS3_SX|MAS3_SW|MAS3_SR, 0, 107 0, 11, BOOKE_PAGESZ_16M, 1), 108 SET_TLB_ENTRY(1, CONFIG_SYS_QMAN_MEM_BASE + 0x01000000, 109 CONFIG_SYS_QMAN_MEM_PHYS + 0x01000000, 110 MAS3_SX|MAS3_SW|MAS3_SR, MAS2_I|MAS2_G, 111 0, 12, BOOKE_PAGESZ_16M, 1), 112 #endif 113 #endif 114 #ifdef CONFIG_SYS_DCSRBAR_PHYS 115 SET_TLB_ENTRY(1, CONFIG_SYS_DCSRBAR, CONFIG_SYS_DCSRBAR_PHYS, 116 MAS3_SX|MAS3_SW|MAS3_SR, MAS2_I|MAS2_G, 117 0, 13, BOOKE_PAGESZ_32M, 1), 118 #endif 119 #ifdef CONFIG_SYS_NAND_BASE 120 /* 121 * *I*G - NAND 122 * entry 14 and 15 has been used hard coded, they will be disabled 123 * in cpu_init_f, so we use entry 16 for nand. 124 */ 125 SET_TLB_ENTRY(1, CONFIG_SYS_NAND_BASE, CONFIG_SYS_NAND_BASE_PHYS, 126 MAS3_SX|MAS3_SW|MAS3_SR, MAS2_I|MAS2_G, 127 0, 16, BOOKE_PAGESZ_64K, 1), 128 #endif 129 #ifdef CONFIG_SYS_CPLD_BASE 130 SET_TLB_ENTRY(1, CONFIG_SYS_CPLD_BASE, CONFIG_SYS_CPLD_BASE_PHYS, 131 MAS3_SX|MAS3_SW|MAS3_SR, MAS2_I|MAS2_G, 132 0, 17, BOOKE_PAGESZ_4K, 1), 133 #endif 134 #ifdef CONFIG_SRIO_PCIE_BOOT_SLAVE 135 /* 136 * SRIO_PCIE_BOOT-SLAVE. 1M space from 0xffe00000 for 137 * fetching ucode and ENV from master 138 */ 139 SET_TLB_ENTRY(1, CONFIG_SYS_SRIO_PCIE_BOOT_UCODE_ENV_ADDR, 140 CONFIG_SYS_SRIO_PCIE_BOOT_UCODE_ENV_ADDR_PHYS, 141 MAS3_SX|MAS3_SW|MAS3_SR, MAS2_G, 142 0, 18, BOOKE_PAGESZ_1M, 1), 143 #endif 144 #if defined(CONFIG_RAMBOOT_PBL) && !defined(CONFIG_SPL_BUILD) 145 SET_TLB_ENTRY(1, CONFIG_SYS_DDR_SDRAM_BASE, CONFIG_SYS_DDR_SDRAM_BASE, 146 MAS3_SX|MAS3_SW|MAS3_SR, MAS2_M, 147 0, 19, BOOKE_PAGESZ_2G, 1) 148 #endif 149 150 }; 151 152 int num_tlb_entries = ARRAY_SIZE(tlb_table); 153