1 /* SPDX-License-Identifier: GPL-2.0+ */ 2 /* 3 * Copyright 2014 Freescale Semiconductor, Inc. 4 */ 5 6 #ifndef __DDR_H__ 7 #define __DDR_H__ 8 struct board_specific_parameters { 9 u32 n_ranks; 10 u32 datarate_mhz_high; 11 u32 rank_gb; 12 u32 clk_adjust; 13 u32 wrlvl_start; 14 u32 wrlvl_ctl_2; 15 u32 wrlvl_ctl_3; 16 }; 17 18 /* 19 * These tables contain all valid speeds we want to override with board 20 * specific parameters. datarate_mhz_high values need to be in ascending order 21 * for each n_ranks group. 22 */ 23 24 static const struct board_specific_parameters udimm0[] = { 25 /* 26 * memory controller 0 27 * num| hi| rank| clk| wrlvl | wrlvl | wrlvl | 28 * ranks| mhz| GB |adjst| start | ctl2 | ctl3 | 29 */ 30 {2, 1200, 2, 10, 7, 0x0808090a, 0x0b0c0c0a}, 31 {2, 1500, 2, 10, 6, 0x07070809, 0x0a0b0b09}, 32 {2, 1600, 2, 10, 8, 0x0808070b, 0x0c0d0e0a}, 33 {2, 1700, 2, 8, 7, 0x080a0a0c, 0x0c0d0e0a}, 34 {2, 1900, 0, 10, 7, 0x0808080c, 0x0b0c0c09}, 35 {1, 1200, 2, 10, 7, 0x0808090a, 0x0b0c0c0a}, 36 {1, 1500, 2, 10, 6, 0x07070809, 0x0a0b0b09}, 37 {1, 1600, 2, 10, 8, 0x0808070b, 0x0c0d0e0a}, 38 {1, 1700, 2, 8, 7, 0x080a0a0c, 0x0c0d0e0a}, 39 {1, 1900, 0, 10, 7, 0x0808080c, 0x0b0c0c09}, 40 {} 41 }; 42 43 static const struct board_specific_parameters *udimms[] = { 44 udimm0, 45 }; 46 #endif 47