1 /* 2 * Copyright 2014 Freescale Semiconductor, Inc. 3 * 4 * SPDX-License-Identifier: GPL-2.0+ 5 */ 6 7 #ifndef __DDR_H__ 8 #define __DDR_H__ 9 struct board_specific_parameters { 10 u32 n_ranks; 11 u32 datarate_mhz_high; 12 u32 rank_gb; 13 u32 clk_adjust; 14 u32 wrlvl_start; 15 u32 wrlvl_ctl_2; 16 u32 wrlvl_ctl_3; 17 }; 18 19 /* 20 * These tables contain all valid speeds we want to override with board 21 * specific parameters. datarate_mhz_high values need to be in ascending order 22 * for each n_ranks group. 23 */ 24 25 static const struct board_specific_parameters udimm0[] = { 26 /* 27 * memory controller 0 28 * num| hi| rank| clk| wrlvl | wrlvl | wrlvl | 29 * ranks| mhz| GB |adjst| start | ctl2 | ctl3 | 30 */ 31 {2, 1200, 2, 5, 7, 0x0808090a, 0x0b0c0c0a}, 32 {2, 1500, 2, 5, 6, 0x07070809, 0x0a0b0b09}, 33 {2, 1600, 2, 5, 8, 0x0808070b, 0x0c0d0e0a}, 34 {2, 1700, 2, 4, 7, 0x080a0a0c, 0x0c0d0e0a}, 35 {2, 1900, 0, 5, 7, 0x0808080c, 0x0b0c0c09}, 36 {1, 1200, 2, 5, 7, 0x0808090a, 0x0b0c0c0a}, 37 {1, 1500, 2, 5, 6, 0x07070809, 0x0a0b0b09}, 38 {1, 1600, 2, 5, 8, 0x0808070b, 0x0c0d0e0a}, 39 {1, 1700, 2, 4, 7, 0x080a0a0c, 0x0c0d0e0a}, 40 {1, 1900, 0, 5, 7, 0x0808080c, 0x0b0c0c09}, 41 {} 42 }; 43 44 static const struct board_specific_parameters *udimms[] = { 45 udimm0, 46 }; 47 #endif 48