1 // SPDX-License-Identifier: GPL-2.0 2 /* 3 * Copyright 2014 Freescale Semiconductor, Inc. 4 */ 5 6 #include <common.h> 7 #include <i2c.h> 8 #include <hwconfig.h> 9 #include <asm/mmu.h> 10 #include <fsl_ddr_sdram.h> 11 #include <fsl_ddr_dimm_params.h> 12 #include <asm/fsl_law.h> 13 #include "ddr.h" 14 15 DECLARE_GLOBAL_DATA_PTR; 16 17 void fsl_ddr_board_options(memctl_options_t *popts, 18 dimm_params_t *pdimm, 19 unsigned int ctrl_num) 20 { 21 const struct board_specific_parameters *pbsp, *pbsp_highest = NULL; 22 ulong ddr_freq; 23 24 if (ctrl_num > 1) { 25 printf("Not supported controller number %d\n", ctrl_num); 26 return; 27 } 28 if (!pdimm->n_ranks) 29 return; 30 31 pbsp = udimms[0]; 32 33 /* Get clk_adjust, wrlvl_start, wrlvl_ctl, according to the board ddr 34 * freqency and n_banks specified in board_specific_parameters table. 35 */ 36 ddr_freq = get_ddr_freq(0) / 1000000; 37 while (pbsp->datarate_mhz_high) { 38 if (pbsp->n_ranks == pdimm->n_ranks && 39 (pdimm->rank_density >> 30) >= pbsp->rank_gb) { 40 if (ddr_freq <= pbsp->datarate_mhz_high) { 41 popts->clk_adjust = pbsp->clk_adjust; 42 popts->wrlvl_start = pbsp->wrlvl_start; 43 popts->wrlvl_ctl_2 = pbsp->wrlvl_ctl_2; 44 popts->wrlvl_ctl_3 = pbsp->wrlvl_ctl_3; 45 goto found; 46 } 47 pbsp_highest = pbsp; 48 } 49 pbsp++; 50 } 51 52 if (pbsp_highest) { 53 printf("Error: board specific timing not found"); 54 printf("for data rate %lu MT/s\n", ddr_freq); 55 printf("Trying to use the highest speed (%u) parameters\n", 56 pbsp_highest->datarate_mhz_high); 57 popts->clk_adjust = pbsp_highest->clk_adjust; 58 popts->wrlvl_start = pbsp_highest->wrlvl_start; 59 popts->wrlvl_ctl_2 = pbsp->wrlvl_ctl_2; 60 popts->wrlvl_ctl_3 = pbsp->wrlvl_ctl_3; 61 } else { 62 panic("DIMM is not supported by this board"); 63 } 64 found: 65 debug("Found timing match: n_ranks %d, data rate %d, rank_gb %d\n" 66 "\tclk_adjust %d, wrlvl_start %d, wrlvl_ctrl_2 0x%x, " 67 "wrlvl_ctrl_3 0x%x\n", 68 pbsp->n_ranks, pbsp->datarate_mhz_high, pbsp->rank_gb, 69 pbsp->clk_adjust, pbsp->wrlvl_start, pbsp->wrlvl_ctl_2, 70 pbsp->wrlvl_ctl_3); 71 72 /* 73 * Factors to consider for half-strength driver enable: 74 * - number of DIMMs installed 75 */ 76 popts->half_strength_driver_enable = 0; 77 /* 78 * Write leveling override 79 */ 80 popts->wrlvl_override = 1; 81 popts->wrlvl_sample = 0xf; 82 83 /* 84 * Rtt and Rtt_WR override 85 */ 86 popts->rtt_override = 0; 87 88 /* Enable ZQ calibration */ 89 popts->zq_en = 1; 90 91 /* DHC_EN =1, ODT = 75 Ohm */ 92 popts->ddr_cdr1 = DDR_CDR1_DHC_EN | DDR_CDR1_ODT(DDR_CDR_ODT_75ohm); 93 popts->ddr_cdr2 = DDR_CDR2_ODT(DDR_CDR_ODT_75ohm); 94 95 /* optimize cpo for erratum A-009942 */ 96 popts->cpo_sample = 0x54; 97 } 98 99 int dram_init(void) 100 { 101 phys_size_t dram_size; 102 103 #if defined(CONFIG_SPL_BUILD) || !defined(CONFIG_RAMBOOT_PBL) 104 puts("Initializing....using SPD\n"); 105 dram_size = fsl_ddr_sdram(); 106 #else 107 /* DDR has been initialised by first stage boot loader */ 108 dram_size = fsl_ddr_sdram_size(); 109 #endif 110 dram_size = setup_ddr_tlbs(dram_size / 0x100000); 111 dram_size *= 0x100000; 112 113 gd->ram_size = dram_size; 114 115 return 0; 116 } 117