1 /* SPDX-License-Identifier: GPL-2.0+ */
2 /*
3  * Copyright 2013 Freescale Semiconductor, Inc.
4  */
5 
6 #ifndef __T208xQDS_QIXIS_H__
7 #define __T208xQDS_QIXIS_H__
8 
9 /* Definitions of QIXIS Registers for T208xQDS */
10 
11 #define QIXIS_SRDS1CLK_122		0x5a
12 #define QIXIS_SRDS1CLK_125		0x5e
13 
14 
15 /* BRDCFG4[4:7]] select EC1 and EC2 as a pair */
16 #define BRDCFG4_EMISEL_MASK             0xE0
17 #define BRDCFG4_EMISEL_SHIFT            5
18 
19 /* SYSCLK */
20 #define QIXIS_SYSCLK_66                 0x0
21 #define QIXIS_SYSCLK_83                 0x1
22 #define QIXIS_SYSCLK_100                0x2
23 #define QIXIS_SYSCLK_125                0x3
24 #define QIXIS_SYSCLK_133                0x4
25 #define QIXIS_SYSCLK_150                0x5
26 #define QIXIS_SYSCLK_160                0x6
27 #define QIXIS_SYSCLK_166                0x7
28 
29 /* DDRCLK */
30 #define QIXIS_DDRCLK_66                 0x0
31 #define QIXIS_DDRCLK_100                0x1
32 #define QIXIS_DDRCLK_125                0x2
33 #define QIXIS_DDRCLK_133                0x3
34 
35 #define BRDCFG5_IRE                     0x20    /* i2c Remote i2c1 enable */
36 
37 #define BRDCFG9_SFP_TX_EN		0x10
38 
39 #define BRDCFG12_SD3EN_MASK             0x20
40 #define BRDCFG12_SD3MX_MASK             0x08
41 #define BRDCFG12_SD3MX_SLOT5            0x08
42 #define BRDCFG12_SD3MX_SLOT6            0x00
43 #define BRDCFG12_SD4EN_MASK             0x04
44 #define BRDCFG12_SD4MX_MASK             0x03
45 #define BRDCFG12_SD4MX_SLOT7            0x02
46 #define BRDCFG12_SD4MX_SLOT8            0x01
47 #define BRDCFG12_SD4MX_AURO_SATA        0x00
48 #endif
49