1 /* 2 * Copyright 2013 Freescale Semiconductor, Inc. 3 * 4 * SPDX-License-Identifier: GPL-2.0+ 5 */ 6 7 #ifndef __T208xQDS_QIXIS_H__ 8 #define __T208xQDS_QIXIS_H__ 9 10 /* Definitions of QIXIS Registers for T208xQDS */ 11 12 #define QIXIS_SRDS1CLK_122 0x5a 13 #define QIXIS_SRDS1CLK_125 0x5e 14 15 16 /* BRDCFG4[4:7]] select EC1 and EC2 as a pair */ 17 #define BRDCFG4_EMISEL_MASK 0xE0 18 #define BRDCFG4_EMISEL_SHIFT 5 19 20 /* SYSCLK */ 21 #define QIXIS_SYSCLK_66 0x0 22 #define QIXIS_SYSCLK_83 0x1 23 #define QIXIS_SYSCLK_100 0x2 24 #define QIXIS_SYSCLK_125 0x3 25 #define QIXIS_SYSCLK_133 0x4 26 #define QIXIS_SYSCLK_150 0x5 27 #define QIXIS_SYSCLK_160 0x6 28 #define QIXIS_SYSCLK_166 0x7 29 30 /* DDRCLK */ 31 #define QIXIS_DDRCLK_66 0x0 32 #define QIXIS_DDRCLK_100 0x1 33 #define QIXIS_DDRCLK_125 0x2 34 #define QIXIS_DDRCLK_133 0x3 35 36 #define BRDCFG5_IRE 0x20 /* i2c Remote i2c1 enable */ 37 38 #define BRDCFG9_SFP_TX_EN 0x10 39 40 #define BRDCFG12_SD3EN_MASK 0x20 41 #define BRDCFG12_SD3MX_MASK 0x08 42 #define BRDCFG12_SD3MX_SLOT5 0x08 43 #define BRDCFG12_SD3MX_SLOT6 0x00 44 #define BRDCFG12_SD4EN_MASK 0x04 45 #define BRDCFG12_SD4MX_MASK 0x03 46 #define BRDCFG12_SD4MX_SLOT7 0x02 47 #define BRDCFG12_SD4MX_SLOT8 0x01 48 #define BRDCFG12_SD4MX_AURO_SATA 0x00 49 #endif 50