1 /*
2  * Copyright 2009-2013 Freescale Semiconductor, Inc.
3  *
4  * SPDX-License-Identifier:     GPL-2.0+
5  */
6 
7 #include <common.h>
8 #include <command.h>
9 #include <i2c.h>
10 #include <netdev.h>
11 #include <linux/compiler.h>
12 #include <asm/mmu.h>
13 #include <asm/processor.h>
14 #include <asm/immap_85xx.h>
15 #include <asm/fsl_law.h>
16 #include <asm/fsl_serdes.h>
17 #include <asm/fsl_portals.h>
18 #include <asm/fsl_liodn.h>
19 #include <fm_eth.h>
20 
21 #include "../common/qixis.h"
22 #include "../common/vsc3316_3308.h"
23 #include "../common/vid.h"
24 #include "t208xqds.h"
25 #include "t208xqds_qixis.h"
26 
27 DECLARE_GLOBAL_DATA_PTR;
28 
29 int checkboard(void)
30 {
31 	char buf[64];
32 	u8 sw;
33 	struct cpu_type *cpu = gd->arch.cpu;
34 	static const char *freq[4] = {
35 		"100.00MHZ(from 8T49N222A)", "125.00MHz",
36 		"156.25MHZ", "100.00MHz"
37 	};
38 
39 	printf("Board: %sQDS, ", cpu->name);
40 	sw = QIXIS_READ(arch);
41 	printf("Sys ID: 0x%02x, Board Arch: V%d, ", QIXIS_READ(id), sw >> 4);
42 	printf("Board Version: %c, boot from ", (sw & 0xf) + 'A' - 1);
43 
44 #ifdef CONFIG_SDCARD
45 	puts("SD/MMC\n");
46 #elif CONFIG_SPIFLASH
47 	puts("SPI\n");
48 #else
49 	sw = QIXIS_READ(brdcfg[0]);
50 	sw = (sw & QIXIS_LBMAP_MASK) >> QIXIS_LBMAP_SHIFT;
51 
52 	if (sw < 0x8)
53 		printf("vBank%d\n", sw);
54 	else if (sw == 0x8)
55 		puts("Promjet\n");
56 	else if (sw == 0x9)
57 		puts("NAND\n");
58 	else
59 		printf("invalid setting of SW%u\n", QIXIS_LBMAP_SWITCH);
60 #endif
61 
62 	printf("FPGA: v%d (%s), build %d", (int)QIXIS_READ(scver),
63 	       qixis_read_tag(buf), (int)qixis_read_minor());
64 	/* the timestamp string contains "\n" at the end */
65 	printf(" on %s", qixis_read_time(buf));
66 
67 	puts("SERDES Reference Clocks:\n");
68 	sw = QIXIS_READ(brdcfg[2]);
69 	printf("SD1_CLK1=%s, SD1_CLK2=%s\n", freq[sw >> 6],
70 	       freq[(sw >> 4) & 0x3]);
71 	printf("SD2_CLK1=%s, SD2_CLK2=%s\n", freq[(sw & 0xf) >> 2],
72 	       freq[sw & 0x3]);
73 
74 	return 0;
75 }
76 
77 int select_i2c_ch_pca9547(u8 ch)
78 {
79 	int ret;
80 
81 	ret = i2c_write(I2C_MUX_PCA_ADDR_PRI, 0, 1, &ch, 1);
82 	if (ret) {
83 		puts("PCA: failed to select proper channel\n");
84 		return ret;
85 	}
86 
87 	return 0;
88 }
89 
90 int i2c_multiplexer_select_vid_channel(u8 channel)
91 {
92 	return select_i2c_ch_pca9547(channel);
93 }
94 
95 int brd_mux_lane_to_slot(void)
96 {
97 	ccsr_gur_t *gur = (void *)(CONFIG_SYS_MPC85xx_GUTS_ADDR);
98 	u32 srds_prtcl_s1;
99 
100 	srds_prtcl_s1 = in_be32(&gur->rcwsr[4]) &
101 				FSL_CORENET2_RCWSR4_SRDS1_PRTCL;
102 	srds_prtcl_s1 >>= FSL_CORENET2_RCWSR4_SRDS1_PRTCL_SHIFT;
103 #if defined(CONFIG_T2080QDS)
104 	u32 srds_prtcl_s2 = in_be32(&gur->rcwsr[4]) &
105 				FSL_CORENET2_RCWSR4_SRDS2_PRTCL;
106 	srds_prtcl_s2 >>= FSL_CORENET2_RCWSR4_SRDS2_PRTCL_SHIFT;
107 #endif
108 
109 	switch (srds_prtcl_s1) {
110 	case 0:
111 		/* SerDes1 is not enabled */
112 		break;
113 #if defined(CONFIG_T2080QDS)
114 	case 0x1b:
115 	case 0x1c:
116 	case 0xa2:
117 		/* SD1(A:D) => SLOT3 SGMII
118 		 * SD1(G:H) => SLOT1 SGMII
119 		 */
120 		QIXIS_WRITE(brdcfg[12], 0x1a);
121 		break;
122 	case 0x94:
123 	case 0x95:
124 		/* SD1(A:B) => SLOT3 SGMII@1.25bps
125 		 * SD1(C:D) => SFP Module, SGMII@3.125bps
126 		 * SD1(E:H) => SLOT1 SGMII@1.25bps
127 		 */
128 	case 0x96:
129 		/* SD1(A:B) => SLOT3 SGMII@1.25bps
130 		 * SD1(C)   => SFP Module, SGMII@3.125bps
131 		 * SD1(D)   => SFP Module, SGMII@1.25bps
132 		 * SD1(E:H) => SLOT1 PCIe4 x4
133 		 */
134 		QIXIS_WRITE(brdcfg[12], 0x3a);
135 		break;
136 	case 0x50:
137 	case 0x51:
138 		/* SD1(A:D) => SLOT3 XAUI
139 		 * SD1(E)   => SLOT1 PCIe4
140 		 * SD1(F:H) => SLOT2 SGMII
141 		 */
142 		QIXIS_WRITE(brdcfg[12], 0x15);
143 		break;
144 	case 0x66:
145 	case 0x67:
146 		/* SD1(A:D) => XFI cage
147 		 * SD1(E:H) => SLOT1 PCIe4
148 		 */
149 		QIXIS_WRITE(brdcfg[12], 0xfe);
150 		break;
151 	case 0x6a:
152 	case 0x6b:
153 		/* SD1(A:D) => XFI cage
154 		 * SD1(E)   => SLOT1 PCIe4
155 		 * SD1(F:H) => SLOT2 SGMII
156 		 */
157 		QIXIS_WRITE(brdcfg[12], 0xf1);
158 		break;
159 	case 0x6c:
160 	case 0x6d:
161 		/* SD1(A:B) => XFI cage
162 		 * SD1(C:D) => SLOT3 SGMII
163 		 * SD1(E:H) => SLOT1 PCIe4
164 		 */
165 		QIXIS_WRITE(brdcfg[12], 0xda);
166 		break;
167 	case 0x6e:
168 		/* SD1(A:B) => SFP Module, XFI
169 		 * SD1(C:D) => SLOT3 SGMII
170 		 * SD1(E:F) => SLOT1 PCIe4 x2
171 		 * SD1(G:H) => SLOT2 SGMII
172 		 */
173 		QIXIS_WRITE(brdcfg[12], 0xd9);
174 		break;
175 	case 0xda:
176 		/* SD1(A:H) => SLOT3 PCIe3 x8
177 		 */
178 		 QIXIS_WRITE(brdcfg[12], 0x0);
179 		 break;
180 	case 0xc8:
181 		/* SD1(A)   => SLOT3 PCIe3 x1
182 		 * SD1(B)   => SFP Module, SGMII@1.25bps
183 		 * SD1(C:D) => SFP Module, SGMII@3.125bps
184 		 * SD1(E:F) => SLOT1 PCIe4 x2
185 		 * SD1(G:H) => SLOT2 SGMII
186 		 */
187 		 QIXIS_WRITE(brdcfg[12], 0x79);
188 		 break;
189 	case 0xab:
190 		/* SD1(A:D) => SLOT3 PCIe3 x4
191 		 * SD1(E:H) => SLOT1 PCIe4 x4
192 		 */
193 		 QIXIS_WRITE(brdcfg[12], 0x1a);
194 		 break;
195 #elif defined(CONFIG_T2081QDS)
196 	case 0x50:
197 	case 0x51:
198 		/* SD1(A:D) => SLOT2 XAUI
199 		 * SD1(E)   => SLOT1 PCIe4 x1
200 		 * SD1(F:H) => SLOT3 SGMII
201 		 */
202 		QIXIS_WRITE(brdcfg[12], 0x98);
203 		QIXIS_WRITE(brdcfg[13], 0x70);
204 		break;
205 	case 0x6a:
206 	case 0x6b:
207 		/* SD1(A:D) => XFI SFP Module
208 		 * SD1(E)   => SLOT1 PCIe4 x1
209 		 * SD1(F:H) => SLOT3 SGMII
210 		 */
211 		QIXIS_WRITE(brdcfg[12], 0x80);
212 		QIXIS_WRITE(brdcfg[13], 0x70);
213 		break;
214 	case 0x6c:
215 	case 0x6d:
216 		/* SD1(A:B) => XFI SFP Module
217 		 * SD1(C:D) => SLOT2 SGMII
218 		 * SD1(E:H) => SLOT1 PCIe4 x4
219 		 */
220 		QIXIS_WRITE(brdcfg[12], 0xe8);
221 		QIXIS_WRITE(brdcfg[13], 0x0);
222 		break;
223 	case 0xaa:
224 	case 0xab:
225 		/* SD1(A:D) => SLOT2 PCIe3 x4
226 		 * SD1(F:H) => SLOT1 SGMI4 x4
227 		 */
228 		QIXIS_WRITE(brdcfg[12], 0xf8);
229 		QIXIS_WRITE(brdcfg[13], 0x0);
230 		break;
231 	case 0xca:
232 	case 0xcb:
233 		/* SD1(A)   => SLOT2 PCIe3 x1
234 		 * SD1(B)   => SLOT7 SGMII
235 		 * SD1(C)   => SLOT6 SGMII
236 		 * SD1(D)   => SLOT5 SGMII
237 		 * SD1(E)   => SLOT1 PCIe4 x1
238 		 * SD1(F:H) => SLOT3 SGMII
239 		 */
240 		QIXIS_WRITE(brdcfg[12], 0x80);
241 		QIXIS_WRITE(brdcfg[13], 0x70);
242 		break;
243 	case 0xde:
244 	case 0xdf:
245 		/* SD1(A:D) => SLOT2 PCIe3 x4
246 		 * SD1(E)   => SLOT1 PCIe4 x1
247 		 * SD1(F)   => SLOT4 PCIe1 x1
248 		 * SD1(G)   => SLOT3 PCIe2 x1
249 		 * SD1(H)   => SLOT7 SGMII
250 		 */
251 		QIXIS_WRITE(brdcfg[12], 0x98);
252 		QIXIS_WRITE(brdcfg[13], 0x25);
253 		break;
254 	case 0xf2:
255 		/* SD1(A)   => SLOT2 PCIe3 x1
256 		 * SD1(B:D) => SLOT7 SGMII
257 		 * SD1(E)   => SLOT1 PCIe4 x1
258 		 * SD1(F)   => SLOT4 PCIe1 x1
259 		 * SD1(G)   => SLOT3 PCIe2 x1
260 		 * SD1(H)   => SLOT7 SGMII
261 		 */
262 		QIXIS_WRITE(brdcfg[12], 0x81);
263 		QIXIS_WRITE(brdcfg[13], 0xa5);
264 		break;
265 #endif
266 	default:
267 		printf("WARNING: unsupported for SerDes1 Protocol %d\n",
268 		       srds_prtcl_s1);
269 		return -1;
270 	}
271 
272 #ifdef CONFIG_T2080QDS
273 	switch (srds_prtcl_s2) {
274 	case 0:
275 		/* SerDes2 is not enabled */
276 		break;
277 	case 0x01:
278 	case 0x02:
279 		/* SD2(A:H) => SLOT4 PCIe1 */
280 		QIXIS_WRITE(brdcfg[13], 0x10);
281 		break;
282 	case 0x15:
283 	case 0x16:
284 		/*
285 		 * SD2(A:D) => SLOT4 PCIe1
286 		 * SD2(E:F) => SLOT5 PCIe2
287 		 * SD2(G:H) => SATA1,SATA2
288 		 */
289 		QIXIS_WRITE(brdcfg[13], 0xb0);
290 		break;
291 	case 0x18:
292 		/*
293 		 * SD2(A:D) => SLOT4 PCIe1
294 		 * SD2(E:F) => SLOT5 Aurora
295 		 * SD2(G:H) => SATA1,SATA2
296 		 */
297 		QIXIS_WRITE(brdcfg[13], 0x78);
298 		break;
299 	case 0x1f:
300 		/*
301 		 * SD2(A:D) => SLOT4 PCIe1
302 		 * SD2(E:H) => SLOT5 PCIe2
303 		 */
304 		QIXIS_WRITE(brdcfg[13], 0xa0);
305 		break;
306 	case 0x29:
307 	case 0x2d:
308 	case 0x2e:
309 		/*
310 		 * SD2(A:D) => SLOT4 SRIO2
311 		 * SD2(E:H) => SLOT5 SRIO1
312 		 */
313 		QIXIS_WRITE(brdcfg[13], 0xa0);
314 		break;
315 	case 0x36:
316 		/*
317 		 * SD2(A:D) => SLOT4 SRIO2
318 		 * SD2(E:F) => Aurora
319 		 * SD2(G:H) => SATA1,SATA2
320 		 */
321 		QIXIS_WRITE(brdcfg[13], 0x78);
322 		break;
323 	default:
324 		printf("WARNING: unsupported for SerDes2 Protocol %d\n",
325 		       srds_prtcl_s2);
326 		return -1;
327 	}
328 #endif
329 	return 0;
330 }
331 
332 int board_early_init_r(void)
333 {
334 	const unsigned int flashbase = CONFIG_SYS_FLASH_BASE;
335 	int flash_esel = find_tlb_idx((void *)flashbase, 1);
336 
337 	/*
338 	 * Remap Boot flash + PROMJET region to caching-inhibited
339 	 * so that flash can be erased properly.
340 	 */
341 
342 	/* Flush d-cache and invalidate i-cache of any FLASH data */
343 	flush_dcache();
344 	invalidate_icache();
345 
346 	if (flash_esel == -1) {
347 		/* very unlikely unless something is messed up */
348 		puts("Error: Could not find TLB for FLASH BASE\n");
349 		flash_esel = 2;	/* give our best effort to continue */
350 	} else {
351 		/* invalidate existing TLB entry for flash + promjet */
352 		disable_tlb(flash_esel);
353 	}
354 
355 	set_tlb(1, flashbase, CONFIG_SYS_FLASH_BASE_PHYS,
356 		MAS3_SX|MAS3_SW|MAS3_SR, MAS2_I|MAS2_G,
357 		0, flash_esel, BOOKE_PAGESZ_256M, 1);
358 
359 	set_liodns();
360 #ifdef CONFIG_SYS_DPAA_QBMAN
361 	setup_portals();
362 #endif
363 
364 	/* Disable remote I2C connection to qixis fpga */
365 	QIXIS_WRITE(brdcfg[5], QIXIS_READ(brdcfg[5]) & ~BRDCFG5_IRE);
366 
367 	/*
368 	 * Adjust core voltage according to voltage ID
369 	 * This function changes I2C mux to channel 2.
370 	 */
371 	if (adjust_vdd(0))
372 		printf("Warning: Adjusting core voltage failed.\n");
373 
374 	brd_mux_lane_to_slot();
375 	select_i2c_ch_pca9547(I2C_MUX_CH_DEFAULT);
376 
377 	return 0;
378 }
379 
380 unsigned long get_board_sys_clk(void)
381 {
382 	u8 sysclk_conf = QIXIS_READ(brdcfg[1]);
383 #ifdef CONFIG_FSL_QIXIS_CLOCK_MEASUREMENT
384 	/* use accurate clock measurement */
385 	int freq = QIXIS_READ(clk_freq[0]) << 8 | QIXIS_READ(clk_freq[1]);
386 	int base = QIXIS_READ(clk_base[0]) << 8 | QIXIS_READ(clk_base[1]);
387 	u32 val;
388 
389 	val =  freq * base;
390 	if (val) {
391 		debug("SYS Clock measurement is: %d\n", val);
392 		return val;
393 	} else {
394 		printf("Warning: SYS clock measurement is invalid, ");
395 		printf("using value from brdcfg1.\n");
396 	}
397 #endif
398 
399 	switch (sysclk_conf & 0x0F) {
400 	case QIXIS_SYSCLK_83:
401 		return 83333333;
402 	case QIXIS_SYSCLK_100:
403 		return 100000000;
404 	case QIXIS_SYSCLK_125:
405 		return 125000000;
406 	case QIXIS_SYSCLK_133:
407 		return 133333333;
408 	case QIXIS_SYSCLK_150:
409 		return 150000000;
410 	case QIXIS_SYSCLK_160:
411 		return 160000000;
412 	case QIXIS_SYSCLK_166:
413 		return 166666666;
414 	}
415 	return 66666666;
416 }
417 
418 unsigned long get_board_ddr_clk(void)
419 {
420 	u8 ddrclk_conf = QIXIS_READ(brdcfg[1]);
421 #ifdef CONFIG_FSL_QIXIS_CLOCK_MEASUREMENT
422 	/* use accurate clock measurement */
423 	int freq = QIXIS_READ(clk_freq[2]) << 8 | QIXIS_READ(clk_freq[3]);
424 	int base = QIXIS_READ(clk_base[0]) << 8 | QIXIS_READ(clk_base[1]);
425 	u32 val;
426 
427 	val =  freq * base;
428 	if (val) {
429 		debug("DDR Clock measurement is: %d\n", val);
430 		return val;
431 	} else {
432 		printf("Warning: DDR clock measurement is invalid, ");
433 		printf("using value from brdcfg1.\n");
434 	}
435 #endif
436 
437 	switch ((ddrclk_conf & 0x30) >> 4) {
438 	case QIXIS_DDRCLK_100:
439 		return 100000000;
440 	case QIXIS_DDRCLK_125:
441 		return 125000000;
442 	case QIXIS_DDRCLK_133:
443 		return 133333333;
444 	}
445 	return 66666666;
446 }
447 
448 int misc_init_r(void)
449 {
450 	return 0;
451 }
452 
453 int ft_board_setup(void *blob, bd_t *bd)
454 {
455 	phys_addr_t base;
456 	phys_size_t size;
457 
458 	ft_cpu_setup(blob, bd);
459 
460 	base = getenv_bootm_low();
461 	size = getenv_bootm_size();
462 
463 	fdt_fixup_memory(blob, (u64)base, (u64)size);
464 
465 #ifdef CONFIG_PCI
466 	pci_of_setup(blob, bd);
467 #endif
468 
469 	fdt_fixup_liodn(blob);
470 	fdt_fixup_dr_usb(blob, bd);
471 
472 #ifdef CONFIG_SYS_DPAA_FMAN
473 	fdt_fixup_fman_ethernet(blob);
474 	fdt_fixup_board_enet(blob);
475 #endif
476 
477 	return 0;
478 }
479