1 /*
2  * Copyright 2009-2013 Freescale Semiconductor, Inc.
3  *
4  * SPDX-License-Identifier:     GPL-2.0+
5  */
6 
7 #include <common.h>
8 #include <command.h>
9 #include <i2c.h>
10 #include <netdev.h>
11 #include <linux/compiler.h>
12 #include <asm/mmu.h>
13 #include <asm/processor.h>
14 #include <asm/immap_85xx.h>
15 #include <asm/fsl_law.h>
16 #include <asm/fsl_serdes.h>
17 #include <asm/fsl_portals.h>
18 #include <asm/fsl_liodn.h>
19 #include <fm_eth.h>
20 
21 #include "../common/qixis.h"
22 #include "../common/vsc3316_3308.h"
23 #include "t208xqds.h"
24 #include "t208xqds_qixis.h"
25 
26 DECLARE_GLOBAL_DATA_PTR;
27 
28 int checkboard(void)
29 {
30 	char buf[64];
31 	u8 sw;
32 	struct cpu_type *cpu = gd->arch.cpu;
33 	static const char *freq[4] = {
34 		"100.00MHZ(from 8T49N222A)", "125.00MHz",
35 		"156.25MHZ", "100.00MHz"
36 	};
37 
38 	printf("Board: %sQDS, ", cpu->name);
39 	sw = QIXIS_READ(arch);
40 	printf("Sys ID: 0x%02x, Board Arch: V%d, ", QIXIS_READ(id), sw >> 4);
41 	printf("Board Version: %c, boot from ", (sw & 0xf) + 'A' - 1);
42 
43 #ifdef CONFIG_SDCARD
44 	puts("SD/MMC\n");
45 #elif CONFIG_SPIFLASH
46 	puts("SPI\n");
47 #else
48 	sw = QIXIS_READ(brdcfg[0]);
49 	sw = (sw & QIXIS_LBMAP_MASK) >> QIXIS_LBMAP_SHIFT;
50 
51 	if (sw < 0x8)
52 		printf("vBank%d\n", sw);
53 	else if (sw == 0x8)
54 		puts("Promjet\n");
55 	else if (sw == 0x9)
56 		puts("NAND\n");
57 	else
58 		printf("invalid setting of SW%u\n", QIXIS_LBMAP_SWITCH);
59 #endif
60 
61 	printf("FPGA: v%d (%s), build %d", (int)QIXIS_READ(scver),
62 	       qixis_read_tag(buf), (int)qixis_read_minor());
63 	/* the timestamp string contains "\n" at the end */
64 	printf(" on %s", qixis_read_time(buf));
65 
66 	puts("SERDES Reference Clocks:\n");
67 	sw = QIXIS_READ(brdcfg[2]);
68 	printf("SD1_CLK1=%s, SD1_CLK2=%s\n", freq[sw >> 6],
69 	       freq[(sw >> 4) & 0x3]);
70 	printf("SD2_CLK1=%s, SD2_CLK2=%s\n", freq[(sw & 0xf) >> 2],
71 	       freq[sw & 0x3]);
72 
73 	return 0;
74 }
75 
76 int select_i2c_ch_pca9547(u8 ch)
77 {
78 	int ret;
79 
80 	ret = i2c_write(I2C_MUX_PCA_ADDR_PRI, 0, 1, &ch, 1);
81 	if (ret) {
82 		puts("PCA: failed to select proper channel\n");
83 		return ret;
84 	}
85 
86 	return 0;
87 }
88 
89 int brd_mux_lane_to_slot(void)
90 {
91 	ccsr_gur_t *gur = (void *)(CONFIG_SYS_MPC85xx_GUTS_ADDR);
92 	u32 srds_prtcl_s1;
93 
94 	srds_prtcl_s1 = in_be32(&gur->rcwsr[4]) &
95 				FSL_CORENET2_RCWSR4_SRDS1_PRTCL;
96 	srds_prtcl_s1 >>= FSL_CORENET2_RCWSR4_SRDS1_PRTCL_SHIFT;
97 #if defined(CONFIG_T2080QDS)
98 	u32 srds_prtcl_s2 = in_be32(&gur->rcwsr[4]) &
99 				FSL_CORENET2_RCWSR4_SRDS2_PRTCL;
100 	srds_prtcl_s2 >>= FSL_CORENET2_RCWSR4_SRDS2_PRTCL_SHIFT;
101 #endif
102 
103 	switch (srds_prtcl_s1) {
104 	case 0:
105 		/* SerDes1 is not enabled */
106 		break;
107 #if defined(CONFIG_T2080QDS)
108 	case 0x1b:
109 	case 0x1c:
110 	case 0xa2:
111 		/* SD1(A:D) => SLOT3 SGMII
112 		 * SD1(G:H) => SLOT1 SGMII
113 		 */
114 		QIXIS_WRITE(brdcfg[12], 0x1a);
115 		break;
116 	case 0x94:
117 	case 0x95:
118 		/* SD1(A:B) => SLOT3 SGMII@1.25bps
119 		 * SD1(C:D) => SFP Module, SGMII@3.125bps
120 		 * SD1(E:H) => SLOT1 SGMII@1.25bps
121 		 */
122 	case 0x96:
123 		/* SD1(A:B) => SLOT3 SGMII@1.25bps
124 		 * SD1(C)   => SFP Module, SGMII@3.125bps
125 		 * SD1(D)   => SFP Module, SGMII@1.25bps
126 		 * SD1(E:H) => SLOT1 PCIe4 x4
127 		 */
128 		QIXIS_WRITE(brdcfg[12], 0x3a);
129 		break;
130 	case 0x50:
131 	case 0x51:
132 		/* SD1(A:D) => SLOT3 XAUI
133 		 * SD1(E)   => SLOT1 PCIe4
134 		 * SD1(F:H) => SLOT2 SGMII
135 		 */
136 		QIXIS_WRITE(brdcfg[12], 0x15);
137 		break;
138 	case 0x66:
139 	case 0x67:
140 		/* SD1(A:D) => XFI cage
141 		 * SD1(E:H) => SLOT1 PCIe4
142 		 */
143 		QIXIS_WRITE(brdcfg[12], 0xfe);
144 		break;
145 	case 0x6a:
146 	case 0x6b:
147 		/* SD1(A:D) => XFI cage
148 		 * SD1(E)   => SLOT1 PCIe4
149 		 * SD1(F:H) => SLOT2 SGMII
150 		 */
151 		QIXIS_WRITE(brdcfg[12], 0xf1);
152 		break;
153 	case 0x6c:
154 	case 0x6d:
155 		/* SD1(A:B) => XFI cage
156 		 * SD1(C:D) => SLOT3 SGMII
157 		 * SD1(E:H) => SLOT1 PCIe4
158 		 */
159 		QIXIS_WRITE(brdcfg[12], 0xda);
160 		break;
161 	case 0x6e:
162 		/* SD1(A:B) => SFP Module, XFI
163 		 * SD1(C:D) => SLOT3 SGMII
164 		 * SD1(E:F) => SLOT1 PCIe4 x2
165 		 * SD1(G:H) => SLOT2 SGMII
166 		 */
167 		QIXIS_WRITE(brdcfg[12], 0xd9);
168 		break;
169 	case 0xda:
170 		/* SD1(A:H) => SLOT3 PCIe3 x8
171 		 */
172 		 QIXIS_WRITE(brdcfg[12], 0x0);
173 		 break;
174 	case 0xc8:
175 		/* SD1(A)   => SLOT3 PCIe3 x1
176 		 * SD1(B)   => SFP Module, SGMII@1.25bps
177 		 * SD1(C:D) => SFP Module, SGMII@3.125bps
178 		 * SD1(E:F) => SLOT1 PCIe4 x2
179 		 * SD1(G:H) => SLOT2 SGMII
180 		 */
181 		 QIXIS_WRITE(brdcfg[12], 0x79);
182 		 break;
183 	case 0xab:
184 		/* SD1(A:D) => SLOT3 PCIe3 x4
185 		 * SD1(E:H) => SLOT1 PCIe4 x4
186 		 */
187 		 QIXIS_WRITE(brdcfg[12], 0x1a);
188 		 break;
189 #elif defined(CONFIG_T2081QDS)
190 	case 0x50:
191 	case 0x51:
192 		/* SD1(A:D) => SLOT2 XAUI
193 		 * SD1(E)   => SLOT1 PCIe4 x1
194 		 * SD1(F:H) => SLOT3 SGMII
195 		 */
196 		QIXIS_WRITE(brdcfg[12], 0x98);
197 		QIXIS_WRITE(brdcfg[13], 0x70);
198 		break;
199 	case 0x6a:
200 	case 0x6b:
201 		/* SD1(A:D) => XFI SFP Module
202 		 * SD1(E)   => SLOT1 PCIe4 x1
203 		 * SD1(F:H) => SLOT3 SGMII
204 		 */
205 		QIXIS_WRITE(brdcfg[12], 0x80);
206 		QIXIS_WRITE(brdcfg[13], 0x70);
207 		break;
208 	case 0x6c:
209 	case 0x6d:
210 		/* SD1(A:B) => XFI SFP Module
211 		 * SD1(C:D) => SLOT2 SGMII
212 		 * SD1(E:H) => SLOT1 PCIe4 x4
213 		 */
214 		QIXIS_WRITE(brdcfg[12], 0xe8);
215 		QIXIS_WRITE(brdcfg[13], 0x0);
216 		break;
217 	case 0xaa:
218 	case 0xab:
219 		/* SD1(A:D) => SLOT2 PCIe3 x4
220 		 * SD1(F:H) => SLOT1 SGMI4 x4
221 		 */
222 		QIXIS_WRITE(brdcfg[12], 0xf8);
223 		QIXIS_WRITE(brdcfg[13], 0x0);
224 		break;
225 	case 0xca:
226 	case 0xcb:
227 		/* SD1(A)   => SLOT2 PCIe3 x1
228 		 * SD1(B)   => SLOT7 SGMII
229 		 * SD1(C)   => SLOT6 SGMII
230 		 * SD1(D)   => SLOT5 SGMII
231 		 * SD1(E)   => SLOT1 PCIe4 x1
232 		 * SD1(F:H) => SLOT3 SGMII
233 		 */
234 		QIXIS_WRITE(brdcfg[12], 0x80);
235 		QIXIS_WRITE(brdcfg[13], 0x70);
236 		break;
237 	case 0xde:
238 	case 0xdf:
239 		/* SD1(A:D) => SLOT2 PCIe3 x4
240 		 * SD1(E)   => SLOT1 PCIe4 x1
241 		 * SD1(F)   => SLOT4 PCIe1 x1
242 		 * SD1(G)   => SLOT3 PCIe2 x1
243 		 * SD1(H)   => SLOT7 SGMII
244 		 */
245 		QIXIS_WRITE(brdcfg[12], 0x98);
246 		QIXIS_WRITE(brdcfg[13], 0x25);
247 		break;
248 	case 0xf2:
249 		/* SD1(A)   => SLOT2 PCIe3 x1
250 		 * SD1(B:D) => SLOT7 SGMII
251 		 * SD1(E)   => SLOT1 PCIe4 x1
252 		 * SD1(F)   => SLOT4 PCIe1 x1
253 		 * SD1(G)   => SLOT3 PCIe2 x1
254 		 * SD1(H)   => SLOT7 SGMII
255 		 */
256 		QIXIS_WRITE(brdcfg[12], 0x81);
257 		QIXIS_WRITE(brdcfg[13], 0xa5);
258 		break;
259 #endif
260 	default:
261 		printf("WARNING: unsupported for SerDes1 Protocol %d\n",
262 		       srds_prtcl_s1);
263 		return -1;
264 	}
265 
266 #ifdef CONFIG_T2080QDS
267 	switch (srds_prtcl_s2) {
268 	case 0:
269 		/* SerDes2 is not enabled */
270 		break;
271 	case 0x01:
272 	case 0x02:
273 		/* SD2(A:H) => SLOT4 PCIe1 */
274 		QIXIS_WRITE(brdcfg[13], 0x10);
275 		break;
276 	case 0x15:
277 	case 0x16:
278 		/*
279 		 * SD2(A:D) => SLOT4 PCIe1
280 		 * SD2(E:F) => SLOT5 PCIe2
281 		 * SD2(G:H) => SATA1,SATA2
282 		 */
283 		QIXIS_WRITE(brdcfg[13], 0xb0);
284 		break;
285 	case 0x18:
286 		/*
287 		 * SD2(A:D) => SLOT4 PCIe1
288 		 * SD2(E:F) => SLOT5 Aurora
289 		 * SD2(G:H) => SATA1,SATA2
290 		 */
291 		QIXIS_WRITE(brdcfg[13], 0x78);
292 		break;
293 	case 0x1f:
294 		/*
295 		 * SD2(A:D) => SLOT4 PCIe1
296 		 * SD2(E:H) => SLOT5 PCIe2
297 		 */
298 		QIXIS_WRITE(brdcfg[13], 0xa0);
299 		break;
300 	case 0x29:
301 	case 0x2d:
302 	case 0x2e:
303 		/*
304 		 * SD2(A:D) => SLOT4 SRIO2
305 		 * SD2(E:H) => SLOT5 SRIO1
306 		 */
307 		QIXIS_WRITE(brdcfg[13], 0xa0);
308 		break;
309 	case 0x36:
310 		/*
311 		 * SD2(A:D) => SLOT4 SRIO2
312 		 * SD2(E:F) => Aurora
313 		 * SD2(G:H) => SATA1,SATA2
314 		 */
315 		QIXIS_WRITE(brdcfg[13], 0x78);
316 		break;
317 	default:
318 		printf("WARNING: unsupported for SerDes2 Protocol %d\n",
319 		       srds_prtcl_s2);
320 		return -1;
321 	}
322 #endif
323 	return 0;
324 }
325 
326 int board_early_init_r(void)
327 {
328 	const unsigned int flashbase = CONFIG_SYS_FLASH_BASE;
329 	int flash_esel = find_tlb_idx((void *)flashbase, 1);
330 
331 	/*
332 	 * Remap Boot flash + PROMJET region to caching-inhibited
333 	 * so that flash can be erased properly.
334 	 */
335 
336 	/* Flush d-cache and invalidate i-cache of any FLASH data */
337 	flush_dcache();
338 	invalidate_icache();
339 
340 	if (flash_esel == -1) {
341 		/* very unlikely unless something is messed up */
342 		puts("Error: Could not find TLB for FLASH BASE\n");
343 		flash_esel = 2;	/* give our best effort to continue */
344 	} else {
345 		/* invalidate existing TLB entry for flash + promjet */
346 		disable_tlb(flash_esel);
347 	}
348 
349 	set_tlb(1, flashbase, CONFIG_SYS_FLASH_BASE_PHYS,
350 		MAS3_SX|MAS3_SW|MAS3_SR, MAS2_I|MAS2_G,
351 		0, flash_esel, BOOKE_PAGESZ_256M, 1);
352 
353 	set_liodns();
354 #ifdef CONFIG_SYS_DPAA_QBMAN
355 	setup_portals();
356 #endif
357 
358 	/* Disable remote I2C connection to qixis fpga */
359 	QIXIS_WRITE(brdcfg[5], QIXIS_READ(brdcfg[5]) & ~BRDCFG5_IRE);
360 
361 	brd_mux_lane_to_slot();
362 	select_i2c_ch_pca9547(I2C_MUX_CH_DEFAULT);
363 
364 	return 0;
365 }
366 
367 unsigned long get_board_sys_clk(void)
368 {
369 	u8 sysclk_conf = QIXIS_READ(brdcfg[1]);
370 #ifdef CONFIG_FSL_QIXIS_CLOCK_MEASUREMENT
371 	/* use accurate clock measurement */
372 	int freq = QIXIS_READ(clk_freq[0]) << 8 | QIXIS_READ(clk_freq[1]);
373 	int base = QIXIS_READ(clk_base[0]) << 8 | QIXIS_READ(clk_base[1]);
374 	u32 val;
375 
376 	val =  freq * base;
377 	if (val) {
378 		debug("SYS Clock measurement is: %d\n", val);
379 		return val;
380 	} else {
381 		printf("Warning: SYS clock measurement is invalid, ");
382 		printf("using value from brdcfg1.\n");
383 	}
384 #endif
385 
386 	switch (sysclk_conf & 0x0F) {
387 	case QIXIS_SYSCLK_83:
388 		return 83333333;
389 	case QIXIS_SYSCLK_100:
390 		return 100000000;
391 	case QIXIS_SYSCLK_125:
392 		return 125000000;
393 	case QIXIS_SYSCLK_133:
394 		return 133333333;
395 	case QIXIS_SYSCLK_150:
396 		return 150000000;
397 	case QIXIS_SYSCLK_160:
398 		return 160000000;
399 	case QIXIS_SYSCLK_166:
400 		return 166666666;
401 	}
402 	return 66666666;
403 }
404 
405 unsigned long get_board_ddr_clk(void)
406 {
407 	u8 ddrclk_conf = QIXIS_READ(brdcfg[1]);
408 #ifdef CONFIG_FSL_QIXIS_CLOCK_MEASUREMENT
409 	/* use accurate clock measurement */
410 	int freq = QIXIS_READ(clk_freq[2]) << 8 | QIXIS_READ(clk_freq[3]);
411 	int base = QIXIS_READ(clk_base[0]) << 8 | QIXIS_READ(clk_base[1]);
412 	u32 val;
413 
414 	val =  freq * base;
415 	if (val) {
416 		debug("DDR Clock measurement is: %d\n", val);
417 		return val;
418 	} else {
419 		printf("Warning: DDR clock measurement is invalid, ");
420 		printf("using value from brdcfg1.\n");
421 	}
422 #endif
423 
424 	switch ((ddrclk_conf & 0x30) >> 4) {
425 	case QIXIS_DDRCLK_100:
426 		return 100000000;
427 	case QIXIS_DDRCLK_125:
428 		return 125000000;
429 	case QIXIS_DDRCLK_133:
430 		return 133333333;
431 	}
432 	return 66666666;
433 }
434 
435 int misc_init_r(void)
436 {
437 	return 0;
438 }
439 
440 void ft_board_setup(void *blob, bd_t *bd)
441 {
442 	phys_addr_t base;
443 	phys_size_t size;
444 
445 	ft_cpu_setup(blob, bd);
446 
447 	base = getenv_bootm_low();
448 	size = getenv_bootm_size();
449 
450 	fdt_fixup_memory(blob, (u64)base, (u64)size);
451 
452 #ifdef CONFIG_PCI
453 	pci_of_setup(blob, bd);
454 #endif
455 
456 	fdt_fixup_liodn(blob);
457 	fdt_fixup_dr_usb(blob, bd);
458 
459 #ifdef CONFIG_SYS_DPAA_FMAN
460 	fdt_fixup_fman_ethernet(blob);
461 	fdt_fixup_board_enet(blob);
462 #endif
463 }
464