1*254887a5SShengzhou Liu# 2*254887a5SShengzhou Liu# Copyright 2013 Freescale Semiconductor, Inc. 3*254887a5SShengzhou Liu# 4*254887a5SShengzhou Liu# SPDX-License-Identifier: GPL-2.0+ 5*254887a5SShengzhou Liu# 6*254887a5SShengzhou Liu# Refer doc/README.pblimage for more details about how-to configure 7*254887a5SShengzhou Liu# and create PBL boot image 8*254887a5SShengzhou Liu# 9*254887a5SShengzhou Liu 10*254887a5SShengzhou Liu#PBI commands 11*254887a5SShengzhou Liu#Initialize CPC1 12*254887a5SShengzhou Liu09010000 00200400 13*254887a5SShengzhou Liu09138000 00000000 14*254887a5SShengzhou Liu091380c0 00000100 15*254887a5SShengzhou Liu#512KB SRAM 16*254887a5SShengzhou Liu09010100 00000000 17*254887a5SShengzhou Liu09010104 fff80009 18*254887a5SShengzhou Liu09010f00 08000000 19*254887a5SShengzhou Liu#enable CPC1 20*254887a5SShengzhou Liu09010000 80000000 21*254887a5SShengzhou Liu#Configure LAW for CPC1 22*254887a5SShengzhou Liu09000d00 00000000 23*254887a5SShengzhou Liu09000d04 fff80000 24*254887a5SShengzhou Liu09000d08 81000012 25*254887a5SShengzhou Liu#Initialize eSPI controller, default configuration is slow for eSPI to 26*254887a5SShengzhou Liu#load data, this configuration comes from u-boot eSPI driver. 27*254887a5SShengzhou Liu09110000 80000403 28*254887a5SShengzhou Liu09110020 2d170008 29*254887a5SShengzhou Liu09110024 00100008 30*254887a5SShengzhou Liu09110028 00100008 31*254887a5SShengzhou Liu0911002c 00100008 32*254887a5SShengzhou Liu#Errata for slowing down the MDC clock to make it <= 2.5 MHZ 33*254887a5SShengzhou Liu094fc030 00008148 34*254887a5SShengzhou Liu094fd030 00008148 35*254887a5SShengzhou Liu#Configure alternate space 36*254887a5SShengzhou Liu09000010 00000000 37*254887a5SShengzhou Liu09000014 ff000000 38*254887a5SShengzhou Liu09000018 81000000 39*254887a5SShengzhou Liu#Flush PBL data 40*254887a5SShengzhou Liu09138000 00000000 41*254887a5SShengzhou Liu091380c0 00000000 42