1 /* Copyright 2013 Freescale Semiconductor, Inc. 2 * 3 * SPDX-License-Identifier: GPL-2.0+ 4 */ 5 6 #include <common.h> 7 #include <console.h> 8 #include <environment.h> 9 #include <malloc.h> 10 #include <ns16550.h> 11 #include <nand.h> 12 #include <i2c.h> 13 #include <mmc.h> 14 #include <fsl_esdhc.h> 15 #include <spi_flash.h> 16 #include "../common/qixis.h" 17 #include "t208xqds_qixis.h" 18 #include "../common/spl.h" 19 20 DECLARE_GLOBAL_DATA_PTR; 21 22 phys_size_t get_effective_memsize(void) 23 { 24 return CONFIG_SYS_L3_SIZE; 25 } 26 27 unsigned long get_board_sys_clk(void) 28 { 29 u8 sysclk_conf = QIXIS_READ(brdcfg[1]); 30 31 switch (sysclk_conf & 0x0F) { 32 case QIXIS_SYSCLK_83: 33 return 83333333; 34 case QIXIS_SYSCLK_100: 35 return 100000000; 36 case QIXIS_SYSCLK_125: 37 return 125000000; 38 case QIXIS_SYSCLK_133: 39 return 133333333; 40 case QIXIS_SYSCLK_150: 41 return 150000000; 42 case QIXIS_SYSCLK_160: 43 return 160000000; 44 case QIXIS_SYSCLK_166: 45 return 166666666; 46 } 47 return 66666666; 48 } 49 50 unsigned long get_board_ddr_clk(void) 51 { 52 u8 ddrclk_conf = QIXIS_READ(brdcfg[1]); 53 54 switch ((ddrclk_conf & 0x30) >> 4) { 55 case QIXIS_DDRCLK_100: 56 return 100000000; 57 case QIXIS_DDRCLK_125: 58 return 125000000; 59 case QIXIS_DDRCLK_133: 60 return 133333333; 61 } 62 return 66666666; 63 } 64 65 void board_init_f(ulong bootflag) 66 { 67 u32 plat_ratio, sys_clk, ccb_clk; 68 ccsr_gur_t *gur = (void *)CONFIG_SYS_MPC85xx_GUTS_ADDR; 69 70 /* Memcpy existing GD at CONFIG_SPL_GD_ADDR */ 71 memcpy((void *)CONFIG_SPL_GD_ADDR, (void *)gd, sizeof(gd_t)); 72 73 /* Update GD pointer */ 74 gd = (gd_t *)(CONFIG_SPL_GD_ADDR); 75 76 console_init_f(); 77 78 /* initialize selected port with appropriate baud rate */ 79 sys_clk = get_board_sys_clk(); 80 plat_ratio = (in_be32(&gur->rcwsr[0]) >> 25) & 0x1f; 81 ccb_clk = sys_clk * plat_ratio / 2; 82 83 NS16550_init((NS16550_t)CONFIG_SYS_NS16550_COM1, 84 ccb_clk / 16 / CONFIG_BAUDRATE); 85 86 #if defined(CONFIG_SPL_MMC_BOOT) 87 puts("\nSD boot...\n"); 88 #elif defined(CONFIG_SPL_SPI_BOOT) 89 puts("\nSPI boot...\n"); 90 #elif defined(CONFIG_SPL_NAND_BOOT) 91 puts("\nNAND boot...\n"); 92 #endif 93 94 relocate_code(CONFIG_SPL_RELOC_STACK, (gd_t *)CONFIG_SPL_GD_ADDR, 0x0); 95 } 96 97 void board_init_r(gd_t *gd, ulong dest_addr) 98 { 99 bd_t *bd; 100 101 bd = (bd_t *)(gd + sizeof(gd_t)); 102 memset(bd, 0, sizeof(bd_t)); 103 gd->bd = bd; 104 bd->bi_memstart = CONFIG_SYS_INIT_L3_ADDR; 105 bd->bi_memsize = CONFIG_SYS_L3_SIZE; 106 107 arch_cpu_init(); 108 get_clocks(); 109 mem_malloc_init(CONFIG_SPL_RELOC_MALLOC_ADDR, 110 CONFIG_SPL_RELOC_MALLOC_SIZE); 111 gd->flags |= GD_FLG_FULL_MALLOC_INIT; 112 113 #ifdef CONFIG_SPL_NAND_BOOT 114 nand_spl_load_image(CONFIG_ENV_OFFSET, CONFIG_ENV_SIZE, 115 (uchar *)CONFIG_ENV_ADDR); 116 #endif 117 #ifdef CONFIG_SPL_MMC_BOOT 118 mmc_initialize(bd); 119 mmc_spl_load_image(CONFIG_ENV_OFFSET, CONFIG_ENV_SIZE, 120 (uchar *)CONFIG_ENV_ADDR); 121 #endif 122 #ifdef CONFIG_SPL_SPI_BOOT 123 fsl_spi_spl_load_image(CONFIG_ENV_OFFSET, CONFIG_ENV_SIZE, 124 (uchar *)CONFIG_ENV_ADDR); 125 #endif 126 127 gd->env_addr = (ulong)(CONFIG_ENV_ADDR); 128 gd->env_valid = ENV_VALID; 129 130 i2c_init_all(); 131 132 dram_init(); 133 134 #ifdef CONFIG_SPL_MMC_BOOT 135 mmc_boot(); 136 #elif defined(CONFIG_SPL_SPI_BOOT) 137 fsl_spi_boot(); 138 #elif defined(CONFIG_SPL_NAND_BOOT) 139 nand_boot(); 140 #endif 141 } 142