xref: /openbmc/u-boot/board/freescale/t208xqds/README (revision cac4d6a6) 
1The T2080QDS is a high-performance computing evaluation, development and
2test platform supporting the T2080 QorIQ Power Architecture processor.
3
4T2080 SoC Overview
5------------------
6The T2080 QorIQ multicore processor combines four dual-threaded e6500 Power
7Architecture processor cores with high-performance datapath acceleration
8logic and network and peripheral bus interfaces required for networking,
9telecom/datacom, wireless infrastructure, and mil/aerospace applications.
10
11T2080 includes the following functions and features:
12 - Four dual-threads 64-bit Power architecture e6500 cores, up to 1.8GHz
13 - 2MB L2 cache and 512KB CoreNet platform cache (CPC)
14 - Hierarchical interconnect fabric
15 - One 32-/64-bit DDR3/3L SDRAM memory controllers with ECC and interleaving
16 - Data Path Acceleration Architecture (DPAA) incorporating acceleration
17 - 16 SerDes lanes up to 10.3125 GHz
18 - 8 Ethernet interfaces, supporting combinations of the following:
19   - Up to four 10 Gbps Ethernet MACs
20   - Up to eight 1 Gbps Ethernet MACs
21   - Up to four 2.5 Gbps Ethernet MACs
22 - High-speed peripheral interfaces
23   - Four PCI Express controllers (two PCIe 2.0 and two PCIe 3.0 with SR-IOV)
24   - Two Serial RapidIO 2.0 controllers/ports running at up to 5 GHz
25 - Additional peripheral interfaces
26   - Two serial ATA (SATA 2.0) controllers
27   - Two high-speed USB 2.0 controllers with integrated PHY
28   - Enhanced secure digital host controller (SD/SDHC/SDXC/eMMC)
29   - Enhanced serial peripheral interface (eSPI)
30   - Four I2C controllers
31   - Four 2-pin UARTs or two 4-pin UARTs
32   - Integrated Flash Controller supporting NAND and NOR flash
33 - Three eight-channel DMA engines
34 - Support for hardware virtualization and partitioning enforcement
35 - QorIQ Platform's Trust Architecture 2.0
36
37Differences between T2080 and T2081
38-----------------------------------
39  Feature		T2080	 T2081
40  1G Ethernet numbers:  8	 6
41  10G Ethernet numbers: 4	 2
42  SerDes lanes:		16	 8
43  Serial RapidIO,RMan:  2	 no
44  SATA Controller:	2	 no
45  Aurora:		yes	 no
46  SoC Package:		896-pins 780-pins
47
48
49T2080QDS feature overview
50-------------------------
51Processor:
52 - T2080 SoC integrating four 64-bit dual-threads e6500 cores up to 1.8GHz
53Memory:
54 - Single memory controller capable of supporting DDR3 and DDR3-LV devices
55 - Two DDR3 DIMMs up to 4GB, Dual rank @ 2133MT/s and ECC support
56Ethernet interfaces:
57 - Two 1Gbps RGMII on-board ports
58 - Four 10Gbps XFI on-board cages
59 - 1Gbps/2.5Gbps SGMII Riser card
60 - 10Gbps XAUI Riser card
61Accelerator:
62 - DPAA components consist of FMan, BMan, QMan, PME, DCE and SEC
63SerDes:
64 - 16 lanes up to 10.3125GHz
65 - Supports Aurora debug, PEX, SATA, SGMII, sRIO, HiGig, XFI and XAUI
66IFC:
67 - 128MB NOR Flash, 512MB NAND Flash, PromJet debug port and FPGA
68eSPI:
69 - Three SPI flash (16MB N25Q128A + 16MB EN25S64 + 512KB SST25WF040)
70USB:
71 - Two USB2.0 ports with internal PHY (one Type-A + one micro Type-AB)
72PCIE:
73 - Four PCI Express controllers (two PCIe 2.0 and two PCIe 3.0 with SR-IOV)
74SATA:
75 - Two SATA 2.0 ports on-board
76SRIO:
77 - Two Serial RapidIO 2.0 ports up to 5 GHz
78eSDHC:
79 - Supports SD/SDHC/SDXC/eMMC Card
80I2C:
81 - Four I2C controllers.
82UART:
83 - Dual 4-pins UART serial ports
84System Logic:
85 - QIXIS-II FPGA system controll
86Debug Features:
87 - Support Legacy, COP/JTAG, Aurora, Event and EVT
88XFI:
89 - XFI is supported on T2080QDS through Lane A/B/C/D on Serdes 1 routed to
90 a on-board SFP+ cages, which to house optical module (fiber cable) or
91 direct attach cable(copper), the copper cable is used to emulate
92 10GBASE-KR scenario.
93 So, for XFI usage, there are two scenarios, one will use fiber cable,
94 another will use copper cable. An hwconfig env "fsl_10gkr_copper" is
95 introduced to indicate a XFI port will use copper cable, and U-Boot
96 will fixup the dtb accordingly.
97 It's used as: fsl_10gkr_copper:<10g_mac_name>
98 The <10g_mac_name> can be fm1_10g1, fm1_10g2, fm1_10g3, fm1_10g4, they
99 do not have to be coexist in hwconfig. If a MAC is listed in the env
100 "fsl_10gkr_copper", it will use copper cable, otherwise, fiber cable
101 will be used by default.
102 for ex. set "fsl_10gkr_copper:fm1_10g1,fm1_10g2,fm1_10g3,fm1_10g4" in
103 hwconfig, then both four XFI ports will use copper cable.
104 set "fsl_10gkr_copper:fm1_10g1,fm1_10g2" in hwconfig, then first two
105 XFI ports will use copper cable, the other two XFI ports will use fiber
106 cable.
1071000BASE-KX(1G-KX):
108 - T2080QDS can support 1G-KX by using SGMII protocol, but serdes lane
109 runs in 1G-KX mode. By default, the lane runs in SGMII mode, to set a lane
110 in 1G-KX mode, need to set corresponding bit in SerDes Protocol Configuration
111 Register 1 (PCCR1), and U-Boot fixup the dtb for kernel to do proper
112 initialization.
113 Hwconfig "fsl_1gkx" is used to indicate a lane runs in 1G-KX mode, MAC
114 1/2/5/6/9/10 are available for 1G-KX, MAC 3/4 run in RGMII mode. To set a
115 MAC to use 1G-KX mode, set its' corresponding env in "fsl_1gkx", 'fm1_1g1'
116 stands for MAC 1, 'fm1_1g2' stands for MAC 2, etc.
117 For ex. set "fsl_1gkx:fm1_1g1,fm1_1g2,fm1_1g5,fm1_1g6,fm1_1g9,fm1_1g10" in
118 hwconfig, MAC 1/2/5/6/9/10 will use 1G-KX mode.
119
120System Memory map
121----------------
122
123Start Address  End Address      Description			Size
1240xF_FFDF_0000  0xF_FFDF_0FFF    IFC - CPLD			4KB
1250xF_FF80_0000  0xF_FF80_FFFF    IFC - NAND Flash		64KB
1260xF_FE00_0000  0xF_FEFF_FFFF    CCSRBAR				16MB
1270xF_F803_0000  0xF_F803_FFFF    PCI Express 4 I/O Space		64KB
1280xF_F802_0000  0xF_F802_FFFF    PCI Express 3 I/O Space		64KB
1290xF_F801_0000  0xF_F801_FFFF    PCI Express 2 I/O Space		64KB
1300xF_F800_0000  0xF_F800_FFFF    PCI Express 1 I/O Space		64KB
1310xF_F600_0000  0xF_F7FF_FFFF    Queue manager software portal	32MB
1320xF_F400_0000  0xF_F5FF_FFFF    Buffer manager software portal	32MB
1330xF_E800_0000  0xF_EFFF_FFFF    IFC - NOR Flash			128MB
1340xF_0000_0000  0xF_003F_FFFF    DCSR				4MB
1350xC_4000_0000  0xC_4FFF_FFFF    PCI Express 4 Mem Space		256MB
1360xC_3000_0000  0xC_3FFF_FFFF    PCI Express 3 Mem Space		256MB
1370xC_2000_0000  0xC_2FFF_FFFF    PCI Express 2 Mem Space		256MB
1380xC_0000_0000  0xC_1FFF_FFFF    PCI Express 1 Mem Space		512MB
1390x0_0000_0000  0x0_ffff_ffff    DDR				4GB
140
141
142128M NOR Flash memory Map
143-------------------------
144Start Address   End Address	Definition			Max size
1450xEFF40000	0xEFFFFFFF	U-Boot (current bank)		768KB
1460xEFF20000	0xEFF3FFFF	U-Boot env (current bank)	128KB
1470xEFF00000	0xEFF1FFFF	FMAN Ucode (current bank)	128KB
1480xED300000	0xEFEFFFFF	rootfs (alt bank)		44MB
1490xEC800000	0xEC8FFFFF	Hardware device tree (alt bank)	1MB
1500xEC020000	0xEC7FFFFF	Linux.uImage (alt bank)		7MB + 875KB
1510xEC000000	0xEC01FFFF	RCW (alt bank)			128KB
1520xEBF40000	0xEBFFFFFF	U-Boot (alt bank)		768KB
1530xEBF20000	0xEBF3FFFF	U-Boot env (alt bank)		128KB
1540xEBF00000	0xEBF1FFFF	FMAN ucode (alt bank)		128KB
1550xE9300000	0xEBEFFFFF	rootfs (current bank)		44MB
1560xE8800000	0xE88FFFFF	Hardware device tree (cur bank)	1MB
1570xE8020000	0xE86FFFFF	Linux.uImage (current bank)	7MB + 875KB
1580xE8000000	0xE801FFFF	RCW (current bank)		128KB
159
160
161
162Software configurations and board settings
163------------------------------------------
1641. NOR boot:
165   a. build NOR boot image
166	$  make T2080QDS_config
167	$  make
168   b. program u-boot.bin image to NOR flash
169	=> tftp 1000000 u-boot.bin
170	=> pro off all;era eff40000 efffffff;cp.b 1000000 eff40000 $filesize
171	set SW1[1:8] = '00010011', SW2[1] = '1', SW6[1:4] = '0000' for NOR boot
172
173   Switching between default bank0 and alternate bank4 on NOR flash
174   To change boot source to vbank4:
175	by software:   run command 'qixis_reset altbank' in U-Boot.
176	by DIP-switch: set SW6[1:4] = '0100'
177
178   To change boot source to vbank0:
179	by software:   run command 'qixis_reset' in U-Boot.
180	by DIP-Switch: set SW6[1:4] = '0000'
181
1822. NAND Boot:
183   a. build PBL image for NAND boot
184	$ make T2080QDS_NAND_config
185	$ make
186   b. program u-boot-with-spl-pbl.bin to NAND flash
187	=> tftp 1000000 u-boot-with-spl-pbl.bin
188	=> nand erase 0 $filesize
189	=> nand write 1000000 0 $filesize
190	set SW1[1:8] = '10000010', SW2[1] = '0' and SW6[1:4] = '1001' for NAND boot
191
1923. SPI Boot:
193   a. build PBL image for SPI boot
194	$ make T2080QDS_SPIFLASH_config
195	$ make
196   b. program u-boot-with-spl-pbl.bin to SPI flash
197	=> tftp 1000000 u-boot-with-spl-pbl.bin
198	=> sf probe 0
199	=> sf erase 0 f0000
200	=> sf write 1000000 0 $filesize
201	set SW1[1:8] = '00100010', SW2[1] ='1' for SPI boot
202
2034. SD Boot:
204   a. build PBL image for SD boot
205	$ make T2080QDS_SDCARD_config
206	$ make
207   b. program u-boot-with-spl-pbl.bin to SD/MMC card
208	=> tftp 1000000 u-boot-with-spl-pbl.bin
209	=> mmc write 1000000 8 0x800
210	=> tftp 1000000 fsl_fman_ucode_T2080_xx.bin
211	=> mmc write 1000000 0x820 80
212	set SW1[1:8] = '00100000', SW2[1] = '0' for SD boot
213
214
2152-stage NAND/SPI/SD boot loader
216-------------------------------
217PBL initializes the internal CPC-SRAM and copy SPL(160K) to SRAM.
218SPL further initializes DDR using SPD and environment variables
219and copy U-Boot(768 KB) from NAND/SPI/SD device to DDR.
220Finally SPL transers control to U-Boot for futher booting.
221
222SPL has following features:
223 - Executes within 256K
224 - No relocation required
225
226Run time view of SPL framework
227-------------------------------------------------
228|Area		   | Address			|
229-------------------------------------------------
230|SecureBoot header | 0xFFFC0000 (32KB)		|
231-------------------------------------------------
232|GD, BD		   | 0xFFFC8000 (4KB)		|
233-------------------------------------------------
234|ENV		   | 0xFFFC9000 (8KB)		|
235-------------------------------------------------
236|HEAP		   | 0xFFFCB000 (50KB)		|
237-------------------------------------------------
238|STACK		   | 0xFFFD8000 (22KB)		|
239-------------------------------------------------
240|U-Boot SPL	   | 0xFFFD8000 (160KB)		|
241-------------------------------------------------
242
243NAND Flash memory Map on T2080QDS
244--------------------------------------------------------------
245Start		End		Definition	Size
2460x000000	0x0FFFFF	U-Boot img	1MB  (2 blocks)
2470x100000	0x17FFFF	U-Boot env	512KB (1 block)
2480x180000	0x1FFFFF	FMAN ucode	512KB (1 block)
249
250
251Micro SD Card memory Map on T2080QDS
252----------------------------------------------------
253Block		#blocks		Definition	Size
2540x008		2048		U-Boot img	1MB
2550x800		0016		U-Boot env	8KB
2560x820		0128		FMAN ucode	64KB
257
258
259SPI Flash memory Map on T2080QDS
260----------------------------------------------------
261Start		End		Definition	Size
2620x000000	0x0FFFFF	U-Boot img	1MB
2630x100000	0x101FFF	U-Boot env	8KB
2640x110000	0x11FFFF	FMAN ucode	64KB
265
266
267How to update the ucode of Freescale FMAN
268-----------------------------------------
269=> tftp 1000000 fsl_fman_ucode_t2080_xx.bin
270=> pro off all;erase 0xeff00000 0xeff1ffff;cp 1000000 0xeff00000 $filesize
271
272
273For more details, please refer to T2080QDS User Guide and access
274website www.freescale.com and Freescale QorIQ SDK Infocenter document.
275